KR100898684B1 - Flash memory device and program method thereof - Google Patents

Abstract

According to an embodiment of the present invention, an erase operation is performed on memory cells, a first program operation is performed such that threshold voltage distributions of first and second memory cells are at a level of a first state, among memory cells. The second program may be configured such that the threshold voltage distributions of the second memory cells become a second state having a higher level than the first state, and at the same time, the threshold voltage distributions of the third memory cells become a third state having a higher level than the second state. And a method of programming a flash memory device comprising the step of performing an operation.

Multi-Level Cells, Programs, Thresholds, Bitlines, Page Buffers, Voltage Differences

Description

Flash memory device and program method thereof

1A to 1D are diagrams for describing a program method of a conventional flash memory device.

2 is a circuit diagram illustrating a program method of a flash memory device of the present invention.

FIG. 3 is a circuit diagram for describing an operation of the page buffer of FIG. 2.

4 is a circuit diagram illustrating a part of FIG. 2 to describe a method of programming a flash memory device of the present invention.

5A through 5F are diagrams for sequentially describing a program method of a flash memory device of the present invention.

6 is a graph for comparing the number of programs of a flash memory device between the present invention and the prior art.

<Explanation of symbols for the main parts of the drawings>

100: memory cell array 110: selected page

S0 ~ Sk: String BL0 ~ BLk, BL, BLe, BLo: Bit line

WL0 ~ WLn: Word line PB: Page buffer

The present invention relates to a flash memory device and a program method thereof, and more particularly, to a flash memory device and a program method thereof capable of improving a program speed.

In general, a flash memory device includes a gate insulating film, a floating gate, a dielectric film, and a control gate stacked on a semiconductor substrate. Among these, the floating gate is used as a charge storage layer, which will be described in detail as follows.

When a program voltage is applied to the control gate through the selected word line, a Fowler-Nordheim (F-N) tunneling phenomenon occurs between the semiconductor substrate and the floating gate, and thus electrons flow from the semiconductor substrate into the floating gate to perform a program operation.

The floating gate, in which the electrons are stored, becomes a programmed cell, which is higher than the threshold voltage of the erase cell. The floating gate may be distinguished from the erase cell and the program cell by reading the difference in the threshold voltage distribution.

In general, a flash memory device has two states, an erase state or a program state. An element driven in one erase state and one program state is called a single level chip (SLC). . On the other hand, in order to store a large amount of data than the SLC has been developed a method for programming each memory cell to a multi-level, which is called a multi-level chip (hereinafter referred to as MLC). The MLC operates by defining a different data state for each threshold voltage section having a different distribution section. Specifically, it is as follows.

For example, when storing data in the MLC, a state that a memory cell can have is divided into an erase state, a PV1 state, a PV2 state, and a PV3 state. Here, when the PV1 state is programmed as the lowest interval among the programmed threshold voltage sections, the PV2 state is divided into a state where the threshold voltage distribution is higher than that of the PV1 state, and the PV3 state is divided into a state where the threshold voltage distribution is higher than the PV2 state. Can be. As such, multi-bit data (eg, 11, 01, 00, and 01) may be sequentially defined for each threshold voltage section. Reference will be made to FIG. 1.

1A to 1D are diagrams for describing a program method of a conventional flash memory device. Each threshold voltage section that a memory cell may have is divided into an erased state, a PV1 state, a PV2 state, and a PV3 state, and data values of 2 bits (multi-bits) are defined in each of them. The lower bit of the 2-bit data value is called a low page and the upper bit is called a high page. Among these, the low page program operation is referred to as a low page program (hereinafter referred to as LSB program), and the high page program operation is referred to as high page program (hereinafter referred to as MSB program).

The program sequence of MLC is as follows.

First, in a memory cell array configured in block units, all memory cells of a selected block are erased (FIG. 1A). Next, the LSB program operation is performed. In the LSB program operation, a ground voltage is applied to a bit line of selected memory cells among memory cells in an erased state, and a power supply voltage is applied to a bit line of unselected memory cells. The LSB program operation is performed by applying a program voltage to the selected word line and applying a pass voltage to the unselected word lines. As a result of the LSB program operation, the selected memory cell is in the PV1 state (Fig. 1B).

The MSB program operation may be divided into a first MSB program operation and a second MSB program operation.

The first MSB program operation is an operation of programming the selected memory cell to the PV2 state. In order to program the memory cell in the erased state to the PV2 state, the selected memory cell is LSB programmed from the erased state to the PV1 state, and then the first MSB program is executed to make the selected memory cell into the PV2 state (FIG. 1C).

The second MSB program operation is an operation of programming the selected memory cell to the PV3 state (FIG. 1D). The second MSB program is performed by applying a ground voltage to the bit lines of selected memory cells among the erased memory cells and applying a program voltage to a word line connected to the selected memory cell.

As described above, the program operation speed of the MLC may be slowed down because the MLC program needs to perform program operation corresponding to each program state (PV1, PV2, or PV3 state) in the erase state.

According to the present invention, in a program operation of a multi-level chip having various program threshold voltage sections, a program operation having different threshold voltage sections is simultaneously performed by applying different voltages corresponding to threshold voltages to bit lines. As a result, the number of program operations can be reduced, thereby reducing the program operating time.

A program method of a flash memory device according to an embodiment of the present disclosure performs an erase operation on memory cells. Among the memory cells, a first program operation may be performed such that threshold voltage distributions of the first memory cells and the second memory cells become a level of the first state. The second memory cell of the memory cells is connected between the bit line and the voltage supply line by using a program element that transfers a positive voltage to the bit line when a second turn on voltage having a level lower than the first turn on voltage is applied to the gate. Performing a second program operation so that the threshold voltage distributions of the third memory cells are at a level higher than the first state and at the same time the threshold voltage distributions of the third memory cells are at a level higher than the second state. The program method of the flash memory device comprising a.

The first program operation is performed by a low bit program operation.

When the erase state is '11', the first state is '10', the second state is '00', and the third state is '01'.

The second program operation may be performed by applying a ground voltage to the bit lines electrically connected to the third memory cells and applying a positive voltage to the bit lines electrically connected to the second memory cells.

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The positive voltage is applied at a voltage equal to the difference between the threshold voltage in the second state and the threshold voltage in the third state.

According to another aspect of the present invention, a method of programming a flash memory device may include applying a first voltage to a word line of a selected page, and supplying a power voltage and a ground voltage to bit lines connected to memory cells included in the page, respectively. Alternatively, each of the positive voltages may be applied so that the memory cells included in the page have different threshold voltage distribution intervals according to the voltage level applied to the bit line, and are connected between the bit line and the voltage supply line, and are connected to the gate. When a second turn-on voltage of a level lower than the turn-on voltage is applied, the program method of the flash memory device may include performing a program operation by using a program element that transfers a positive voltage to a bit line.

Among the memory cells, the first memory cells connected to the bit lines to which the power supply voltage is applied maintain the threshold voltage distribution interval of the previous state, and the second memory cells connected to the bit lines to which the positive voltage is applied are selected among the memory cells. The third memory cells that are programmed to have a threshold voltage distribution section in two states and among the memory cells that are connected to bit lines to which a ground voltage is applied are programmed to have a threshold voltage distribution section in a third state.

The positive voltage is higher than the ground voltage and lower than the supply voltage.

The first memory cells maintain an erase state or a threshold voltage distribution period of the first state.

The threshold voltage distribution section of the second state is higher than the threshold voltage distribution section of the first state and lower than the threshold voltage distribution section of the third state.

The flash memory device according to the present invention includes a bit line. A voltage supply line. A program element connected between the bit line and the voltage supply line and configured to transfer a positive voltage to the bit line when a second turn-on voltage having a level lower than the first turn-on voltage is applied to the gate.

The second turn-on voltage is lower than the first turn-on voltage, but is applied at a voltage level at which the program element can be turned on.

The positive voltage is a level between the supply voltage and the ground voltage, and the program element is implemented with an NMOS transistor.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 is a circuit diagram illustrating a program method of a flash memory device of the present invention.

2 is a circuit diagram illustrating one cell block 100 constituting a memory cell array and a page buffer PB connected thereto. The cell block 100 includes a plurality of strings S0 to Sk. Each of the strings includes a drain select transistor (DST), memory cells F0 to Fn, and a source select transistor (SST) connected in series. Each drain select transistor DST is connected to each of the bit lines BL0 to BLk to transfer and receive the voltage of the page buffer PB to the strings S0 to Sk. Each source select transistor SST is connected to a common source line CSL. The plurality of memory cells F0 to Fn are arranged in series between the drain select transistor DST and the source select transistor SST.

The gate electrode of the drain select transistor DST shares the drain select line DSL. Each gate electrode of the source select transistor SST is connected to share the source select line SSL.

The page buffer PB transfers the voltage corresponding to each operation to the bit lines during the program and erase operations, and transmits the voltages corresponding to the respective operations to the bit lines, and during the read operation, the bit lines BL0. To BLk).

In the present invention, the page buffer PB is a third voltage that is a voltage between the first voltage and the second voltage in addition to the first voltage (for example, 0V) and the second voltage (for example, Vcc) generated during a general program operation. Further generates voltage Vd. The third voltage Vd is a positive voltage between the first voltage and the second voltage, which will be described with reference to FIGS. 3A and 3B.

FIG. 3 is a circuit diagram for describing an operation of the page buffer of FIG. 2.

Referring to FIG. 3, the page buffer PB used in the present invention is a page buffer PB which further generates the above-mentioned third voltage, but the configuration is similar to that of a general page buffer PB. However, the voltage of any one of the first to third voltages is changed from the page buffer PB to the bit line BL by adjusting the turn on voltage of some of the devices configuring the page buffer PB. Can optionally be delivered. Accordingly, the page buffer PB will be briefly described with reference to the following drawings for the convenience of understanding.

The page buffer PB includes a selection circuit 32 for selecting a plurality of bit lines, and has a dual latch structure.

Specifically, the precharge device P1 may be implemented as a PMOS transistor that operates in response to the precharge signal PRECHb, and is connected between the power supply voltage Vcc and the sensing node SO. The program element P2 operates in response to the program signal PGM and is connected between the sensing node SO and the first node E1. The first control element P3 and the second control element P4 are connected in series between the second node E2 and the ground Vss, and the first control element P3 is connected to the potential of the sensing node SO. In response, the second control element P4 operates in response to the first latch signal LAT1. The first reset device P5 operates in response to the first reset signal RST1 and is connected between the first node E1 and the ground Vss. The first latch 33 is connected between the first node E1 and the second node E2 and consists of two inverters I3 and I4. The transfer element P6 operates in response to the transfer signal PDUMP and is connected between the sensing node SO and the third node E3. The third control element P7 and the fourth control element P8 are connected in series between the third node E3 and the ground Vss, and the third control element P7 is a potential applied to the sensing node SO. The fourth control element P8 operates in response to the second latch signal LAT2. The second reset device P9 operates in response to the second reset signal RST2 and is connected between the fourth node E4 and the ground Vss. The second latch 34 is connected between the third node E3 and the fourth node E4 and consists of two inverters I5 and I6. Data input to the second latch 34 is stored according to the operations of the first input element P10 and the second input element P11. The first input element P10 operates in response to the first input signal DI and is connected between the fourth node E4 and the fifth node E5. The second input element P11 operates in response to the second input signal nDI and is connected between the third node E3 and the fifth node E5. The input / output device P12 operates in response to the input / output signal PBDO and is connected between the first node E1 and the fifth node E5, and the fifth node E5 is connected to the input / output line DIO.

The selection circuit 32 includes an even charging device P13, an odd charging device P14, an even selection device P15, and an odd selection device for connecting the bit lines BLe and BLo and the page buffer PB. P16). The even charging device P13 and the odd charging device P14 are connected in series between the bit lines BLe and BLo through the sixth node E6. The even charging device P13 operates in response to the even charging signal DISCHe and is connected between the even bit line BLe and the sixth node E6, and the odd charging device P14 is connected to the odd charge signal DISCHo. It operates in response and is connected between the odd bit line BLo and the sixth node E6. The charge voltage VIRPWR is applied to the sixth node E6. The even selection device P15 operates in response to the even selection signal BSLe and connects the sensing node SO and the even bit line BLe. The odd selection element P16 operates in response to the odd selection signal BSLo to connect the sensing node SO and the odd bit line BLo.

In the program operation, when the program signal PGM is activated, the program element P2 is turned on to transmit the voltage of the first latch 33 to the sensing node SO. The voltage transferred to the sensing node SO is transferred to the even bit line BLe or the odd bit line BLO through the even selection element P15 or the odd selection element P16 of the selection circuit 32.

On the other hand, in the case where the third voltage is transmitted to the even or odd bit line BLe or BLo, the bit is turned on by weakly turning on the program element P2 and activating the selected selection signal BSLe or BSLo. A third voltage that is a positive voltage between the first voltage and the second voltage may be output to the line. Alternatively, even when the program signal PGM is activated and the selected selection signal BSLe or BSLo is weakly turned on, the third voltage may be output to the bit line BLe or BLo. In this case, it is preferable to perform the program operation in the state where the potential of the bit line BLe or BLo is 0V.

Next, the program method of the present invention will be specifically described by taking any one page 110 of FIG. 2 as an example.

4 is a circuit diagram illustrating a part of FIG. 2 to describe a method of programming a flash memory device of the present invention. Among the memory cells 0F ₀ to kF ₀ of the selected page 110, the zeroth cell 0F ₀ is in an erased state, the first cell 1F ₀ is in a PV1 state, and the second cell 2F ₀ is in an erased state. For example, the PV2 state, the third cell 3F ₀ is in the PV3 state, and the kth cell kF ₀ is programmed in the PV2 state. At this time, the erase state, PV1 state, PV2 state and PV3 state is generally divided into 11, 10, 00, and 01, but this can be changed according to the definition, so in the present invention erase state, PV1 in the order of increasing the threshold voltage The program status is defined by the status, PV2 status and PV3 status. An example thereof will be described below with reference to FIGS. 5A to 5F.

5A through 5F are diagrams for sequentially describing a program method of a flash memory device of the present invention.

Referring to FIG. 5A, before performing a program operation, an erase operation may be performed in a cell block unit so that memory cells (all memory cells of a cell block including 0F ₀ to kF ₀ ) are erased. Be sure to The erase operation may be performed by applying a first voltage (for example, 0V) to the selected word line WL0 and connecting a second voltage (for example, Vcc) to all of the bit lines BL0 to BLk. According to the erase operation, the threshold voltage distribution is set to the erased state (Fig. 5B).

Referring to FIG. 5C, a first program operation, which is an LSB program operation, is performed to program the first cell 1F ₀ to be a second memory cell having a PV1 state. At this time, the LSB program operation is simultaneously performed on the second and k-th cells 2F ₀ and kF ₀ to be programmed to the PV2 state to make the PV1 state.

Specifically, in the LSB program, a program voltage is applied to the selected word line WL0 and a first voltage (for example, 0V) is applied to the selected bit lines BL1, BL2, and BLk, but the bit lines are not selected. A second voltage (for example, Vcc) is applied to BL0 and BL3. As a result, the zeroth cell 0F ₀ remains in the erased state, and the first cell 1F ₀ , the second cell 2F ₀ , and the kth cell kF ₀ are in the PV1 state (FIG. 5D).

Referring to FIG. 5E, the third cell 3F ₀ is brought into the PV3 state by performing a second program operation, which is an MSB program, and simultaneously the second cell 2F ₀ and the k th cell kF ₀ are turned into the PV2 state. Program with Specifically, it is as follows.

Applying a program voltage to a selected word line (WL0), and the third cell (3F ₀₎ and a bit line (BL3) connected to a first voltage (e.g., 0V) for application to a third cell (3F ₀₎ PV3 Program to state. At the same time, a third voltage Vd is applied to the bit line BL2 connected to the second cell 2F ₀ to program the PV2 state having a threshold voltage distribution higher than the PV1 state and lower than the PV3 state (FIG. 5F). .

At this time, when the verifiable voltage of the PV1 state is called Va, the verifiable voltage of the PV2 state is called Vb, and the verifiable voltage of the PV3 state is called Vc, the third voltage Vd is equal to the voltage difference between Vc and Vb. It is preferable to apply. This is because the threshold voltage distribution of the PV2 state should be distributed between the threshold voltages of the PV1 state and the PV3 state.

There are a number of factors that determine the threshold voltage distribution, but mainly depends on the amount of electrons stored in the floating gate. The amount of electrons stored in the floating gate may be determined by the voltage difference between the word line and the semiconductor substrate. Specifically, it is as follows.

If the program voltage is applied to the word line and the channel of the semiconductor substrate is applied to the ground voltage through the bit line, a coupling phenomenon occurs between the control gate and the floating gate by the program voltage. This coupling phenomenon induces a tunneling phenomenon in which electrons can flow from the semiconductor substrate to the floating gate, and the threshold voltage of the programmed cell varies according to the amount of the tunneled electrons. Therefore, an important factor determining the threshold voltage of a program cell may be a voltage difference between a program voltage applied to a word line and a voltage applied to a bit line. This will be described in detail with reference to the graph as follows.

6 is a graph for comparing the number of programs of a flash memory device between the present invention and the prior art.

Referring to FIG. 6, the x-axis of the graph represents the number of programs and the y-axis represents a threshold voltage. In the prior art, in order to program the PV3 state, the program operation (a) reaching the PV2 state must be performed, and then the program operation (b) which can be made into the PV3 state by increasing the threshold voltage must be further performed.

However, in the present invention, by applying the voltage Vd equal to the threshold voltage difference between the PV3 state and the PV2 state simultaneously to the bit line connected to the cell to be programmed in the PV2 state, the program of the PV3 state and the PV2 state is performed in one program operation (A). This can reduce the program run time.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, during a program operation of a multi-level chip having a plurality of threshold voltage sections, a program operation having different threshold voltage sections may be simultaneously performed by applying different voltages corresponding to threshold voltages to bit lines. As a result, the number of program operations can be reduced, thereby reducing the program operation time.

Claims (16)

Performing an erase operation on the memory cells; Performing a first program operation such that threshold voltage distributions of first and second memory cells among the memory cells are at a level of a first state; And By using a program element connected between the bit line and the voltage supply line and transferring a positive voltage to the bit line when a second turn-on voltage having a level lower than the first turn-on voltage is applied to the gate, Among the memory cells, the threshold voltage distribution of the second memory cells is set to a second state of a higher level than the first state, and at the same time, the threshold voltage distribution of the third memory cells is of a higher level than the second state. And performing a second program operation so as to be in a tristate. The method of claim 1, And said first program operation is a low bit program operation. The method of claim 1, When the erase state is '11', the first state is '10', the second state is '00', and the third state is '01'. The method of claim 1, And the first memory cells, the second memory cells and the third memory cells are different memory cells. The method of claim 1, The second program operation is performed by applying a ground voltage to a bit line electrically connected to the third memory cells, and applying a positive voltage to the bit line electrically connected to the second memory cells. delete The method of claim 1, And the positive voltage is applied at a voltage equal to a difference between the threshold voltage of the second state and the threshold voltage of the third state. Applying a first voltage to a word line of a selected page, By applying a power supply voltage, a ground voltage, or a positive voltage to bit lines respectively connected to the memory cells included in the page, the threshold voltages of the memory cells included in the page are different from each other according to a voltage level applied to the bit line. Have a distribution interval, Performing a program operation by using a program element connected between the bit line and the voltage supply line and transferring a positive voltage to the bit line when a second turn on voltage having a level lower than a first turn on voltage is applied to a gate; Program method of a flash memory device comprising. The method of claim 8, Among the memory cells, first memory cells connected to bit lines to which the power supply voltage is applied maintain a threshold voltage distribution period in a previous state. Among the memory cells, second memory cells connected to the bit lines to which the positive voltage is applied are programmed to have a threshold voltage distribution period in a second state. And among the memory cells, third memory cells connected to bit lines to which the ground voltage is applied are programmed to have a threshold voltage distribution section in a third state. The method of claim 8, And the positive voltage is higher than the ground voltage and lower than the power supply voltage. The method of claim 9, And the first memory cells maintain an erase state or a threshold voltage distribution period of the first state. The method of claim 11, The threshold voltage distribution section of the second state is higher than the threshold voltage distribution section of the first state and is lower than the threshold voltage distribution section of the third state. Bitline; Voltage supply line; And And a program device connected between the bit line and the voltage supply line and transferring a positive voltage to the bit line when a second turn-on voltage having a level lower than a first turn-on voltage is applied to a gate. The method of claim 13, The second turn on voltage is lower than the first turn on voltage, but is applied to a voltage level at which the program device can be turned on. The method of claim 13, And the positive voltage is a level between a power supply voltage and a ground voltage. The method according to any one of claims 1, 8 or 13, The program device is a flash memory device implemented as an NMOS transistor.

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