KR20100027785A - Bitline sensing unit of non volatile memory device and erasing method using that - Google Patents

Abstract

The bit line sensing unit of the nonvolatile memory device of the present invention is connected between a bit line common node and a sensing node, and includes a switching element whose threshold voltage is adjusted according to a user's selection.

In addition, the erase method of the nonvolatile memory device of the present invention comprises the steps of determining the threshold voltage of the nonvolatile cell included in the bit line sensing unit, programming the nonvolatile cell to have the determined threshold voltage, And performing an erase verification operation using the bit line sensing unit including the nonvolatile cell.

Description

Bitline sensing unit of non volatile memory device and erasing method using that}

The present invention relates to a bit line sensing unit of a nonvolatile memory device and an erase method using the same.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. A sensing node sensing a level, a bit line selecting unit controlling whether the specific bit line and the sensing node are connected, and a bit line sensing for transmitting a voltage level of the bit line to the sensing node according to the state of the memory cell during a verify or read operation. Contains wealth.

According to the principle of the erase verification operation of the nonvolatile memory device, it is necessary to adjust the threshold voltages of the erased cells according to the characteristics of the memory cells. That is, when the manufacturing process for the nonvolatile memory device is completed and the test is performed, if there are many program disturb failures, it is necessary to lower the threshold voltages of the cells in the erase operation completed state. However, if the program disturbance characteristic is excellent, but the distribution characteristic is to be improved by reducing the interference, the threshold voltage of the cells in the erase operation is required to be higher.

An object of the present invention to solve the above problems is to provide a nonvolatile memory device capable of adjusting the threshold voltage of the switching element included in the bit line sensing unit. In addition, the present invention provides a method of erasing a nonvolatile memory device capable of controlling threshold voltages of erased cells using the nonvolatile memory device.

The bit line sensing unit of the nonvolatile memory device of the present invention for solving the above problems is connected between the bit line common node and the sensing node, characterized in that it comprises a switching element whose threshold voltage is adjusted according to the user's selection .

In addition, the erase method of the nonvolatile memory device of the present invention comprises the steps of determining the threshold voltage of the nonvolatile cell included in the bit line sensing unit, programming the nonvolatile cell to have the determined threshold voltage, And performing an erase verification operation using the bit line sensing unit including the nonvolatile cell.

According to the aforementioned problem solving means of the present invention, the threshold voltage value of the switching element included in the bit line sensing unit may be adjusted according to a user's selection. In addition, when the erase verification operation is performed using the bit line sensing unit, the threshold voltage distribution of the erased cells may be adjusted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a circuit diagram showing a configuration of a nonvolatile memory device that is commonly used.

The nonvolatile memory device 100 includes a memory cell array 110 including a plurality of memory cells, and a page buffer 120 connected to the memory cells to program specific data or to read data stored in the memory cells. It includes.

The memory cell array 110 may input / output memory cells MC0 to MCn for storing data, word lines WL <0: n> for selecting and activating the memory cells, and data of the memory cells. And a plurality of bit lines BLe and BLo, wherein the plurality of word lines and the plurality of bit lines are arranged in a matrix form.

The memory cell array 110 includes drain select transistors DSTe and DSTo connected between a bit line and a memory cell, and source select transistors SSTe and SSTo connected between a common source line CSL and a memory cell. do. In addition, a plurality of memory cells connected in series between the source select transistors SSTe and SSTo and the drain select transistors DSTe and DSTo may be referred to as cell strings. Gates of the memory cells are connected to word lines, and a set of memory cells commonly connected to the same word line is called a page. A plurality of strings connected to each bit line are connected in parallel to a common source line to form a memory cell block.

The page buffer 120 includes a bit line selector 130 for selectively connecting a bit line connected to a specific cell with a sensing node, a sensing node precharge unit 140 for applying a high level power voltage to the sensing node; A data latch unit 150 for temporarily storing data to be programmed in a specific cell or temporarily storing data read from a specific cell, a data setting unit 160 for inputting data to be stored in the data latch unit, and a level of the sensing node A sensing node sensing unit 170 for applying a ground voltage to a specific node of the data latch unit, a data transfer unit 180 for applying data stored in the data latch unit to the sensing node, and a state of a memory cell during a verify or read operation. The bit line sensing unit 190 transmits the voltage level of the bit line to the sensing node.

The bit line selector 130 may include an NMOS transistor N136 connecting the even bit line BLe and the sensing node SO in response to a first bit line select signal BSLe, and a second bit line select signal. And an NMOS transistor N138 connecting the odd bit line BLo and the sensing node SO in response to BSLo. In addition, the bit line selector 130 connects the even bit line BLe and the variable voltage input terminal in response to a variable voltage input terminal applying a variable voltage VIRPWR having a specific level and a first discharge signal DISCHe. An NMOS transistor N132 and an NMOS transistor N134 for connecting the odd bit line BLo and a variable voltage input terminal in response to a second discharge signal DISCHo.

The sensing node precharge unit 140 applies a high level voltage VDD to the sensing node SO in response to a precharge signal Prechb. To this end, it includes a PMOS transistor (P130) connected between the power supply voltage terminal (VDD) and the sensing node. Accordingly, a high level power supply voltage is applied to the sensing node SO in response to a low level precharge signal.

The data latch unit 150 temporarily stores data to be programmed in a specific cell or temporarily stores data read from a specific cell. To this end, the output terminal of the first inverter IV152 is connected to the input terminal of the second inverter IV154, and the output terminal of the second inverter IV154 is connected to the input terminal of the first inverter IV152. . In this case, a node to which the output terminal of the first inverter IV152 and the input terminal of the second inverter IV154 are connected is called a first node Q, and the output terminal of the second inverter IV154 and the first inverter IV152 are connected. The node to which the input terminal of) is connected is called a second node Qb.

The data setting unit 160 applies a ground voltage to the first data setting transistor N162 and a second node Qb to apply a ground voltage to the first node Q of the data latch unit 150. The second data setting transistor N164 is included. The first data setting transistor N162 is connected between the sensing node sensing unit 170 and the first node, and is grounded by the sensing node sensing unit 170 in response to a first data setting signal RESET. A voltage is applied to the first node. In addition, the second data setting transistor N164 is connected between the sensing node sensing unit 170 and the second node, and the sensing node sensing unit 170 is transferred in response to a second data setting signal SET. Apply a ground voltage to the second node.

The sensing node sensing unit 170 applies a ground voltage to the data setting unit 160 according to the voltage level of the sensing node. To this end, it includes an NMOS transistor (N170) connected between the data setting unit 160 and the ground terminal. Therefore, the ground voltage is applied to the data setting unit 160 according to the voltage level of the sensing node. Only when the sensing node has a high level, the ground voltage is applied to the data setting unit 160. At this time, when the high level first data setting signal RESET is applied, the ground voltage is applied to the first node Q, which is considered to be low level data applied to the first node. However, when the high level second data setting signal SET is applied, the ground voltage is applied to the second node Qb, which is considered to be applied to the first node.

The data transmitter 180 selectively applies data stored in the first node Q of the data latch unit 150 to the sensing node. To this end, the data transmission transistor N180 selectively connects the first node Q and the sensing node according to the data transmission signal TRAN.

The bit line sensing unit 190 includes an NMOS transistor N190 connected between the bit line selecting unit 130 and the sensing node SO. The bit line sensing unit 190 connects the bit line common node BLCM and the sensing node SO in response to the high level bit line sensing signal PBSENSE, and evaluates a specific bit line voltage level. The voltage level of the data stored in the cell is applied to the sensing node. In this case, a first voltage V1 or a second voltage V2 lower than the first voltage is applied as the voltage of the sensing signal. That is, a read or verify operation is performed according to the voltage level of the bit line sensing signal PBSENSE applied to the gate of the NMOS transistor N190. Detailed operations will be described with reference to the drawings.

2 is a waveform diagram illustrating various signals applied in an erase verify operation of a conventional nonvolatile memory device.

(1) T1 section

First, the bit line is discharged before connecting the cell string including the specific cell to be verified with the specific bit line. The first and second discharge signals DISCHe / o are enabled for a predetermined period of time so that the NMOS transistors N132 and N134 are turned on. Since the variable voltage VIRPWR is low level, each bit line BLe / o is turned on. Discharged to a low level potential.

In addition, the first node Q of the data latch unit 150 is initialized. When the sense node SO is made high by applying the low level of the gate signal PRECHb, the sensing node sensing unit 170 operates to transmit the ground voltage to the data setting unit 160. In this case, the ground voltage is applied to the first node Q by applying the first data setting signal RESET. Accordingly, low level data is stored in the first node Q.

(2) T2 section

Next, a high level voltage is applied to the common source line CSL and a high level voltage Vread is applied to the drain select transistor DSL to connect the cell string including the specific cell to be verified and the specific bit line. . In addition, a verification voltage of a specific level is applied to the word line, and since the erase verification is performed at this time, a voltage of 0 V is applied to the word lines of all cells.

On the other hand, in the state where the high level variable voltage VIRPWR is applied, the application of the first discharge signal DISCHe is stopped to disconnect the connection between the bit line BLe and the variable voltage input terminal to be verified. The second discharge signal DISCHo is continuously applied so that the bit line BLo, which is not a verification target, is maintained at a high level.

Next, a bit line sensing signal PBSENSE of the first voltage V1 is applied to connect the bit line common node BLCM and the sensing node SO. At this time, a high level bit line selection signal BSLe or BSLo is applied to a specific bit line to be read to connect the specific bit line BLe or BLo and the bit line common node BLCM.

In addition, the application of the precharge signal PRECHb is stopped to maintain the sensing node in the floating state SO. At this time, as the data transmission signal TRAN is applied, data stored in the first node Q is transferred to the sensing node SO, and the sensing node SO transitions to a low level.

(3) T3 section

Next, a high level voltage Vread is applied to the source select transistor SSL to connect the cell string including the verification target cell and the common source line to form a current path from the bit line to the common source line.

Next, the bit line sensing signal PBSENSE, which was a high level, is shifted to a low level, thereby disconnecting the corresponding bit line and the sensing node for a predetermined time. During this period, the voltage level of the bit line connected to the cell changes according to the state of the cell to be verified. That is, when the target cell is sufficiently erased below the verification voltage, the current flows sufficiently through the cell string, so that the voltage of the common source line in the high level state is transferred to the bit line, thereby increasing the voltage level of the bit line ( Va). However, when the target cell is not sufficiently erased below the verification voltage, the current does not flow sufficiently through the cell string, so that the voltage level of the bit line does not sufficiently increase (Vb).

Meanwhile, a low level precharge signal PRECHb is applied for a predetermined period to precharge the sensing node to a high level. Then, the precharge signal PRECHb is transitioned from the low level to the high level prior to the entry of the next section T4 to release the connection between the sensing node SO and the power supply voltage.

(4) T4 section

Next, the bit line sensing signal PBSENSE of the second voltage V2 is applied to determine the voltage level of the sensing node SO according to the voltage level of the corresponding bit line. When the cell is erased, the voltage level of the bit line is large (V2-Va <Vth), so the NMOS transistor N190 is not turned on, so the sensing node SO maintains the high level. However, when the corresponding cell is not sufficiently erased, the voltage level of the bit line is low (V2-Vb> Vth), so the NMOS transistor N190 is turned on, so that the sensing node SO transitions to the low level.

As described above, the erase verification operation is performed according to the voltage level of the bit line sensing signal PBSENSE applied to the bit line sensing unit 190. In this case, an important factor for determining the verification level is the threshold voltage Vth of the switching element included in the bit line signal generator 190. That is, as the threshold voltage increases, the threshold voltages of the memory cells must be lowered in order to pass the erase verification. In addition, when the threshold voltage is lowered, the erase verification operation may pass even if the threshold voltages of the memory cells are lowered. Therefore, the threshold voltage state of the erase cells may be adjusted using this characteristic. However, in the case of the NMOS transistor N190, there is no method of adjusting the threshold voltage level after the process is completed.

3 is a circuit diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

The nonvolatile memory device 300 includes a memory cell array 310 and a page buffer 320. The page buffer 320 may include a bit line selector 330, a sensing node precharge unit 340, a data latch unit 350, a data setting unit 360, a sensing node sensing unit 370, and a data transmission unit ( 380 and a bit line sensing unit 390. The detailed configuration is the same as described in FIG. However, there is a feature of the present invention in the configuration of the bit line sensing unit 390 according to an embodiment of the present invention.

The bit line sensing unit 390 uses a switching device that can adjust the level of the threshold voltage according to the user's selection. Preferably, the nonvolatile cell F390 to which the bit line sensing signal PBSENSE is applied as the gate voltage is included in the bit line sensing unit 390. The nonvolatile cell may have a threshold voltage desired by a user through a program operation. Such characteristics are used for the erase verification operation of the nonvolatile memory device.

As a result of completing the manufacturing process for the nonvolatile memory device and performing a test, it is necessary to lower the threshold voltages of the cells in the erase operation when there are many program disturb failures. In this case, the threshold voltage of the nonvolatile cell F390 included in the bit line sensing unit 390 is programmed to be high. As a result, the threshold voltages of the erase cells may be further lowered according to the principle described above. That is, as the threshold voltage of the nonvolatile cell F390 increases, the threshold voltage of each memory cell must be lowered in order to pass an erase verification. Therefore, the erase verification is completed with the threshold voltage lowered.

In addition, although the program disturbance characteristic is excellent, it is necessary to improve the distribution characteristic by reducing interference. In this case, the threshold voltage of the nonvolatile cell F390 included in the bit line sensing unit 390 is programmed to be low. When the threshold voltage of the nonvolatile cell F390 is reduced, the erase verification operation may pass even if the threshold voltage of each of the memory cells is lowered. Therefore, the erase verification is completed with the threshold voltage lowered.

4 is a flowchart illustrating an erase verification operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

First, the threshold voltage of the nonvolatile cell F390 included in the bit line sensing unit 390 is determined (step 410).

As mentioned above, the threshold voltage value is determined using test results of memory cells performed after the process is completed. That is, if there are many program disturb failures, it is necessary to lower the threshold voltages of the cells in the erase operation completed state, so that the threshold voltage of the nonvolatile cell F390 is increased.

In addition, when the program disturbance characteristic is excellent but it is necessary to improve the distribution characteristic by reducing the interference phenomenon, the threshold voltage of the cells in the erase operation is required to be increased, so that the nonvolatile cell F390 Determine the threshold voltage of to be reduced.

Next, the nonvolatile cell of the bit line sensing unit 390 is programmed to have the determined threshold voltage (step 420).

The program method and the verification method thereof apply conventional methods. That is, the program and verify operations are performed using the page buffer 320 including the bit line sensing unit 390.

During programming, a high voltage is applied to the gate of the nonvolatile cell F390 to perform a program operation according to FN tunneling.

In the verification, the determined threshold voltage is applied to the gate of the nonvolatile cell F390 to verify the verification. Since one end of the nonvolatile cell F390 needs to maintain the ground voltage or the specific voltage during the verify operation, the bit line select node 330 is used to maintain the bit line common node BLCM at the ground voltage or the specific voltage. .

In the state where the sensing node is precharged to the high level, when the nonvolatile cell F390 is programmed above the verify voltage, the nonvolatile cell F390 is not turned on, so the sensing node maintains the high level. However, when not programmed above the verification voltage, the nonvolatile cell F390 is turned on so that the sensing node transitions to the low level. This can be used to determine whether the nonvolatile cell has been programmed above the target verification voltage.

Next, an erase operation and an erase verify operation of the nonvolatile memory device are performed by using the bit line sensing unit 390 having the threshold voltage set by the steps 410 and 420. As the threshold voltage of the nonvolatile cell F390 increases, the threshold voltages of the erased cells also decrease.

In summary, the bit line sensing unit 390 capable of adjusting the threshold voltage may be employed to adjust the erase cells according to the state of the memory cells.

1 is a circuit diagram showing a configuration of a nonvolatile memory device that is commonly used.

2 is a waveform diagram illustrating various signals applied in an erase verify operation of a conventional nonvolatile memory device.

3 is a circuit diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

4 is a flowchart illustrating an erase verification operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Claims (10)

In a bit line sensing unit of a nonvolatile memory device, And a switching element connected between the bit line common node and the sensing node, the switching element of which a threshold voltage is adjusted according to a user's selection. The bit line sensing unit of claim 1, wherein the switching element is a nonvolatile cell receiving a bit line sensing signal as a gate. The bit line of claim 1, wherein when an erase verification is performed based on a bit line sensing unit including a switching device having a first threshold voltage, the bit line includes a switching device having a second threshold voltage smaller than the first threshold voltage. The bit line sensing unit of the nonvolatile memory device, wherein the threshold voltage of the erased memory cells is lower than that of the case of performing the erase verification based on the sensing unit. The bit line sensing unit of claim 2, wherein the nonvolatile cell is programmed and verified by a page buffer including the bit line sensing unit. Determining a threshold voltage of the nonvolatile cell included in the bit line sensing unit; Programming the nonvolatile cell to have the determined threshold voltage; Performing an erase operation on the memory cells; And performing an erase verification operation by using the bit line sensing unit including the nonvolatile cell. The method of claim 5, wherein the programming comprises applying a program voltage to a gate of the nonvolatile cell; And performing a verify operation by applying the determined threshold voltage to a gate of the nonvolatile cell. The erase method of claim 6, wherein the applying of the program voltage and the performing of the verify operation are performed using a page buffer including the bit line sensing unit. The memory of claim 5, wherein the performing of the erase verify operation is performed when the nonvolatile cell is programmed to have a first threshold voltage, compared to a case where the nonvolatile cell is programmed to have a second threshold voltage smaller than the first threshold voltage. A method of erasing a nonvolatile memory device, wherein the threshold voltages of the cells are lowered. The erase method of claim 5, wherein as the threshold voltage of the programmed nonvolatile cell increases as a result of performing the erase verification operation, the threshold voltage of the erased memory cells decreases. The erase method of claim 5, wherein as a result of performing the erase verification operation, as the threshold voltage of the programmed nonvolatile cell decreases, the threshold voltage of the erased memory cells increases.

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