KR20100006666A - None volatile memory device and multi level cell programming method thereof - Google Patents

None volatile memory device and multi level cell programming method thereof Download PDF

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Publication number
KR20100006666A
KR20100006666A KR1020080066883A KR20080066883A KR20100006666A KR 20100006666 A KR20100006666 A KR 20100006666A KR 1020080066883 A KR1020080066883 A KR 1020080066883A KR 20080066883 A KR20080066883 A KR 20080066883A KR 20100006666 A KR20100006666 A KR 20100006666A
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South Korea
Prior art keywords
verification
voltage
sensing
sensing voltage
level
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KR1020080066883A
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Korean (ko)
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이석규
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주식회사 하이닉스반도체
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Publication of KR20100006666A publication Critical patent/KR20100006666A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE: A nonvolatile memory device and a multi level cell program method thereof are provided to improve accuracy of a verification result by supplying a proper sensing voltage by estimating a leakage current of a bit line. CONSTITUTION: A verification number counter(420) counts the verification number according to a verification operation. A sensing voltage generator(430) controls the level of a sensing voltage used for the verification operation according to the verification number. The sensing voltage generator reduces the level of the sensing voltage as the verification number increases.

Description

Non-volatile memory device and multi level cell programming method

The present invention relates to a nonvolatile memory device and a multi-level cell program method thereof.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

In the verification operation of the nonvolatile memory device, a bit line precharge step, an evaluation step, a sensing step, and a bit line discharge step are performed. When applied to the multi-level cell program method, since a plurality of verification operations are performed, the time required for the verification operation is greatly increased when all of the above steps are performed. Therefore, the bit line discharge step is omitted and the verification operation is performed. However, in this method, since the initial bit line precharge level is continuously maintained, a voltage drop occurs due to bit line leakage during the next verification operation, which needs to be compensated for.

SUMMARY OF THE INVENTION An object of the present invention to solve the above problems is to provide a nonvolatile memory device and a multi-level cell program method capable of performing the same operation as the conventional operation while omitting the bit line discharge step in the verify operation.

The nonvolatile memory device of the present invention for solving the above-described problem is a counting counting unit for counting the number of verification for each verification operation, and adjusting the level of the sensing voltage used in the verification operation according to the number of verification for each verification operation And a sensing voltage generator.

The multi-level cell program method of the nonvolatile memory device of the present invention may further include performing a program operation, setting a sensing voltage according to a first verification frequency, and performing a first verification operation according to the set sensing voltage. And setting a sensing voltage according to a second verification frequency, performing a second verification operation according to the set sensing voltage, setting a sensing voltage according to a third verification frequency, and setting the sensing voltage. And performing a third verification operation according to the sensing voltage.

According to such an operation, it is possible to predict a situation in which leakage current occurs in the bit line, and provide the same verification result by supplying an appropriate sensing voltage. In other words, even if the bit line discharge step is omitted, the same verification result can be produced, thereby reducing the time required for the verification operation as a whole.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a circuit diagram showing a configuration of a nonvolatile memory device to which the present invention is applied.

The nonvolatile memory device 100 includes a memory cell array 110 including a plurality of memory cells, and a page buffer 120 connected to the memory cells to program specific data or to read data stored in the memory cells. It includes.

The memory cell array 110 may input / output memory cells MC0 to MCn for storing data, word lines WL <0: n> for selecting and activating the memory cells, and data of the memory cells. And a plurality of bit lines BLe and BLo, wherein the plurality of word lines and the plurality of bit lines are arranged in a matrix form.

The memory cell array 110 includes drain select transistors DSTe and DSTo connected between a bit line and a memory cell, and source select transistors SSTe and SSTo connected between a common source line and a memory cell. In addition, a plurality of memory cells connected in series between the source select transistors SSTe and SSTo and the drain select transistors DSTe and DSTo may be referred to as cell strings 112.

Gates of the memory cells are connected to word lines, and a set of memory cells commonly connected to the same word line is called a page (page 114). A plurality of strings connected to each bit line are connected in parallel to a common source line to form a block.

The page buffer 120 includes a bit line selector 130 for selectively connecting a bit line connected to a specific cell with a sensing node, a sensing node precharge unit 140 for applying a high level power voltage to the sensing node; A data latch unit 150 for temporarily storing data to be programmed in a specific cell or temporarily storing data read from a specific cell, a data setting unit 160 for inputting data to be stored in the data latch unit, and a level of the sensing node A sensing node sensing unit 170 for applying a ground voltage to a specific node of the data latching unit, a data transmitting unit 180 for applying data stored in the data latching unit to the sensing node, and the data latching unit 150 stored in the data latching unit 150. It includes a verification signal output unit 190 for notifying whether the verification is completed according to the data.

The bit line selector 130 may include an NMOS transistor N136 connecting the even bit line BLe and the sensing node SO in response to a first bit line select signal BSLe, and a second bit line select signal. And an NMOS transistor N138 connecting the odd bit line BLo and the sensing node SO in response to BSLo. In addition, the bit line selector 130 connects the even bit line BLe and the variable voltage input terminal in response to a variable voltage input terminal applying a variable voltage VIRPWR having a specific level and a first discharge signal DISCHe. And an NMOS transistor N134 for connecting the odd bit line BLo and a variable voltage input terminal in response to a second discharge signal DISCHo.

The sensing node precharge unit 140 applies a high level voltage VDD to the sensing node SO in response to a precharge signal Prechb. To this end, it includes a PMOS transistor (P130) connected between the power supply voltage terminal (VDD) and the sensing node. Accordingly, a high level power supply voltage is applied to the sensing node SO in response to a low level precharge signal.

The data latch unit 150 temporarily stores data to be programmed in a specific cell or temporarily stores data read from a specific cell. To this end, the output terminal of the first inverter IV152 is connected to the input terminal of the second inverter IV154, and the output terminal of the second inverter IV154 is connected to the input terminal of the first inverter IV152. . In this case, a node to which the output terminal of the first inverter IV152 and the input terminal of the second inverter IV154 are connected is called a first node Q, and the output terminal of the second inverter IV154 and the first inverter IV152 are connected. The node to which the input terminal of) is connected is called a second node Qb.

The data setting unit 160 applies a ground voltage to the first data setting transistor N162 and a second node Qb to apply a ground voltage to the first node Q of the data latch unit 150. The second data setting transistor N164 is included. The first data setting transistor N162 is connected between the sensing node sensing unit 170 and the first node, and is transmitted by the sensing node sensing unit 170 in response to a first data setting signal RESET. The ground voltage is applied to the first node. In addition, the second data setting transistor N164 is connected between the sensing node sensing unit 170 and the second node, and the sensing node sensing unit 170 is transferred in response to a second data setting signal SET. Apply a ground voltage to the second node.

The sensing node sensing unit 170 applies a ground voltage to the data setting unit 160 according to the voltage level of the sensing node. To this end, it includes an NMOS transistor (N170) connected between the data setting unit 160 and the ground terminal. Therefore, the ground voltage is applied to the data setting unit 160 according to the voltage level of the sensing node. Only when the sensing node has a high level, the ground voltage is applied to the data setting unit 160. At this time, when the high level first data setting signal RESET is applied, the ground voltage is applied to the first node Q, which is considered to be low level data applied to the first node. However, when the high level second data setting signal SET is applied, the ground voltage is applied to the second node Qb, which is considered to be applied to the first node.

The data transmitter 180 selectively applies data stored in the first node Q of the data latch unit 150 to the sensing node. To this end, it includes a data transfer transistor (N180) for selectively connecting the first node (Q) and the sensing node.

The verification signal output unit 190 outputs a signal indicating whether verification is completed according to data stored in the first node Q of the data latch unit 150. To this end, it includes a PMOS transistor (P190) for transmitting a high-level power supply voltage terminal to the verification signal output terminal (nWDO) according to the signal of the first node (Q). According to an exemplary embodiment, an NMOS transistor may be used to transfer a high level power supply voltage terminal to the verification signal output terminal nWDO according to the signal of the second node Qb.

Now, the principle of the read operation / verification operation of the nonvolatile memory device will be described. 2 is a view for explaining the principle of a read operation / verification operation of a conventional nonvolatile memory device.

(1) T1 section

First, the sensing node SO is precharged to a high level by applying a low level sensing node precharge signal PRECHb. In addition, the bit line selection signal BSL of the first voltage V1 is applied to precharge the bit line VBL to the high level V1 -Vth.

(2) T2 section

Next, the application of the bit line selection signal BSL is stopped to maintain or discharge the voltage level of the bit line according to the state of the cell to be read. To this end, a pass voltage Vpass is applied to word lines of cells other than the cell to be read to turn on all of the corresponding cells. In addition, a read voltage or a verify voltage Vread or Vver is applied to the word line of the cell to be read. If the threshold voltage of the cell to be read is greater than the read voltage or the verify voltages Vread and Vver, the cell is not turned on and maintains the precharged high level voltages V1 -Vth. However, if the threshold voltage of the cell to be read is less than the read voltage or the verification voltage (Vread, Vver), the cell is turned on and the precharged voltage is discharged to ground through the cell string.

(3) T3 section

Next, the voltage level of the bit line VBL is sensed by applying the bit line selection signal BSL of the second voltage V2. Meanwhile, at this time, the sensing node is stopped by floating the sensing node precharge operation.

If the voltage level of the bit line is discharged because the threshold voltage of the read target cell is lower than the read voltage or the verify voltage Vread and Vver, the bit line selection signal BSL of the second voltage V2 is discharged. The NMOS transistor N136 or N38 is turned on so that the sensing node SO is also discharged to a low level. This is because the difference between the gate voltage V2 and the source voltage 0V of the NMOS transistor N136 or N38 is larger than the threshold voltage Vth.

On the other hand, if the threshold voltage of the read target cell is higher than the read voltage or the verify voltages Vread and Vver, and the voltage level of the bit line is maintained at the high level (V1-Vth), the bit line of the second voltage V2. The NMOS transistor N136 or N38 is turned off even when the selection signal BSL is applied, so that the sensing node SO is discharged to a low level. This is because the difference between the gate voltage V2 and the source voltages V1-Vth of the NMOS transistors N136 or N38 is smaller than the threshold voltage Vth. In this case, the second voltage V2 and the first voltage V1 are set such that a difference between the gate voltage V2 and the source voltages V1 -Vth is smaller than the threshold voltage Vth.

Subsequently, although not shown in the drawing, an operation of discharging the bit line using the bit line selection unit 130 is performed. That is, the bit lines may be discharged by applying the ground voltage to the variable voltage VIRPWR and applying the discharge signal DISCHe or DISCHo.

In summary, the verification operation of the nonvolatile memory device performs the bit line precharge step, the evaluation step, the sensing step, and the bit line discharge step. When applied to the multi-level cell program method, since a plurality of verification operations are performed, the time required for the verification operation is greatly increased when all of the above steps are performed.

3 is a view for explaining the concept of a multi-level cell program method of a nonvolatile memory device according to the present invention.

The multi-level cell program method illustrates a 2-bit multi-level cell program method. According to the operation of the lower bit program LSB, two distributions having different threshold voltages are formed. The single level cell program method stores one bit of data in each memory cell only with this lower bit program operation.

When the upper bit program (MSB) operation is performed on the distribution, four distributions having different threshold voltages are formed. Therefore, four different states, that is, two bits of data, can be stored in each memory cell. At this time, the distribution of the cells having the lowest threshold voltage is greater than the first state and the first verification voltage PV1 and less than the second verification voltage PV2. The distribution of the programmed cells is greater than the second state and the second verification voltage PV2. The distribution of cells programmed to be larger and lower than the third verification voltage PV3 is referred to as the third state, and the distribution of cells programmed to be greater than the third verification voltage PV3 is referred to as the fourth state.

According to the multi-level cell program method, a verification operation for determining whether each cell is programmed in a specified state as well as a program operation is performed. That is, a first verification operation based on the first verification voltage PV1, a second verification operation based on the second verification voltage PV2, a third verification operation based on the third verification voltage PV3, and the like. Will be performed. By this verification operation, it is possible to confirm whether each cell is programmed to a desired state. However, in the multi-level cell program method, since a verification operation based on a plurality of verification voltages is performed, the time required for the verification operation is increased, and thus it is necessary to minimize the verification operation.

Accordingly, in the present invention, the bit line discharge step described in FIG. 2 is omitted and the verification operation is performed. However, in this method, since the initial bit line precharge level is continuously maintained, a voltage drop occurs due to bit line leakage during the following verification operation. To compensate for this, the second voltage ( It is necessary to adjust the level of V2).

4 illustrates a nonvolatile memory device according to an embodiment of the present invention.

The nonvolatile memory device 400 includes a controller 410, a verification count counting unit 420, a sensing voltage generator 430, and a memory cell array 440.

The controller 410 counts the number of verification operations performed on the verification target cell of the memory cell array 440 and stores the number of verification operations in the verification counting unit 420. In the multi-level cell program method, a verification operation is performed after applying a program pulse according to an incremental step pulse program (ISPP) program method, and the operation of applying a program pulse increased by a step pulse is repeated continuously. At this time, the number of repeated verification operations is called a verification frequency. At this time, the verification count is counted by each verification operation. In the case of the 2-bit multi-level cell program method, the first verify operation, the second verify operation, and the third verify operation are performed in the upper bit program operation. The verification count is counted and stored for each verify operation. In the 3-bit multi-level cell program method, a total of seven verify operations are performed in the most significant bit program operation, and each of them is stored separately.

As described above, the verification count counting unit 420 counts verification counts for each verification operation and stores each verification count. Therefore, it includes a counter for counting the number of verifications and a register for storing each verification.

The sensing voltage generator 430 controls the level of the second voltage V2 applied as the bit line selection signal BSLe / o in accordance with the verification frequency. In this case, the second voltage V2 is called a sensing voltage. Referring back to FIG. 2, when the leakage current occurs in the bit line, as the number of verification increases, the voltage level of the bit line decreases. Accordingly, the sensing voltage V2 needs to be reduced. Accordingly, the sensing voltage generator 430 varies the sensing voltage V2 according to the verification frequency.

5 is a flowchart illustrating a multi-level cell program method of a nonvolatile memory device according to an embodiment of the present invention.

First, a program operation is performed (step 510).

The program start voltage is applied to the selected word line according to the ISPP program operation. When the program operation is repeatedly performed, the program voltage is increased by the step voltage to the program pulse applied during the immediately preceding program operation.

Next, it is determined whether the first verification operation is completed (step 520). When it is confirmed that all of the first verification target cells are programmed to be greater than or equal to the first verification voltage, it is determined whether to perform the second verification operation without performing the first verification operation any more.

If the first verification operation is not completed, the sensing voltage V2 is set according to the number of times the first verification operation is performed, that is, the first verification frequency (step 522). That is, the range of the first verification count is specified and the sensing voltage is set differently according to the count. Preferably, the sensing voltage decreases as the number of verifications increases.

In operation 524, a first verification operation is performed according to the set sensing voltage. The detailed verification operation is the same as described with reference to FIG. 2, except that the sensing voltage V2 that is variably set according to the verification frequency is applied.

Next, it is determined whether the second verification operation is completed (step 530). When it is confirmed that all of the second verification target cells are programmed to be greater than or equal to the second verification voltage, it is determined whether to perform the third verification operation without performing the second verification operation any more.

When the second verification operation is not completed, the sensing voltage V2 is set according to the number of times the second verification operation is performed, that is, the second verification frequency (step 532). That is, the range of the second verification count is specified and the sensing voltage is set differently according to the count. Preferably, the sensing voltage decreases as the number of verifications increases.

Next, a second verification operation is performed according to the set sensing voltage (step 534). The detailed verification operation is the same as described with reference to FIG. 2, except that the sensing voltage V2 that is variably set according to the verification frequency is applied.

Next, it is determined whether the third verification operation is completed (step 540). If it is confirmed that all of the third verification target cells have been programmed above the third verification voltage, the program operation is terminated without performing the third verification operation any more.

If the third verification operation is not completed, the sensing voltage V2 is set according to the number of times the third verification operation is performed, that is, the third verification frequency (step 542). That is, the range of the third verification frequency is specified and the sensing voltage is set differently according to the number of verification times. Preferably, the sensing voltage decreases as the number of verifications increases.

Next, a third verification operation is performed according to the set sensing voltage (step 544). The detailed verification operation is the same as that described with reference to FIG. 2, except that the sensing voltage V2 that is set variably according to the verification frequency is applied.

Next, the program voltage is increased by the step voltage, and the program operation is repeatedly performed (steps 550 and 510).

Meanwhile, as described above, the bit line discharge step is not performed when each verification operation is performed. According to such an operation, it is possible to predict a situation in which leakage current occurs in the bit line, and provide the same verification result by supplying an appropriate sensing voltage. In other words, even if the bit line discharge step is omitted, the same verification result can be produced, thereby reducing the time required for the verification operation as a whole.

1 is a circuit diagram showing the configuration of a nonvolatile memory device to which the present invention is applied.

to be.

2 is a view for explaining the principle of a read operation / verification operation of a conventional nonvolatile memory device.

3 is a view for explaining the concept of a multi-level cell program method of a nonvolatile memory device according to the present invention.

4 illustrates a nonvolatile memory device according to an embodiment of the present invention.

5 is a flowchart illustrating a multi-level cell program method of a nonvolatile memory device according to an embodiment of the present invention.

Description of the main parts of the drawing

400: nonvolatile memory device

410: control unit

420: verification count counting unit

430: sensing voltage generator

440: memory cell array

Claims (5)

A verification count counting unit for counting verification counts for each verification operation; And a sensing voltage generator configured to adjust a level of a sensing voltage used in the verifying operation according to the verifying frequency of each verifying operation. The nonvolatile memory device of claim 1, wherein the sensing voltage generator reduces and supplies the level of the sensing voltage as the number of verifications increases. The nonvolatile memory device of claim 1, wherein the counting unit stores the number of verification operations of (2 ^ n−1) verification operations in the case of an n-bit multi-level cell program operation. Performing a program operation, Setting a sensing voltage according to a first verification number; Performing a first verification operation according to the set sensing voltage; Setting a sensing voltage according to a second verification frequency; Performing a second verification operation according to the set sensing voltage; Setting a sensing voltage according to a third verification frequency; And performing a third verification operation according to the set sensing voltage. The method of claim 5, wherein the setting of the sensing voltages comprises setting the sensing voltages lower as the number of verification times increases.
KR1020080066883A 2008-07-10 2008-07-10 None volatile memory device and multi level cell programming method thereof KR20100006666A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8374023B2 (en) 2010-09-30 2013-02-12 SK Hynix Inc. Semiconductor memory apparatus
US8456932B2 (en) 2010-09-30 2013-06-04 SK Hynix Inc. Semiconductor memory apparatus
US8526239B2 (en) 2010-04-29 2013-09-03 Hynix Semiconductor Inc. Semiconductor memory device and method of operating the same
US11600344B2 (en) 2020-04-08 2023-03-07 SK Hynix Inc. Memory device and method of operating the memory device including program verify operation with program voltage adjustment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8526239B2 (en) 2010-04-29 2013-09-03 Hynix Semiconductor Inc. Semiconductor memory device and method of operating the same
US8374023B2 (en) 2010-09-30 2013-02-12 SK Hynix Inc. Semiconductor memory apparatus
US8456932B2 (en) 2010-09-30 2013-06-04 SK Hynix Inc. Semiconductor memory apparatus
US11600344B2 (en) 2020-04-08 2023-03-07 SK Hynix Inc. Memory device and method of operating the memory device including program verify operation with program voltage adjustment

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