CN106206587A - Three-dimensional longitudinal memorizer that address/data transducer separates - Google Patents
Three-dimensional longitudinal memorizer that address/data transducer separates Download PDFInfo
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Abstract
The present invention proposes a kind of separation 3D-MV50, it contains at least one three-dimensional array chip 30 and at least one address/data converter chip 40*.Three-dimensional array chip 30 is containing multiple vertical storage string 16X, 16Y.At least one address/data transducer is positioned at address/data converter chip 40*, rather than in three-dimensional array chip 30.Three-dimensional array chip 30 and address/data converter chip 40* have diverse rear end (BEOL) structure.
Description
Technical field
The present invention relates to integrated circuit storage field, more precisely, relate to three-dimensional longitudinal memorizer (3D-MV).
Background technology
Three-dimensional storage (3D-M) is a kind of monomer (monolithic) semiconductor memory, and it contains multiple storage being stacked with unit.3D-M includes that 3 D ROM (3D-ROM) and three-dimensional random read memorizer (3D-RAM).3D-ROM can be further divided into three-dimensional masking film program read-only memory (3D-MPROM) and three-dimensional electric programming read-only memory (3D-EPROM).Based on its programming mechanism, 3D-M can be 3D-memristor, 3D-RRAM or 3D-ReRAM (resistive random-access memor), 3D-PCM(phase-change
Memory), 3D-PMC(programmable
Metallization-cell memory) or 3D-CBRAM(conductive-bridging random-access memory) etc..
United States Patent (USP) 5,835,396 disclose a kind of 3D-M, i.e. 3D-ROM.As shown in Figure 1A, 3D-M chip 20 containing a substrate circuitry layer 0K and multiple be stacked on substrate circuitry layer 0K and be stacked with accumulation layer 16A, 16B.Substrate circuitry layer 0K contains transistor 0t and interconnection line 0i thereof.Transistor 0t is formed in Semiconductor substrate 0.Substrate interconnection line 0i is that transistor 0t realizes being connected with each other.In this example, substrate interconnection line 0i contains metal level 0M1,0M2.
Accumulation layer 16A, 16B are stacked on substrate circuitry layer 0K, and they are coupled with substrate 0 by contact access opening (such as 1av).Each accumulation layer (such as 16A) is containing a plurality of top address line (such as 2a), end address wire (such as 1a) and storage unit (such as 5aa).Storage unit can use diode, transistor or other device.In various storage units, the storage unit of diode is used to have minimum area, only 4F2(F is minimum feature size).Diode storage is first is typically incorporated in top address line and the intersection of end address wire, thus constitutes a cross point (cross-point) array.Here, diode refers to any two-terminal device with following feature: when the numerical value of its applied voltage is contrary with read voltage less than the direction of read voltage or applied voltage, its resistance is much larger than its resistance under read voltage.The example of diode includes semiconductor diode (such as p-i-n silicon diode etc.) and MOS diode (such as titanium oxide diode, nickel oxide diode etc.) etc..
Accumulation layer 16A, 16B constitute at least one 3D-M array 16, and substrate circuitry layer 0K then contains the peripheral circuit of 3D-M array 16.Wherein, a part of peripheral circuit is positioned at below 3D-M array, and they are referred to as array following peripheral circuit；Another part peripheral circuit is positioned at outside 3D-M array, and they are referred to as array neighboring circuit 18.Due to array neighboring circuit 18 than 3D-M array 16 containing less rear end (back-end-of-line, referred to as BEOL) layer, the space 17 above array neighboring circuit 18 does not contains storage unit, and this space is actually wasted.In this manual, BEOL layer means above one layer of conductor wire of substrate.In figure ia, 3D-M array 16 is containing 6 BEOL layer (including 2 address-wire layer 1a-4a that 2 substrate interconnections line layer 0M1,0M and accumulation layer 16A, 16B respectively contain)；And array neighboring circuit 18 comprises only 2 BEOL layer (2 substrate interconnections line layer 0M1,0M2).
United States Patent (USP) 7,388,476 disclose a kind of integrated 3D-M chip, and its cubical array and peripheral circuit thereof are all integrated in same chip.As shown in Figure 1B, this integrated 3D-M chip 20 is containing cubical array region 22 and peripheral circuit area 28.Cubical array region 22 is containing multiple 3D-M arrays (such as 22aa, 22ay) and decoder thereof (such as 24,24G).These decoders 24 include local decoder 24 and overall decoder 24G.Wherein, the address/data of single 3D-M array is decoded by local decoder 24, and total address/data 25 is decoded to single 3D-M array by overall decoder 24G.
Circuit unit in peripheral circuit area 28 makes integrated 3D-M chip 20 can complete basic storage function, and they can be to realize voltage, data, address conversion between cubical array region 22 and main frame (the most directly using the equipment of this chip 20).Peripheral circuit 28 is containing read/write voltage generator 21 and address/data transducer 29.Wherein, supply voltage 23 is converted into read voltage V by read/write voltage generator 21ROr/and write (programming) voltage VW；Logical address/data 27 are mutually changed by address/data transducer 29 with physical address/data 25.In this manual, logical address/data 27 are the address/data that main frame uses；And physical address/data 25 are the address/data that 3D-M array uses.
Example in Figure 1A and Figure 1B is three-dimensional laterally memorizer (3D-MH), it stores assembly substantially is horizontal accumulation layer.Above-mentioned introduction can be used for three-dimensional longitudinal memorizer (3D-MV), it stores assembly substantially is vertically to store string.
United States Patent (USP) 8,638,611 discloses a kind of 3D-MV.It is a kind of longitudinal NAND(vertical NAND).Except longitudinal NAND, 3D-ROM, 3D-RAM, 3D-memristor, 3D-RRAM or 3D-ReRAM, 3D-PCM, 3D-PMC, 3D-CBRAM can also form 3D-MV.As in figure 2 it is shown, this 3D-MVChip 20 is containing at least one 3D-MVArray 16 and peripheral circuit 18.3D-MVArray 16 is containing multiple vertical storage string 16X, 16Y.Storage unit (such as 8a-8h) containing multiple vertical stackings of each storage string (such as 16X), these storage units are intercoupled by a vertical address wire.Each storage unit (such as 8f) is containing a vertical transistor, and this vertical transistor contains grid 6, storage film 7 and longitudinal channel 9.In a vertical storage string, the grid 6 of each storage unit (such as 8f) constitutes a BEOL layer.In fig. 2,3D-MVArray 16 is containing 8 BEOL layer, i.e. accumulation layers 8a-8h.
Owing to vertically storage string 16X, 16Y occupy substrate 0(Fig. 2 below), 3D-MVChip 20 can not contain array following peripheral circuit, and can only contain array neighboring circuit 18.This and 3D-MH(Figure 1A) different, 3D-MHChip 20 can contain array following peripheral circuit.3D-MVThe peripheral circuit 18 of array 16 is containing substrate transistor 0t and substrate interconnection line 0i thereof.Substrate transistor 0t is formed in Semiconductor substrate 0, and it is traditional planar ransistor.Substrate interconnection line 0i is that substrate transistor 0t realizes being connected with each other.In this example, peripheral circuit 18 is containing 2 BEOL layer, i.e. substrate interconnection line layer 0M1,0M2.
The 3D-M of conventional artVIt is integrated 3D-MV.It is to say, 3D-MVArray 16 and peripheral circuit 18 are integrated in same 3D-MVIn chip 20.Owing to their manufacturing process is not mated, 3D-MVArray 16 and peripheral circuit 18 need to be formed respectively.Correspondingly, the 3D-M in Fig. 2VChip 20 is containing 10 BEOL layer, including 3D-MV8 BEOL layer of array 16 and 2 BEOL layer of peripheral circuit 18.
The Main Viewpoints of prior art is: integrated level is the bigger the better, and the most integrated can reduce cost and improve performance.Unfortunately, this viewpoint is to 3D-MVIt is false.First for, owing to vertically storing the BEOL layer of string 16X, 16Y far more than peripheral circuit 18, the most integrated direct result is exactly to have to manufacture the simplest original peripheral circuit 18 by the expensive process flow process manufacturing vertically storage string 16X, 16Y, and this can increase 3D-MVHolistic cost.Secondly as 3D-MVChip 20 is mainly for 3D-MVArray 16 optimizes, it have to sacrifice peripheral circuit 18 performance.Such as saying, peripheral circuit 18 is containing a few (such as 2) substrate interconnection line layer, or the high temperature resistant interconnection material (such as employing tungsten as conductive material, silicon oxide as insulant) that operating speed is slower, and this can reduce 3D-MVOverall performance.
Summary of the invention
The main object of the present invention is to reduce three-dimensional longitudinal memorizer (3D-MV) overall price.
It is another object of the present invention to improve 3D-MVOverall performance.
In order to realize these and other purpose, the present invention defers to following design principle: three-dimensional circuit and two-dimensional circuit are separated to different chip, in order to they be separately optimized.Such as say, by 3D-MVArray 16(three-dimensional circuit) and voltage generator (two-dimensional circuit) be separated in different chip.Correspondingly, the present invention proposes a kind of separation 3D-MV, it contains at least one three-dimensional array chip and at least one address/data converter chip.Three-dimensional array chip (three-dimensional circuit) builds in three dimensions and containing multiple functional layers (multiple accumulation layer being stacked with), and address/data converter chip (two-dimensional circuit) builds in two-dimensional space and comprises only a functional layer (i.e. the transducer Han address/data).
Separating 3D-MVIn, owing to three-dimensional array chip and address/data converter chip can separately design and manufacture, they can have different rear end (BEOL) structures.Firstly, since address/data converter chip contains less BEOL layer, its wafer cost is far below three-dimensional array chip (or integrated 3D-MVChip).In one embodiment, three-dimensional array chip vertically stores the interconnection line number of plies much larger than address/data converter chip of the storage unit number contained by string.Correspondingly, 3D-M is separatedVHolistic cost less than integrated 3D-MV.Secondly as the rear end structure of address/data converter chip can be with single optimization, the performance of its address/data transducer is better than integrated 3D-MVIn address/data transducer (or the peripheral circuit in three-dimensional array chip).In one embodiment, the interconnection line number of plies of address/data converter chip is more than the peripheral circuit in three-dimensional array chip.In another embodiment, address/data converter chip can use high-performance interconnection material (as use copper as conductive material, high-g value is as insulant；The peripheral circuit of three-dimensional array chip uses slow high temperature resistant interconnection material).Correspondingly, 3D-M is separatedVOverall performance be better than integrated 3D-MV。
Correspondingly, the present invention proposes three-dimensional longitudinal memorizer (3D-M of a kind of separationV) (50), it is characterised in that including: one contains at least one 3D-MVThe three-dimensional array chip (30) of array (36), this 3D-MV array (36) is containing multiple vertical strings (16X, 16Y) that store, and the storage containing multiple vertical stackings of each vertical storage string is first (8a-8h)；The one address/data converter chip (40*) containing at least part of address/data converter, this address/data transducer carries out address and/or data conversion between main frame and this three-dimensional array chip (30)；Described three-dimensional array chip (30) does not contains described partial address/data converter, vertically storing the interconnection line number of plies more than described address/data converter chip (40*) of storage unit (8a-8h) number contained by string (16X) in described three-dimensional array chip (30), described three-dimensional array chip (30) is two different chips with described address/data converter chip (40*).
The present invention also proposes three-dimensional longitudinal memorizer (3D-M of a kind of separationV) (50), it is characterised in that including: one contains at least one 3D-MVThe three-dimensional array chip (30) of array (36) and a peripheral circuit (38), this 3D-MVArray (36) is containing multiple vertical storages string (16X, 16Y), and this peripheral circuit (38) is positioned at this 3D-MVOutside array (36)；The one address/data converter chip (40*) containing at least part of address/data converter, this address/data transducer carries out address and/or data conversion between main frame and this three-dimensional array chip (30)；Described three-dimensional array chip (30) does not contains described partial address/data converter, the interconnection line number of plies of described address/data converter chip (40*) is more than the interconnection line number of plies of described peripheral circuit (38), and described three-dimensional array chip (30) is two different chips with described address/data converter chip (40*).
The present invention also proposes three-dimensional longitudinal memorizer (3D-M of a kind of separationV) (50), it is characterised in that including: one contains at least one 3D-MVThe three-dimensional array chip (30) of array (36) and a peripheral circuit (38), this 3D-MVArray (36) is containing multiple vertical storages string (16X, 16Y), and this peripheral circuit (38) is positioned at this 3D-MVOutside array (36)；The one address/data converter chip (40*) containing at least part of address/data converter, this address/data transducer carries out address and/or data conversion between main frame and this three-dimensional array chip (30)；Described three-dimensional array chip (30) does not contains described partial address/data converter, described peripheral circuit (38) and described address/data converter chip (40*) are containing different interconnection material, and described three-dimensional array chip (30) is two different chips with described address/data converter chip (40*).
Accompanying drawing explanation
Figure 1A is a kind of 3D-M(prior art) sectional view；Figure 1B is the system architecture of a kind of integrated 3D-chip (prior art).
Group 2 is a kind of integrated 3D-MVThe sectional view of chip (prior art).
Fig. 3 A-Fig. 3 C represents that three kinds separate 3D-MV。
Fig. 4 A is a kind of separation 3D-MVThe sectional view of middle three-dimensional array chip；Fig. 4 B is this separation 3D-MVThe sectional view of middle address/data converter chip.
Fig. 5 A-Fig. 5 B represents the first peripheral circuit component method of salary distribution at chip chamber.
Fig. 6 A-Fig. 6 B represents the second peripheral circuit component method of salary distribution at chip chamber.
Fig. 7 A-Fig. 7 C represents the third peripheral circuit component method of salary distribution at chip chamber.
Fig. 8 A-Fig. 8 B represents the 4th kind of peripheral circuit component method of salary distribution at chip chamber.
Fig. 9 A-Fig. 9 B represents two kinds of address/data converter chips supporting multiple three-dimensional array chip.
Figure 10 A-Figure 10 C is three kinds and separates 3D-M encapsulation or the sectional view of assembly.
Figure 11 A-Figure 11 C is the circuit block diagram of three kinds of voltage generators.
Figure 12 A is the circuit block diagram of a kind of address translator；Figure 12 B is the circuit block diagram of a kind of data converter.
Noticing, these accompanying drawings are only synoptic diagrams, and they nots to scale (NTS) are drawn.For the sake of obvious and convenient, portion size and structure in figure may zoom in or out.In different embodiments, identical symbol typicallys represent correspondence or similar structure.
Detailed description of the invention
In the present invention, "/" represent " with " or the relation of "or".Such as, read/write voltage represents read voltage or writes voltage or read voltage and write voltage；Address/data represents address or data or address and voltage.
Fig. 3 A-Fig. 3 C represents three kinds of three-dimensional longitudinal memorizer (3D-M separatedV) 50.It includes that one can realize physical connection the interface 54 according to a kind of communication standard communication with various main frames.Interface 54 includes multiple contact jaw 52a, 52b, 54a-54d, the contact jaw coupling that they can be corresponding with main frame socket.Wherein, power end 52a couples with the electrical power contacts end of main frame, and main frame is referred to as supply voltage V by the power supply that power end 52a providesDD；Earth terminal 52b is for separating 3D-MV50 provide ground voltage VSS；Signal end 54a-54d is main frame and separates 3D-MV50 provide signal exchange, and these signals include address/data.Owing to these address/data are directly used by main frame, they are logical address/data.
Separate 3D-MV50 contain at least one three-dimensional array chip 30(three-dimensional circuit) and an address/data converter chip 40*(two-dimensional circuit).In these embodiments, at least one address/data transducer is positioned in address/data converter chip 40*, rather than is positioned in three-dimensional array chip 30.Owing to address/data transducer is to realize 3D-MVThe required assembly of function, the three-dimensional array chip 30 without address/data transducer itself is not a storage chip that can work alone.
Separation 3D-M in Fig. 3 AV
50 is a storage card, and it contains a single three-dimensional array chip (three-dimensional circuit) 30 and single address/data converter chip (two-dimensional circuit) 40*.Address/data converter chip 40* contains an address/data transducer, including address translator and data converter.Wherein, address translator its external bus 54(is included from the signal on contact jaw 52a-52d) on logical address mutually change with the physical address on internal bus 58；Logical data on external bus 54 is mutually changed by data converter with the physical data on internal bus 58.Here, address/data transducer can only realize address conversion or only realizes data conversion or realize address and data conversion simultaneously.
In Fig. 3 B separation 3D-MV
50 is also a storage card.It contains two peripheral circuit chip: voltage generator chip 40 and address/data converter chip 40*.Voltage generator chip 40 is containing a voltage generator；Address/data converter chip 40* contains an address/data transducer.Voltage generator obtains supply voltage V at main frameDD, convert thereof into read/write voltage, and provide read/write voltage by power bus 56 to three-dimensional array chip 30.Here, read/write voltage can be merely read voltage VR, or only write voltage VW, or include read voltage VRWith write voltage VW, it and supply voltage VDDThere is different numerical value.In the present embodiment, read/write voltage includes read voltage VRVoltage V is write with twoW1、VW2.In other embodiments, read/write voltage can include more than one read voltage or two write voltage.
Separation 3D-M in Fig. 3 CV
50 is a large-capacity memory card or a solid state hard disc.It contains multiple three-dimensional array chip 30a, 30b ... 30w.These three-dimensional array chip two passage: A and B of composition.In passage A, internal bus 58A is three-dimensional array chip 30a, 30b ... 30i provides physical address/data, and in passage B, internal bus 58B is three-dimensional array chip 30r, 30s ... 30w provides physical address/data.Meanwhile, power bus 56 is dimension array chip 30a, 30b ... 30w provides read/write voltage.Although the present embodiment only has two passages, for the personage being familiar with this specialty, large-capacity memory card and solid state hard disc can contain more multichannel.
Fig. 4 A is to separate 3D-MV
The sectional view of three-dimensional array chip 30 in 50.It contains at least one 3D-MVArray 36 and a peripheral circuit 38.3D-MVArray 36 is formed in three dimensions, and containing multiple vertical storage string 16X, 16Y.Storage unit (such as 8a-8h) containing multiple vertical stackings of each vertical storage string (such as 16X).These storage units are intercoupled by a vertical address wire.Each storage unit (such as 8f) is containing a vertical transistor, and this vertical transistor contains grid 6, storage film 7 and longitudinal channel 9.One 3D-MVExample be longitudinal NAND(vertical NAND).For 3D-MVFor array 36, its BEOL layer number is equal to the storage unit number in vertically storage string, it is also possible to more than the storage unit number in vertically storage string.3D-M in Fig. 4 AVArray 36 is containing 8 BEOL layer, the 3D-M of actual volume productionVArray 36 is containing 24 or more BEOL layer.
Peripheral circuit 18 is positioned at 3D-MVOutside array 36.It contains substrate transistor 0t and substrate interconnection line 0i.Substrate transistor 0t is formed in Semiconductor substrate 0, and it is traditional planar ransistor.Substrate interconnection line 0i is that substrate transistor 0t realizes being connected with each other.In this example, peripheral circuit 18 is containing 2 BEOL layer, i.e. substrate interconnection line layer 0M1,0M2.On the other hand, although in Fig. 4 A, the sectional view of peripheral circuit 38 is similar with peripheral circuit in Figure 1B 18, in Fig. 4 A, peripheral circuit component contained by peripheral circuit 38 is fewer than peripheral circuit in Figure 1B 18.Particularly, peripheral circuit 38 at least lacks a voltage generator.The details of peripheral circuit 38 discloses in Fig. 5 A-Figure 10 B further.
Fig. 4 B is to separate 3D-MV
The sectional view of address/data converter chip 40* in 50.Address/data converter chip 40* is formed in two-dimensional space, and comprises only a functional layer, i.e. substrate circuitry layer 0K '.Substrate circuitry layer 0K ' includes transistor 0t ' and interconnection line 0i ' thereof.Transistor 0t ' is formed on voltage generator substrate 0 ', and interconnection line 0i ' is that transistor 0t ' realizes being connected with each other.This address/data converter chip 40 is containing four BEOL layer, i.e. interconnection line layer 0M1 '-0M4 '.
The understanding being familiar with this specialty both knows about, and the production cost of integrated circuit is directly proportional to its BEOL layer number substantially.Owing to address/data converter chip 40* contains less BEOL layer, its wafer cost is far below three-dimensional array chip 30.Because being at least partially separate 3D-MV
50(i.e. address/data converter chip 40) production cost far below integrated 3D-MVChip 20(address/data transducer is positioned in chip 20), separate 3D-MVThe holistic cost of 50 is less than integrated 3D-MV
20。
Additionally, due to address/data converter chip 40* is an individual chips, it can be than integrated 3D-MVThe peripheral circuit 18 of chip 20 has a more substrate interconnection line layer (as increased to four layers from two-layer), therefore the address/data transducer in address/data converter chip 40* is simpler than the address/data converter design in integrated 3D-M chip 20, better performances and shared chip area less.Noticing, although the interconnection line number of plies of address/data converter chip 40* is more than peripheral circuit 18, its BEOL layer number is still much smaller than three-dimensional array chip 30(4 vs. 8).
Further, since address/data converter chip 40* need not experience high-temperature technology, its interconnection line 0i ' can use high-performance interconnection material, as used copper (Cu) as conductive material, high-g value as insulant.These materials can improve the function of address/data converter chip 40*, thus improves separation 3D-MV
The overall performance of 50.
For traditional two dimensional memory (2D-M, such as flash memory), although its peripheral circuit component can be separated to a peripheral circuit chip from two-dimensional array chip, but do so can increase cost and reduce performance, this is because two-dimensional array chip is similar with the rear end structure of peripheral circuit chip, there is close wafer cost and circuit performance；Plus unnecessary lead-in wire cost and delay, the cost and the performance that separate 2D-M are all poor than integrated 2D-M.This and 3D-MVEntirely different.The rear end structure difference of three-dimensional array chip and peripheral circuit chip is very big (such as having different BEOL layer numbers, the different substrate interconnection line numbers of plies, different substrate interconnection wire materials etc.), separates 3D-MVCost and performance be all better than integrated 3D-MV。
Separate 3D-MV50 and integrated 3D-MV
The difference of 20 is: at least one peripheral circuit component is positioned at address/data converter chip 40, rather than is positioned at three-dimensional array chip 30.It is to say, 3D-MVPeripheral circuit component be assigned between three-dimensional array chip 30 and address/data converter chip 40.Fig. 5 A-Fig. 9 B illustrates multiple distribution method between chip (30,40).
Fig. 5 A-Fig. 5 B represents the first peripheral circuit component method of salary distribution at chip chamber.In fig. 5, storage array chip 30 is containing multiple 3D-M arrays (such as 22aa, 22ay) and decoder thereof.It is possibly together with voltage generator 41, but does not contains address/data transducer 49.In figure 5b, address/data converter chip 40 is containing the address/data transducer 49 not contained in Fig. 5 A.Owing to not containing address/data transducer 49, storage array chip 30 has higher array efficiency.
Fig. 6 A-Fig. 6 B represents the second peripheral circuit component method of salary distribution at chip chamber.In fig. 6, storage array chip 30 is containing multiple 3D-M arrays (such as 22aa, 22ay) and decoder thereof, but does not contains voltage generator 41 and address/data transducer 49.In fig. 6b, peripheral circuit chip 40 is containing voltage generator 41 and address/data transducer 49.Owing to not containing voltage generator 41 and address/data transducer 49, storage array chip 30 has the highest array efficiency.
Fig. 7 A-Fig. 7 C represents the third peripheral circuit component method of salary distribution at chip chamber.In fig. 7, storage array chip 30 is containing multiple 3D-M arrays (such as 22aa, 22ay) and decoder thereof, but does not contains voltage generator 41 and address/data transducer 49.Voltage generator 41 and address/data transducer 49 are positioned in different peripheral circuit chip: voltage generator 41 is positioned at voltage generator chip 40(Fig. 7 B) in；Address/data transducer 49 is positioned at address/data converter chip 40*(Fig. 7 C) in.Voltage generator 41 is based on analog circuit, and address/data transducer 49 is based on digital circuit.Owing to they are positioned at different peripheral circuit chip 40,40*, they can be separately optimized: to voltage generator chip 40 Optimized Simulated performance, address/data converter chip 40* is optimized digital performance.
Fig. 8 A-Fig. 8 B represents the 4th kind of peripheral circuit component method of salary distribution at chip chamber.It is similar with Fig. 6 A-Fig. 6 B, and simply three-dimensional array chip 30 is possibly together with first parallel-to-serial conversion circuit 47(Fig. 8 A), the parallel digital signal (such as address/data/instruction) within chip 30 is converted into the serial digital signals outside chip 30 by it.Address/data converter chip 40* is possibly together with the second parallel-to-serial conversion circuit 47 ' (Fig. 8 B), and the parallel digital signal (such as address/data/instruction) within address/data converter chip 40* is also converted into the serial digital signals outside chip 40* by it.Being converted by parallel-to-serial, lead-in wire (or soldered ball) number between three-dimensional array chip 30 and address/data converter chip 40* can be greatly reduced, therefore can reduce owing to using separation 3D-MVAdditional feedthrough (or soldered ball) cost encapsulated and cause.
Fig. 9 A-Fig. 9 B represents two kinds of address/data converter chip 40* supporting multiple cubical arraies.Address/data converter chip 40* in Fig. 9 A contains multiple address/data transducer 49a, 49b ... 49w.Each address/data transducer (such as 49a) is that corresponding three-dimensional array chip (30a as in Fig. 3 C) provides address/data conversion.Address/data converter chip 40 in Fig. 9 B is possibly together with multiple voltage generator 41a, 41b ... 41w.Each voltage generator (such as 41a) is that corresponding three-dimensional array chip (30a as in Fig. 3 C) provides read/write voltage.
Figure 10 A-Figure 10 C is three kinds and separates 3D-MVSectional view.Separation 3D-M in Figure 10 A-Figure 10 BVIt it is a kind of multi-chip package (MCP).Separation 3D-M in Figure 10 CVIt it is a kind of multi-chip module (MCM).These MCP and MCM may be used for storage card or solid state hard disc.
3D-M in Figure 10 AVEncapsulation 60 is containing two single chips: a three-dimensional array chip 30 and an address/data converter chip 40*.Chip 30,40 is stacked in a package substrate (interposer) 63 and is positioned in same encapsulating shell 61.Lead-in wire (bond wire) 65 is chip 30,40* provides electrical connection.Except lead-in wire, it is also possible to use soldered ball (solder
Bump) etc..In order to guarantee data security, chip 30,40* are preferably enclosed in a moulding compound (molding compound) 67.In the present embodiment, three-dimensional array chip 30 is stacked on address/data converter chip 40*.In other embodiments, address/data converter chip 40* can be stacked in three-dimensional array chip 30, or three-dimensional array chip 30 is stacked Face to face with address/data converter chip 40*, or three-dimensional array chip 30 and address/data converter chip 40* place side by side.
3D-M in Figure 10 BVMulti-chip package 60 is containing at least two three-dimensional array chip 30a, a 30b and address/data converter chip 40*.These chips 30a, 30b and 40* are three single chips.They are positioned in same encapsulating shell 61.Wherein, three-dimensional array chip 30a is stacked on three-dimensional array chip 30b, and three-dimensional array chip 30b is stacked on address/data converter chip 40*.Lead-in wire 65 provides electrical connection for chip 30a, 30b and 40*.
Separation 3D-M in Figure 10 CVAssembly 60 is containing a component framework 76.This framework 76 is containing two single encapsulation: cubical array encapsulation 72 and peripheral circuit encapsulation 74.Wherein, cubical array encapsulation 72 is containing two three-dimensional array chip 30a, 30b, and peripheral circuit encapsulation 74 is containing address/data converter chip 40*.Framework 76 is also for cubical array encapsulation 72 and peripheral circuit encapsulation 74 offer electrical connection (not shown here).
Figure 11 A-Figure 11 C is the circuit block diagram of three kinds of voltage generators.Voltage generator is preferably used DC-DC converter (DC-DC converter).DC-DC converter includes booster and reducing transformer.The output voltage of booster is higher than input voltage, and the input voltage of reducing transformer is lower than input voltage.The example of booster includes electric charge pump (charge
Pump, Figure 11 A) and Boost (Boost converter, Figure 11 B) etc..The example of reducing transformer includes low dropout voltage regulator (low dropout, Figure 11 C) and Buck changer (Buck converter) etc..
Voltage generator in Figure 11 A includes an electric charge pump 71, its output voltage VoutMore than input voltage Vin.It is, in general, that electric charge pump 71 is possibly together with one or more electric capacity.Voltage generator in Figure 11 B includes a high frequency Boost 73, its output voltage VoutMore than input voltage Vin.Boost 73 is possibly together with inductance.This inductance is preferably a thin inductance, to meet the requirement to thickness of storage card or solid state hard disc.Voltage generator in Figure 11 C includes a low dropout voltage regulator 75, its output voltage VoutLess than input voltage Vin.It is, in general, that low dropout voltage regulator 75 is possibly together with one or more electric capacity.
Figure 12 A-Figure 12 B represents two assemblies of address/data transducer 49 respectively: address translator 43 and data converter 45.Figure 12 A represents a kind of address translator 43.Logical address 54A of main frame is converted into the physical address 58A of 3D-M nucleus 22 by it.Address translator 43 is containing a processor 92 and a memorizer 94.Memorizer 94 stores address mapping table 82, trouble block table 84 and a wear management table 86.These state tables 82,84,86 are stored in read only memory (ROM) time flat.It is loaded in use in random-access memory (ram).Here, read only memory can a kind of nonvolatile memory (NVM), such as flash memory.For an address/data converter chip 40* supporting many three-dimensional array chip (such as 30a, 30b in Fig. 3 C ... 30w), memorizer 94 is all three-dimensional array chip 30a, 30b ... 30w stores state table 82,84,86, and it is by all three-dimensional array chip 30a, 30b ... 30w shares.
In the various state tables 82,84,86 of memorizer 94, address mapping table 82 stores the mapping between logical address and physical address；Trouble block table 84 stores the address of out of order memory block in three-dimensional memory array；The number of times of each memory block read/write noted down by wear management table 86.Here, " memory block " refers to the allocation unit of memorizer, and its size can be from the first all storage units to a three-dimensional memory array of storage.
In read procedure, once processor 92 receives logical address 54A of the memory block needing reading, and it obtains corresponding physical address 58A from address mapping table 82.During writing, once processor 92 receives logical address 54A of the memory block needing write, and it selects the memory block of vacant a, fault-free and less use to write data from address mapping table 82, trouble block table 84 and wear management table 86.The address of this selected memory block is physical address.
Figure 12 B represents a kind of data converter 45.The logical data 54D of main frame is converted into physical data 58D of three-dimensional memory array by it, or physical data 58D of three-dimensional memory array is converted into the logical data 54D of main frame.Data converter 45 is containing error checking correction (ECC) encoder 96 and an ECC decoder 98.The logical data 54D of input is converted into physical data 58D storing three-dimensional memory array by ECC encoder 96.Physical data 58D read from three-dimensional memory array is converted into logical data 54D to be output by ECC decoder 98.In this process, the error bit in physical data 58D is examined and correction.The ECC encryption algorithm being suitable for 3D-M includes Reed-Solomon code, Golay code, BCH code, multidimensional parity code and Hamming code etc..
It should be appreciated that on the premise of not away from the spirit and scope of the present invention, can be modified the form of the present invention and details, this does not hinder the spirit of they application present invention.Therefore, except the spirit according to appended claims, the present invention should not be restricted by any restriction.
Claims (10)
1. the three-dimensional longitudinal memorizer (3D-M separatedV) (50), it is characterised in that including:
One contains at least one 3D-MVThe three-dimensional array chip (30) of array (36), this 3D-MV array (36) is containing multiple vertical strings (16X, 16Y) that store, and the storage containing multiple vertical stackings of each vertical storage string is first (8a-8h)；
The one address/data converter chip (40*) containing at least part of address/data converter, this address/data transducer carries out address and/or data conversion between main frame and this three-dimensional array chip (30)；
Described three-dimensional array chip (30) does not contains described partial address/data converter, vertically storing the interconnection line number of plies more than described address/data converter chip (40*) of storage unit (8a-8h) number contained by string (16X) in described three-dimensional array chip (30), described three-dimensional array chip (30) is two different chips with described address/data converter chip (40*).
2. the three-dimensional longitudinal memorizer (3D-M separatedV) (50), it is characterised in that including:
One contains at least one 3D-MVThe three-dimensional array chip (30) of array (36) and a peripheral circuit (38), this 3D-MVArray (36) is containing multiple vertical storages string (16X, 16Y), and this peripheral circuit (38) is positioned at this 3D-MVOutside array (36)；
The one address/data converter chip (40*) containing at least part of address/data converter, this address/data transducer carries out address and/or data conversion between main frame and this three-dimensional array chip (30)；
Described three-dimensional array chip (30) does not contains described partial address/data converter, the interconnection line number of plies of described address/data converter chip (40*) is more than the interconnection line number of plies of described peripheral circuit (38), and described three-dimensional array chip (30) is two different chips with described address/data converter chip (40*).
3. the three-dimensional longitudinal memorizer (3D-M separatedV) (50), it is characterised in that including:
One contains at least one 3D-MVThe three-dimensional array chip (30) of array (36) and a peripheral circuit (38), this 3D-MVArray (36) is containing multiple vertical storages string (16X, 16Y), and this peripheral circuit (38) is positioned at this 3D-MVOutside array (36)；
The one address/data converter chip (40*) containing at least part of address/data converter, this address/data transducer carries out address and/or data conversion between main frame and this three-dimensional array chip (30)；
Described three-dimensional array chip (30) does not contains described partial address/data converter, described peripheral circuit (38) and described address/data converter chip (40*) are containing different interconnection material, and described three-dimensional array chip (30) is two different chips with described address/data converter chip (40*).
4. according to the memorizer described in claim 1-3, it is further characterized in that: described 3D-MVIt is a longitudinal NAND.
5. according to the memorizer described in claim 1-3, it is further characterized in that: described 3D-MVIt is 3 D ROM (3D-ROM) or three-dimensional random reading memorizer (3D-RAM).
6. according to the memorizer described in claim 1-3, it is further characterized in that: described separation 3D-MVIt is at least one in storage card, solid state hard disc, multi-chip package and multi-chip module.
7. according to the memorizer described in claim 1-3, it is further characterized in that: containing another three-dimensional array chip, this address/data converter chip (40*) address/data transducer containing another three-dimensional array chip described.
8. according to the memorizer described in claim 1-3, it is further characterized in that: this address/data transducer contains address translator (43) and/or data converter (45).
Memorizer the most according to claim 3, is further characterized in that: described peripheral circuit (18) contains high temperature resistant interconnection material.
Memorizer the most according to claim 3, is further characterized in that: described address/data converter chip (40*) contains high-performance interconnection material.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060097279A1 (en) * | 2004-11-05 | 2006-05-11 | Guobiao Zhang | Three-Dimensional Memory System-on-a-Chip |
| CN101236780A (en) * | 2008-02-26 | 2008-08-06 | 中国科学院上海微系统与信息技术研究所 | Circuit design standard and implementation method for 3-D solid structure phase change memory chip |
| CN103050149A (en) * | 2011-10-13 | 2013-04-17 | 三星电子株式会社 | Nonvalatile memory device and programming method and memory device system including the nonvalatile memory device |
| CN103632699A (en) * | 2012-08-22 | 2014-03-12 | 成都海存艾匹科技有限公司 | Three-dimensional memory containing address/data converter chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060097279A1 (en) * | 2004-11-05 | 2006-05-11 | Guobiao Zhang | Three-Dimensional Memory System-on-a-Chip |
| CN101236780A (en) * | 2008-02-26 | 2008-08-06 | 中国科学院上海微系统与信息技术研究所 | Circuit design standard and implementation method for 3-D solid structure phase change memory chip |
| CN103050149A (en) * | 2011-10-13 | 2013-04-17 | 三星电子株式会社 | Nonvalatile memory device and programming method and memory device system including the nonvalatile memory device |
| CN103632699A (en) * | 2012-08-22 | 2014-03-12 | 成都海存艾匹科技有限公司 | Three-dimensional memory containing address/data converter chip |
| CN103633091A (en) * | 2012-08-22 | 2014-03-12 | 成都海存艾匹科技有限公司 | Three-dimensional memory (3D-M) with integrated intermediate circuit chip |
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