CN105990351A - Separated three-dimensional vertical memory - Google Patents
Separated three-dimensional vertical memory Download PDFInfo
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- CN105990351A CN105990351A CN201510088410.0A CN201510088410A CN105990351A CN 105990351 A CN105990351 A CN 105990351A CN 201510088410 A CN201510088410 A CN 201510088410A CN 105990351 A CN105990351 A CN 105990351A
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Abstract
The present invention provides a separated 3D-MV50 which includes at least one three-dimensional array chip 30 and at least one voltage generation chip 40. The three-dimensional array chip 30 includes a plurality of vertical storage strings 16X and 16Y. At least one voltage generator assembly is located in the voltage generation chip 40 and is not located in the non-three-dimensional array chip 30. The three-dimensional array chip 30 and the voltage generation chip 40 have completely different back-end (BEOL) structure.
Description
Technical field
The present invention relates to integrated circuit memory field, more precisely, relate to three-dimensional longitudinal memory.
Background technology
Three-dimensional longitudinal memory (three-dimensional vertical
Memory, referred to as 3D-MV) it is a kind of monomer (monolithic) semiconductor memory, it contains multiple vertical storage string.3D-MVIncluding 3 D ROM (3D-ROM) and three-dimensional random read memory (3D-RAM).3D-ROM can be further divided into three-dimensional masking film program read-only memory (3D-MPROM) and three-dimensional electric programming read-only memory (3D-EPROM).Based on its programming mechanism, 3D-MVMemristor, resistive random-access can be contained
Memory(RRAM or ReRAM), phase-change memory(PCM), programmable metallization
Or conductive-bridging memory(PMM)
Random-access memory(CBRAM) etc..
United States Patent (USP) 8,638,611 discloses a kind of 3D-MV, it is a kind of longitudinal NAND(vertical NAND).As it is shown in figure 1, this 3D-MVChip 20V contains at least one 3D-MVArray 16V and peripheral circuit 18.3D-MVArray 16V contains multiple vertical storage string 16X, 16Y.Storage unit (such as 8a-8h) containing multiple vertical stackings for each storage string (such as 16X).These storage units are intercoupled by a vertical address wire.Each storage unit (such as 8f) contains a vertical transistor, and this vertical transistor contains grid the 6th, storage film 7 and longitudinal channel 9.Peripheral circuit 18 contains transistor 0t and interconnection line 0i thereof.Transistor 0t is formed in Semiconductor substrate 0, and it is traditional planar ransistor.Interconnection line 0i is that transistor 0t realizes being connected with each other.In FIG, substrate interconnection line 0i contains metal level 0M1,0M2.
Peripheral circuit 18 is 3D-MVArray 16V produces read/write voltage and/or conversion address/data.Particularly, the supply voltage that the external world provides is converted into read voltage and/or writes voltage by it, it is possible to extraneous logical address/data are converted into 3D-MVPhysical address/the data of array 16V.The 3D-M of prior artVIt is a kind of integrated 3D-MV, i.e. 3D-MVArray 16V and peripheral circuit 18 thereof are integrated in same chip 20V.It is to say, 3D-MVChip 20V produces read/write voltage and/or conversion address/data in inside.Due to 3D-MVVertically storage string 16X, 16Y take substrate 0 below, peripheral circuit 18 can be only positioned at 3D-MVOutside array 16V.
The Main Viewpoints of prior art is: integrated reduction cost.Unfortunately, this viewpoint is to 3D-MVIt is false.For 3D-MVFor, owing to vertical storage string 16X, 16Y have employed complicated rear end (BEOL) technique, and the backend process of peripheral circuit 18 is simpler, therefore it is exactly to have to be gone here and there the expensive process flow process of 16X, 16Y and manufactured peripheral circuit 18 by manufacturing storage by storage string 16X, 16Y and the integrated direct result of peripheral circuit 18 blindly, this not only can not reduce cost, can increase cost on the contrary.
Content of the invention
The main object of the present invention is to provide a kind of more cheap three-dimensional longitudinal memory (3D-MV).
It is another object of the present invention to improve 3D-MVArray efficiency.
In order to realize these and other purpose, the present invention defers to following design principle: three-dimensional circuit and two-dimensional circuit are separated to different chip, in order to be separately optimized them.In order to improve the array efficiency of three-dimensional array chip, the peripheral circuit on it should be reduced as far as possible.For example say, can be by 3D-MVVoltage generator be separated in another one chip.Correspondingly, the present invention proposes a kind of separation 3D-MV, it contains at least one three-dimensional array chip and at least one voltage generator chip.Three-dimensional array chip (three-dimensional circuit) builds in three dimensions and contains multiple functional layers, and voltage generator chip (two-dimensional circuit) builds in two-dimensional space and comprises only a functional layer.Owing to Voltage generator component is to realize 3D-MVThe required assembly of function, the three-dimensional array chip itself without Voltage generator component is not a storage chip that can work alone.Separate 3D-MVBring a benefit: three-dimensional array chip has higher array efficiency.
Separating 3D-MVIn, owing to three-dimensional array chip and voltage generator chip can separately design and manufacture, they can have different rear end (BEOL) structures: voltage generator chip can be containing less rear end film.Although three-dimensional array chip and integrated 3D-MVThe wafer cost of chip is close, but owing to voltage generator chip can use independent, cheap backend process flow process to manufacture, its wafer cost is relatively low.Therefore, for identical memory capacity, 3D-M is separatedVTotle drilling cost be less than integrated 3D-MV。
The present invention proposes a kind of separation 3D-MV(50), it is characterised in that include: one contains at least one 3D-MVThe three-dimensional array chip (30) of array (16V), this 3D-MVArray (16V) is containing multiple vertical storages string (16X, 16Y), and each vertically stores string storage unit (8a-8h) containing multiple vertical stackings；The one voltage generator chip (40) containing at least part of voltage generator, this voltage generator is that this three-dimensional array chip (30) provides at least one and supply voltage (VDD) different read voltage (VR) and/or write voltage (VW)；Described three-dimensional array chip (30) does not contains described portion voltage generator, described three-dimensional array chip (30) contains more rear end film than described voltage generator chip (40), and described three-dimensional array chip (30) is two different chips with described voltage generator chip (40).
Brief description
Fig. 1 is a kind of integrated 3D-MVThe sectional view of chip (prior art).
Fig. 2 A is a kind of separation 3D-MVSchematic diagram, Fig. 2 B is this separation 3D-MVCircuit block diagram.
Fig. 3 is another kind of separation 3D-MVSchematic diagram.
Fig. 4 is a kind of separation 3D-MVThe sectional view of middle three-dimensional array chip.
Fig. 5 is this separation 3D-MVThe sectional view of middle voltage generator chip.
Fig. 6 A-Fig. 6 C is the circuit diagram of three kinds of voltage generators.
Fig. 7 A-Fig. 7 C is three kinds and separates 3D-MVSectional view.
Noticing, these accompanying drawings are only synoptic diagrams, and their nots to scale (NTS) are drawn.For the sake of obvious and convenient, portion size and structure in figure may zoom in or out.In different embodiments, identical symbol typicallys represent correspondence or similar structure.
Detailed description of the invention
In the present invention, "/" represent " with " or the relation of "or".For example, read/write voltage represents read voltage or writes voltage or read voltage and write voltage；Address/data represents address or data or address and voltage.
Fig. 2 A-Fig. 2 B represents a kind of and separates 3D-MV50.It contains a three-dimensional array chip 30(three-dimensional circuit) and a voltage generator chip 40(two-dimensional circuit).Wherein, three-dimensional array chip 30 builds in three dimensions and contains multiple functional layers (i.e. accumulation layer), and voltage generator chip 40 builds in two-dimensional space and comprises only a functional layer.Three-dimensional circuit and two-dimensional circuit are separated to they can be separately optimized by different chip.
Separation 3D-M in Fig. 2 AV50 is a 3D-MVStorage card, it includes that one can realize physical connection the interface 54 according to a kind of communication standard communication with various main frames.Interface 54 includes multiple contact jaw 52a, 52b, 54a-54d, and they can contact jaw corresponding with main frame socket couple.Wherein, power end 52a couples with the electrical power contacts end of main frame, and main frame is referred to as supply voltage V by the power supply that power end 52a providesDD；Earth terminal 52b is for separating 3D-MV50 offer ground voltage VSS；Signal end 54a-54d is main frame and separates 3D-MV50 offer signal exchange, these signals include address/data.Owing to these address/data are directly used by main frame, they are logical address/data.
Voltage generator chip 40 obtains supply voltage V at power end 52DD, convert thereof into read/write voltage, and provide this read/write voltage by power bus 56 to three-dimensional array chip 30.Read/write voltage can be merely read voltage VR, or only write voltage VW, or include read voltage V simultaneouslyRWith write voltage VW；Additionally, VRAnd VWWith VDDThere is different numerical value.In the present embodiment, read/write voltage includes read voltage VRWrite voltage V with twoW1、VW2.In other embodiments, read/write voltage can include more than one read voltage or two write voltage.
Fig. 2 B is to separate 3D-MVThe circuit block diagram of 50.Three-dimensional array chip 30 contains multiple 3D-MVArray 22aa, 22ay ... and decoder the 24th, 24G.Voltage produces chip 40 and is positioned between the overall decoder 24G of three-dimensional array chip 30 and interface 54.It contains at least one 3D-MVVoltage generator component.With integrated 3D-MVDifference, this assembly is positioned at voltage and produces chip 40, rather than in three-dimensional array chip 30.Owing to this assembly is to realize 3D-MVThe required assembly of function, the three-dimensional array chip 30 itself without Voltage generator component is not a storage chip that can work alone.
3D-MVVoltage generator can contain multiple Voltage generator component, such as band-gap reference circuit (accurate reference voltage source) 40B, read voltage generator 40R and electric charge pump 40W.Wherein, read voltage generator 40R produces read voltage VR, electric charge pump 40W produces and writes voltage VW(with reference to United States Patent (USP) 6,486,728).Fig. 6 A-Fig. 6 C discloses the example of more voltage generator.
Separation 3D-M in Fig. 3V50 can be used as large-capacity memory card or solid state hard disc, and it contains multiple three-dimensional array chip 30a, 30b ... 30w.Voltage generator chip 40 provides read/write voltage by power bus 56 for these three-dimensional array chip.Logical address/data from contact jaw 54a-54d are converted to physical address/data by converter chip 60.Three-dimensional array chip forms two passage: A and B.In passage A, internal bus 58A is three-dimensional array chip 30a, 30b ... 30i provides physical address/data；In passage B, internal bus 58B is three-dimensional array chip 30r, 30s ... 30w provides physical address/data.Although the present embodiment only has two passages, for the personage being familiar with this specialty, large-capacity memory card and solid state hard disc can contain more multichannel.
Fig. 4 is to separate 3D-MVThe sectional view of three-dimensional array chip 30 in 50.Three-dimensional array chip 30 is formed in three dimensions, and containing multiple storage string 16X, 16Y.Storage unit (such as 8a-8h) containing multiple vertical stackings for each storage string (such as 16X).These storage units are intercoupled by a vertical address wire.Each storage unit (such as 8f) contains a vertical transistor, and this vertical transistor contains grid the 6th, storage film 7 and longitudinal channel 9.One 3D-MVExample be longitudinal NAND(vertical NAND).Due to the storage unit containing 24 to 256 vertical stackings for the longitudinal NAND storage string, the rear end film containing Numerous (24 to 256 layers) for the three-dimensional array chip 30.
Fig. 5 is to separate 3D-MVThe sectional view of voltage generator chip 40 in 50.Voltage generator chip 40 is formed in two-dimensional space, and comprises only a functional layer, i.e. substrate layer 0K '.Substrate layer 0K ' includes transistor 0t and interconnection line 0iB thereof.Transistor 0t is formed on voltage generator substrate 0B, and interconnection line 0iB includes two metal level 0M1 '-0M2 '.Owing to each metal level (such as 0M1 ') contains 2 two-layer rear end films, voltage produces chip 40 and altogether comprises only 4 layers of rear end film.
Separating 3D-MVIn 50, owing to three-dimensional array chip 30 and voltage generator chip 40 can separately design and manufacture, they can have different rear end structures: voltage generator chip 40 can be containing less rear end film.Although three-dimensional array chip 30 and integrated 3D-MVThe wafer cost of chip 20V is close, but owing to voltage generator chip 40 can use independent, cheap backend process flow process to manufacture, its wafer cost is relatively low.Therefore, for identical memory capacity, 3D-M is separatedVThe totle drilling cost of 50 is less than integrated 3D-MV 20V。
For conventional two dimensional memory (2D-M, storage unit is distributed on two dimensional surface, such as flash memory), although also can be as separating 3D-MVEqually being separated to 2D-M array and voltage generator on different chip, do so can increase totle drilling cost.This is because two-dimensional array chip produces chip with voltage has similar rear end structure and close wafer cost, add extra packaging cost, separate 2D-M more expensive than integrated 2D-M.This and 3D-MVQuite different.3D-MVMiddle three-dimensional array chip 30 and voltage produce chip 40 and have different rear end structures, therefore separate 3D-MVThan integrated 3D-MVInexpensively.
Fig. 6 A-Fig. 6 C is the circuit diagram of three kinds of voltage generators.Voltage generator is preferably used DC-DC converter (DC-DC converter).DC-DC converter includes stepup transformer and reducing transformer.The output voltage of stepup transformer is higher than input voltage, and the input voltage of reducing transformer is lower than input voltage.The example of stepup transformer includes electric charge pump (charge pump, Fig. 6 A) and Boost (Boost converter, Fig. 6 B) etc..The example of reducing transformer includes low dropout voltage regulator (low dropout, Fig. 6 C) and Buck converter (Buck converter) etc..
Voltage generator in Fig. 6 A includes an electric charge pump 72, its output voltage VoutMore than input voltage Vin.It is, in general, that electric charge pump 72 is possibly together with one or more electric capacity.Voltage generator in Fig. 6 B includes a high frequency Boost 74, its output voltage VoutMore than input voltage Vin.Boost 74 is possibly together with inductance.This inductance is preferably a thin inductance, to meet the requirement to thickness of storage card or solid state hard disc.Voltage generator in Fig. 6 C includes a low dropout voltage regulator 76, its output voltage VoutLess than input voltage Vin.It is, in general, that low dropout voltage regulator 76 is possibly together with one or more electric capacity.
Fig. 7 A-Fig. 7 C is three kinds and separates 3D-MVSectional view.Separation 3D-M in Fig. 7 A-Fig. 7 BVIt is a kind of multi-chip package (MCP).Wherein, the 3D-M in Fig. 7 AVMulti-chip package 60 is containing two single chips: a three-dimensional array chip 30 and a voltage generator chip 40.The 30th, chip 40 is stacked in a package substrate (interposer) 63 and is positioned in same encapsulating shell 61.The 30th, lead-in wire (bond wire) 65 40 provide electrical connection for chip.Except lead-in wire, soldered ball (solder bump) etc. can also be used.In order to guarantee data security, the 30th, chip 40 is preferably enclosed in a moulding compound (molding compound) 67.In the present embodiment, three-dimensional array chip 30 is stacked on voltage generator chip 40.In other embodiments, voltage generator chip 40 can be stacked in three-dimensional array chip 30, or three-dimensional array chip 30 is stacked Face to face with voltage generator chip 40, or three-dimensional array chip 30 and voltage generator chip 40 are placed side by side.
3D-M in Fig. 7 BVMulti-chip package 60 is containing at least two three-dimensional array chip 30a, 30b and a voltage generator chip 40.These chips 30a, 30b and 40 is three single chips.They are positioned in same encapsulating shell 61.Wherein, three-dimensional array chip 30a is stacked on three-dimensional array chip 30b, and three-dimensional array chip 30b is stacked on voltage generator chip 40.Lead-in wire 65 is chip 30a, 30b and 40 offer electrical connections.
Separation 3D-M in Fig. 7 CVIt is a 3D-MVMulti-chip module (MCM) 60, it contains a framework 76.This framework 76 contains two single encapsulation: cubical array encapsulation 72 and voltage generator encapsulate 74.Wherein, cubical array encapsulation 72 contains two three-dimensional array chip 30a, 30b, and voltage generator encapsulation 74 contains voltage generator chip 40.Framework 76 is also for cubical array encapsulation 72 and voltage generator encapsulation 74 offer electrical connection (not shown here).
It should be appreciated that on the premise of not away from the spirit and scope of the present invention, can be modified the form of the present invention and details, this does not hinder them to apply the spirit of the present invention.Therefore, except the spirit according to appended claims, the present invention should not be restricted by any restriction.
Claims (10)
1. the three-dimensional longitudinal memory (3D-M separatingV) (50), it is characterised in that include:
One contains at least one 3D-MVThe three-dimensional array chip (30) of array (16V), this 3D-MV array (16V) is containing multiple vertical storages string (16X, 16Y), and each vertically stores string storage unit (8a-8h) containing multiple vertical stackings；
The one voltage generator chip (40) containing at least part of voltage generator, this voltage generator is that this three-dimensional array chip (30) provides at least one and supply voltage (VDD) different read voltage (VR) and/or write voltage (VW)；
Described three-dimensional array chip (30) does not contains described portion voltage generator, described three-dimensional array chip (30) contains more rear end (BEOL) film than described voltage generator chip (40), and described three-dimensional array chip (30) is two different chips with described voltage generator chip (40).
2. memory according to claim 1, is further characterized in that: a vertical transistor is contained in each described storage unit.
3. memory according to claim 2, is further characterized in that: described vertical transistor contains a longitudinal channel.
4. memory according to claim 1, is further characterized in that: described 3D-MVIt is longitudinal NAND(vertical NAND).
5. memory according to claim 1, is further characterized in that: described 3D-MVIt is 3 D ROM (3D-ROM) or three-dimensional random reading memory (3D-RAM).
6. memory according to claim 1, is further characterized in that: described 3D-MV3D-memristor, 3D-RRAM or 3D-ReRAM, the one in 3D-PCM, 3D-PMC and 3D-CBRAM.
7. memory according to claim 1, is further characterized in that: described voltage generator chip (40) contains a DC-DC converter (DC-DC converter).
8. memory according to claim 7, is further characterized in that: this DC-DC converter is electric charge pump (charge
Pump), the one in Boost (Boost converter), low dropout voltage regulator (low dropout) and Buck converter (Buck converter).
9. memory according to claim 1, is further characterized in that: described separation 3D-MVIt is at least one in storage card, solid state hard disc, multi-chip package and multi-chip module.
10. memory according to claim 1, is further characterized in that: contain another three-dimensional array chip, and this voltage produces the voltage generator that chip contains another three-dimensional array chip described.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510088410.0A CN105990351A (en) | 2015-02-26 | 2015-02-26 | Separated three-dimensional vertical memory |
| CN202010369182.5A CN111584490A (en) | 2015-02-26 | 2015-02-26 | Separated three-dimensional longitudinal memory |
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| CN201510088410.0A CN105990351A (en) | 2015-02-26 | 2015-02-26 | Separated three-dimensional vertical memory |
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| CN201510088410.0A Pending CN105990351A (en) | 2015-02-26 | 2015-02-26 | Separated three-dimensional vertical memory |
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| US20100162065A1 (en) * | 2008-12-19 | 2010-06-24 | Unity Semiconductor Corporation | Protecting integrity of data in multi-layered memory with data redundancy |
| US8921991B2 (en) * | 2011-09-01 | 2014-12-30 | Chengdu Haicun Ip Technology Llc | Discrete three-dimensional memory |
| WO2014134865A1 (en) * | 2013-03-06 | 2014-09-12 | Zhang Guobiao | Three-dimensional memory comprising independent intermediate circuit chip |
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- 2015-02-26 CN CN202010369182.5A patent/CN111584490A/en active Pending
- 2015-02-26 CN CN201510088410.0A patent/CN105990351A/en active Pending
Patent Citations (7)
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|---|---|---|---|---|
| CN1447429A (en) * | 2001-11-18 | 2003-10-08 | 张国飙 | Design of 3D storage |
| CN1467844A (en) * | 2002-06-10 | 2004-01-14 | ������������ʽ���� | Semiconductor integrated circuit device |
| CN101110425A (en) * | 2002-11-17 | 2008-01-23 | 张国飙 | Three-dimensional electric programming read-only memory |
| CN1811986A (en) * | 2005-01-13 | 2006-08-02 | 三星电子株式会社 | Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage |
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