CN107689377A - Electrical programming memory of three-dimensional containing separation address/data converter - Google Patents
Electrical programming memory of three-dimensional containing separation address/data converter Download PDFInfo
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- CN107689377A CN107689377A CN201610640347.1A CN201610640347A CN107689377A CN 107689377 A CN107689377 A CN 107689377A CN 201610640347 A CN201610640347 A CN 201610640347A CN 107689377 A CN107689377 A CN 107689377A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention proposes a kind of electrical programming memory of three-dimensional of separation（3D‑OTP）50, it contains an at least three-dimensional array chip 30 and an at least address/data converter chip 40.Three-dimensional array chip 30 contains multiple 3D OTP storage members being stacked with.At least an address/data converter is located in address/data converter chip 40, rather than in three-dimensional array chip 30.Three-dimensional array chip 30 and address/data converter chip 40 have different rear ends（BEOL）Structure.
Description
Technical field
The present invention relates to integrated circuit memory field, more precisely, being related to electrical programming memory (3D- of three-dimensional
OTP)。
Background technology
Three-dimensional storage (3D-M) is a kind of monomer (monolithic) semiconductor memory, and it contains multiple be stacked with
Storage member.3D-M includes 3 D ROM (3D-ROM) and three-dimensional random reads memory (3D-RAM).3D-ROM can
To be further divided into three-dimensional masking film program read-only memory (3D-MPROM) and three-dimensional electric programming read-only memory (3D-
EPROM).Based on the number of its energy electrical programming, 3D-EPROM can be further divided into electrical programming memory (3D- of three-dimensional
) and three-dimensional repeatedly electrical programming memory (3D-MTP) OTP.3D-OTP can be 3D-memristor, three-dimensional resistance-variable storing device
(3D-RRAM or 3D-ReRAM), three-dimensional phase transition storage (3D-PCM), 3D-PMM (programmable metallization
) or 3D-CBRAM (conductive-bridging random-access memory) etc. memory.
(the inventor of United States Patent (USP) 5,835,396：Open state's hurricane；Grant date：On November 3rd, 1998) disclose a kind of 3D-
ROM, especially 3D-OTP.As shown in Figure 1A, 3D-OTP chips 20 containing a substrate circuitry layer 0K and it is multiple be stacked in substrate electricity
On the floor 0K of road and accumulation layer 16A, 16B that is stacked with.Substrate circuitry layer 0K contains transistor 0t and its interconnection line 0i.Transistor
0t is formed in Semiconductor substrate 0.In this example, substrate interconnection line 0i contains metal level 0M1,0M2.In this specification
In, metal level 0M1,0M2 that substrate interconnection line 0i is used are referred to as substrate metal layer, and substrate interconnection line 0i is referred to as using material
Substrate interconnection material.
Accumulation layer 16A, 16B is stacked on substrate circuitry layer 0K, and they are by contacting access opening (such as 1av) and substrate 0
Coupling.Each accumulation layer (such as 16A) is first (such as 1aa) containing a plurality of top address line (such as 2a), bottom address wire (such as 1a) and storage.Deposit
Storage member can use diode, transistor or other device.In various storage members, there is minimum using the storage member of diode
Area, it is only~4F2(F is minimum feature size).Diode storage member is typically incorporated in the friendship of top address line and bottom address wire
At crunode, so as to form a crosspoint (cross-point) array.Here, diode refer to it is any with following feature two
End-apparatus part：When the numerical value of its applied voltage is opposite with read voltage less than the direction of read voltage or applied voltage, its resistance is long-range
In its resistance under read voltage.The example of diode includes semiconductor diode (such as p-i-n silicon diodes) and metal oxygen
Compound diode (such as titanium oxide diode, nickel oxide diode) etc..
Accumulation layer 16A, 16B forms an at least 3D-OTP arrays 16, and substrate circuitry layer 0K then contains 3D-OTP arrays 16
Peripheral circuit.Wherein, a part of peripheral circuit is located at below 3D-OTP arrays, and they are referred to as array following peripheral circuit；Separately
A part of peripheral circuit is located at outside 3D-OTP arrays, and they are referred to as array neighboring circuit 18.Due to array neighboring electricity
Contain less rear end (back-end-of-line, referred to as BEOL) film layer, array periphery than 3D-OTP array 16 in road 18
The space 17 of the top of side circuit 18 does not contain storage member, and the space is actually wasted.In this manual, a rear end is thin
Film layer refers to a conductor layer in substrate structure, such as the address-wire layer or interconnection line in accumulation layer 16A, 16B
An interconnection line layer in 0i.In figure ia, 3D-OTP arrays 16 contain 6 rear end film layers, including 2 interconnection line layer 0M1,
Address-wire layer 3a, 4a in 2 address-wire layers 1a, 2a and the second accumulation layer 16B in 0M2, the first accumulation layer 16A；And battle array
Row neighboring circuit 18 comprises only 2 rear end film layers, including interconnection line layer 0M1,0M2.
(the inventor of United States Patent (USP) 7,388,476：Crowley etc.；Grant date：On June 3rd, 2008) disclose a kind of integrate
3D-OTP chips, its cubical array and its peripheral circuit are all integrated in same chip.This integration mode is referred to as fully integrated.
As shown in Figure 1B, the integrated 3D-OTP chips 20 contain cubical array region 22 and peripheral circuit area 28.Cubical array region
22 contain multiple 3D-OTP arrays (such as 22aa, 22ay) and its decoder (such as 24,24G).These decoders 24 include local solve
Code device 24 and overall decoder 24G.Wherein, local decoder 24 decodes to the address/data of single 3D-OTP arrays, whole
Body decoder 24G decodes overall address/data 25 into single 3D-OTP arrays.
Peripheral circuit area 28 contains all peripheral circuit groups for allowing integrated 3D-OTP chips 20 to complete basis function storage
Part, it realizes that voltage, data, address turn between cubical array region 22 and main frame (equipment for directly using the chip 20)
Change.Peripheral circuit 28 contains read/write voltage generator 21 and address/data converter 29.Wherein, read/write voltage generator 21
Supply voltage 23 is converted into read voltage VROr/and write (programming) voltage VW；Address/data converter 29 is by logical address/data
27 mutually change with physical address/data 25.In this manual, logical address/data 27 are address/numbers that main frame uses
According to；And physical address/data 25 are the address/datas that 3D-OTP arrays use.
The Main Viewpoints of prior art are：It is integrated to reduce cost.Unfortunately, the viewpoint is invalid to 3D-OTP.For
For 3D-OTP, because 3D-OTP arrays 16 employ complicated backend process, and the backend process of peripheral circuit 18 is simpler,
Therefore by the integrated direct result of 3D-OTP arrays 16 and peripheral circuit 18 it is exactly blindly to have to manufacture 3D-OTP arrays
16 expensive process flow manufactures peripheral circuit 18, and this can not only reduce cost, can increase cost on the contrary.Further, since
Peripheral circuit 18 can only use and 16 same number of interconnection line layer of 3D-OTP arrays (as only two layers), therefore peripheral circuit 18
Design comparison trouble, poor-performing and required chip area are larger.Finally, due to 3D-OTP storage members typically can be through too high
Warm technique, peripheral circuit 18 need to use resistant to elevated temperatures interconnection material, such as tungsten (W), and these materials can make that 3D-OTP's is whole
Body hydraulic performance decline.
The content of the invention
The main object of the present invention is to provide a kind of more cheap electrical programming memory (3D- of three-dimensional of overall price
OTP)。
It is a further object of the present invention to provide the 3D-OTP that a kind of overall performance is more excellent.
It is a further object of the present invention to provide a kind of smaller 3D-OTP of volume.
In order to realize these and other purpose, the present invention defers to following guideline：By 3D-OTP circuits and its periphery
Circuit is separated to different chips, so as to which they are separately optimized.Such as say, 3D-OTP arrays (three-dimensional circuit) and at least a periphery
Circuit unit (two-dimensional circuit) is separated into two chip-three-dimensional array chips and peripheral circuit chip.Correspondingly, it is of the invention
A kind of 3D-OTP of separation is proposed, it contains a three-dimensional array chip and at least a peripheral circuit chip.Three-dimensional array chip structure
Build in three dimensions and contain multiple functions (storage) layer, it contains the first peripheral circuit component (group of 3D-OTP arrays
Part is referred to as peripheral circuit component in chip)；Peripheral circuit chip structure is in two-dimensional space and comprises only One function layer, it
The second peripheral circuit component containing 3D-OTP arrays (component is referred to as chip neighboring circuit unit).Chip neighboring electricity
Road component is 3D-OTP necessary component, and it can be that 3D-OTP realizes voltage, data and/or address conversion.If 3D-OTP
There is no chip neighboring circuit unit, then it is unable to complete independently basis function storage.
Because they are individually designed and manufacture, separating the three-dimensional array chip in 3D-OTP and peripheral circuit chip has
Different rear end (BEOL) structures.The rear end structure of peripheral circuit chip can have array neighboring circuit with independent optimization
Lower cost, better performance and less area.Generally speaking, 3D-OTP is separated than integrated 3D-OTP with lower whole
Body cost, more preferable overall performance and less entire area.
The peripheral circuit chip of separation can be different from three-dimensional array chip at three aspects.First, peripheral circuit chip
Rear end film layer number it is fewer than three-dimensional array chip a lot.Due to wafer cost it is basic with the number of rear end film layer into
Direct ratio, the wafer cost of peripheral circuit chip will be far below three-dimensional array chip.In one embodiment, three-dimensional array chip
The rear end film number of plies is at least twice of the interconnection line number of plies of peripheral circuit chip.In another embodiment, cubical array core
The address wire number of plies of piece is much larger than the interconnection line number of plies of peripheral circuit chip.The huge spread of these numbers of plies can ensure chip into
This difference is more than using caused additional package cost after isolating construction.Therefore, the holistic cost for separating 3D-OTP is less than integrated 3D-
OTP。
Secondly, the peripheral circuit chip separated in 3D-OTP contains more interconnection line layers, chip than three-dimensional array chip
The design of neighboring circuit is simpler, performance is more excellent, chip area is also smaller.Therefore, 3D-OTP globality is separated
Integrated 3D-OTP can be better than with entire area.Similar with integrated 3D-OTP, the interconnection line of three-dimensional array chip does not include any deposit
Storage structure, its interconnection line number of plies are those that the interconnection line number of plies is larger in array following peripheral circuit and array neighboring circuit.Note
Anticipate and arrive, although the interconnection line number of plies of peripheral circuit chip wishes larger, but still no more than the rear end film of three-dimensional array chip
The number of plies.One preferable pattern is：The interconnection line number of plies of peripheral circuit chip is more than the interconnection line number of plies of three-dimensional array chip,
But much smaller than the rear end film number of plies of three-dimensional array chip.
Finally, peripheral circuit chip and three-dimensional array chip contain different interconnection materials.Peripheral circuit chip it is mutual
Line can use High Speed Interconnect Lines material, such as copper (Cu) or high K medium, and three-dimensional array chip can only use high temperature to interconnect
Wire material (such as tungsten or silica).High Speed Interconnect Lines material is higher than high temperature interconnection material speed, and this can improve 3D-OTP's
Overall performance.
Brief description of the drawings
Figure 1A is a kind of sectional view of 3D-OTP in the prior art；Figure 1B is a kind of integrated 3D-OTP chips (prior art)
Circuit block diagram；Fig. 1 C are a kind of sectional views of unprogrammed 3D-OTP storages member；Fig. 1 D are that a kind of 3D-OTP that programmed stores member
Sectional view.
Fig. 2A-Fig. 2 D are four kinds of separation 3D-OTP circuit block diagrams.
Fig. 3 A- Fig. 3 B are the sectional views of three-dimensional array chip in two kinds of separation 3D-OTP.
Fig. 4 A- Fig. 4 B are the sectional views of peripheral circuit chip in two kinds of separation 3D-OTP.
Fig. 5 A- Fig. 5 B are the first separation 3D-OTP allocation models.
Fig. 6 A- Fig. 6 B are second of separation 3D-OTP allocation models.
Fig. 7 A- Fig. 7 C are the third separation 3D-OTP allocation models.
Fig. 8 A- Fig. 8 B are the 4th kind of separation 3D-OTP allocation models.
Fig. 9 A- Fig. 9 B are the circuit block diagrams of two kinds of peripheral circuit chips for supporting more three-dimensional array chips.
Figure 10 A- Figure 10 C are the sectional views of three kinds of separation 3D-OTP encapsulation (or module).
Figure 11 A- Figure 11 C are the circuit block diagrams of three kinds of voltage generators.
Figure 12 A are a kind of circuit block diagrams of address translator；Figure 12 B are a kind of circuit block diagrams of data converter.
It is noted that these accompanying drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and be convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.
Embodiment
In the present invention, "/" represent " and " or "or" relation.For example, read/write voltage represent read voltage or write voltage,
Or read voltage and write voltage；Address/data represents address or data or address and voltage.
Fig. 1 C and Fig. 1 D represent that two kinds of 3D-OTP store first 1aa, 1ab respectively.Wherein, it is unprogrammed to store first 1aa, and stores
First 1ab has been programmed.First 1aa and 1ab are stored containing Top electrode 1a (i.e. the first address-wire layer), diode film 1*, antifuse film
1** and bottom electrode (i.e. the second address-wire layer).Diode film 1* function and diode (also referred to as steering component or selection member
Part) it is similar.Antifuse film 1** has big resistance before programming.In one embodiment, antifuse film 1** contains one layer of oxidation
Silicon thin film.After a program voltage and program current, antifuse film 1** is breakdown, and storing first 1ab has low resistance.
Fig. 2A-Fig. 2 D are four kinds of separation 3D-OTP circuit block diagrams.Separating 3D-OTP 50 can be real with various main frames including one
Show physical connection and according to a kind of interface 54 of communication standard communication.Interface 54 includes multiple contact jaw 52a, 52b, 54a-
54d, they can contact jaw coupling corresponding with main frame socket.For example, main frame is respectively by power end 52a and earth terminal 52b
Separate 3D-OTP 50 and supply voltage V is providedDDWith ground voltage VSS；Main frame is by signal end 54a-54d with separating 3D-OTP
50 exchanging address/data.Because these address/datas are directly used by main frame, they are logical address/data.
Separation 3D-OTP 50 contains a three-dimensional array chip 30 and an at least peripheral circuit chip 40/40*.3D-OTP's
At least a chip neighboring circuit unit is located at peripheral circuit chip 40/40*, rather than positioned at three-dimensional array chip 30.Outside chip
Peripheral circuit component is 3D-OTP necessary component, and it can be that 3D-OTP realizes voltage, data and/or address conversion.If
The not no chip neighboring circuit unit of three-dimensional array chip, then it be unable to complete independently basis function storage.
Separation 3D-OTP 50 in Fig. 2A is a 3D-OTP storage cards, and its peripheral circuit chip 40 contains a read/write voltage
Generator.Read/write voltage generator obtains supply voltage V at main frameDD, read/write voltage is converted thereof into, and it is total by power supply
Line 56 provides the read/write voltage to three-dimensional array chip 30.Here, read/write voltage can be merely read voltage VROr it is only to write
Voltage VWOr simultaneously it is read voltage VRWith write voltage VW, it is with supply voltage VDDWith different numerical value.In the present embodiment kind,
Read/write voltage includes a read voltage VRVoltage V is write with twoW1、VW2.In other embodiments, read/write voltage can be included not
Only a read voltage or two write voltage.
Separation 3D-OTP 50 in Fig. 2 B is a 3D-OTP storage cards, and its peripheral circuit chip 40 contains an address/data
Conversion.Address/data converter is by the logical address on external bus 57 (including signal on contact jaw 54a-54d)
Mutually changed with the physical address on internal bus 58；Can also be by the logical data on external bus 57 and internal bus 58
Physical data mutually change.Here, address/data converter 40* can only realize address conversion or only realize that data turn
Change or realize address and data conversion simultaneously.
Separation 3D-OTP 50 in Fig. 2 C is still a 3D-OTP storage cards, and it contains two Hes of peripheral circuit chip 40
40*.Wherein, peripheral circuit chip 40 then contains a core containing the outer read/write voltage generator of a chip, peripheral circuit chip 40*
Outer address/the data converter of piece.
Separation 3D-OTP 50 in Fig. 2 D is a Large Copacity 3D-OTP storage cards or a 3D-OTP solid state hard discs.It contains
Two peripheral circuit chips 40 and 40* and multiple three-dimensional array chips 30a, 30b...30w.Wherein, peripheral circuit chip 40
Containing read/write voltage generator, peripheral circuit chip 40* outside a chip then containing address/data converter outside a chip.These
Three-dimensional array chip forms two passages：A and B.In passage A, the internal bus 58A from peripheral circuit chip 40* is three-dimensional
Array chip 30a, 30b ... 30i provide physical address/data, in passage B, the internal bus from peripheral circuit chip 40*
58B is that three-dimensional array chip 30r, 30s ... 30w provides physical address/data.Meanwhile from the power supply of peripheral circuit chip 40
Bus 56 provides read/write voltage for dimension array chip 30a, 30b ... 30w.Although the present embodiment only has two passages, for being familiar with
For this professional personage, Large Copacity 3D-OTP storage cards and 3D-OTP solid state hard discs can contain more multichannel.
Fig. 3 A represent the three-dimensional array chip 30 in a kind of separation 3D-OTP.The three-dimensional array chip 30 contains at least one
3D-OTP arrays 36 and chip inner rim circuit unit 38.3D-OTP arrays 36 are formed in three dimensions, and are deposited containing multiple
Reservoir 16A-16D.Each accumulation layer (such as 16A) is containing multiple between upper address wire (such as 2a) and lower address wire (such as 1a)
3D-OTP storages are first (such as 1aa).In this manual, the address wire in same level forms an address-wire layer.It is noted that
The present embodiment is a kind of 3D-OTP of zone isolation, i.e. adjacent storage layers are kept apart by dielectric.Correspondingly, in cubical array
In chip 30, the address wire number of plies is 8, i.e. 1a-8a (address-wire layer 3a-6a is not drawn into)；It is 4 to store the number of plies, i.e. 16A-16D (is deposited
Reservoir 16B, 16C are not drawn into).
Chip inner rim circuit 38 contains transistor 0t and its interconnection line 0iA.The interconnection line of three-dimensional array chip 30 does not wrap
Containing any storage organization, its interconnection line number of plies is that the interconnection line number of plies is larger in array following peripheral circuit and array neighboring circuit
That.In this embodiment, the interconnection line number of plies of three-dimensional array chip 30 is 2, i.e. interconnection line layer 0M1,0M2.
Because 3D-OTP arrays 36 are formed above chip inner rim circuit 38, the rear end film of the three-dimensional array chip 30
The number of plies is the address wire number of plies and interconnection line number of plies sum.In this embodiment, the rear end film number of plies of three-dimensional array chip 30 is
10, including 8 address-wire layers and 2 interconnection line layers.
Fig. 3 B represent the three-dimensional array chip 30 in another separation 3D-OTP 50.It is the 3D- that a kind of interlayer interlocks
OTP, i.e. adjacent storage layers share address-wire layer.As accumulation layer 16A* and accumulation layer share address-wire layer 2a from 16B*.Correspondingly,
Total address wire number of plies is only 1 more than total storage number of plies.In this embodiment, the address wire number of plies is 9, i.e. 1a-9a (address-wire layer 3a-
8a is not drawn into)；It is 8 to store the number of plies, i.e. 16A*-16H* (accumulation layer 16C*-16G* is not drawn into).Generally speaking, cubical array core
The rear end film number of plies of piece 30 is 11, including 9 address-wire layers and 2 interconnection line layers.
Although sectional view in Fig. 3 A- Fig. 3 B, similar to Figure 1A, the peripheral circuit in Figure 1A includes all peripheral circuits
Component, and the peripheral circuit in Fig. 3 A- Fig. 3 B is free of the necessary peripheral circuit components of some 3D-OTP, as read/write voltage occurs
Device or address/data converter.Its details will disclose in Fig. 5 A- Fig. 8 B.
Fig. 4 A- Fig. 4 B represent the peripheral circuit chip 40 (or 40*) in two kinds of separation 3D-OTP 50.Peripheral circuit chip
40 form on two dimensional surface, and it is containing only One function layer, i.e. substrate circuitry 0K '.Substrate circuitry 0K ' containing transistor 0t ' and
Its interconnection line 0t '.Because peripheral circuit chip 40 is free of any storage organization, its rear end film number of plies is its interconnection line number of plies.
In Fig. 4 A embodiment, the rear end film number of plies is 2, i.e. interconnection line 0M1 ' -0M2 '；In Fig. 4 B embodiment, rear end film
The number of plies is 4, i.e. interconnection line 0M1 ' -0M4 '.
In Fig. 3 A- Fig. 4 B embodiment, the number (2 or 4) of the rear end film layer of peripheral circuit chip 40 is than three-dimensional
Array chip 40 (10 or 11) is few a lot.One tightened up requirement is that the rear end film number of plies of three-dimensional array chip 40 is periphery
At least twice of the interconnection line number of plies of circuit chip 30.Because wafer cost is basic and the number of rear end film layer is directly proportional, periphery
The wafer cost of circuit chip 40 will be far below three-dimensional array chip 30.Therefore, the holistic cost for separating 3D-OTP will be less than collecting
Into 3D-OTP.
In addition, in figure 4b, the interconnection line layer of the interconnection line number of plies (4) of peripheral circuit chip 40 than three-dimensional array chip 30
More, the design of chip neighboring circuit is simpler, performance is more excellent, chip area is also smaller for number (2).Therefore, separate
3D-OTP overall performance and entire area is better than integrated 3D-OTP.It is noted that the interconnection line number of plies (4) of peripheral circuit chip 40
Still it is much smaller than the rear end film number of plies (10 or 11) of three-dimensional array chip 30.
Further, since the interconnection line of peripheral circuit chip 40 needs not be subjected to high temperature process steps, it can be used at a high speed
Interconnection material, such as copper (Cu) or high K medium；And the interconnection line in three-dimensional array chip 40 needs to be subjected to high-temperature technology step
Suddenly, it can only use high temperature interconnection material (such as tungsten or silica).High Speed Interconnect Lines material can improve peripheral circuit 40
To 3D-OTP overall performance.
For traditional two dimensional memory (referring to storage member to be distributed on two dimensional surface, such as traditional flash memory), it is deposited
Storage array has similar rear end structure with peripheral circuit.Although it is technically feasible that they, which are separated on different chips,
, but because the wafer cost of storage array and peripheral circuit approaches, can not be decreased after separation on chip cost,
Plus unnecessary packaging cost, the storage array of two-dimensional storage and peripheral circuit separation can be increased into cost, this and three-dimensional store
Device has very big difference.
Different from integrated 3D-OTP 20, in 3D-OTP 50 is separated, an at least peripheral circuit component is located at peripheral circuit
Chip 40, without positioned at three-dimensional array chip 30.In other words, peripheral circuit component is in three-dimensional array chip 30 and peripheral circuit
Distributed between chip 40.Fig. 5 A- Fig. 9 B disclose several allocation models.
Fig. 5 A- Fig. 5 B are the first separation 3D-OTP 50 allocation models.Three-dimensional array chip 30 contains multiple 3D-OTP
Read/write voltage generator 41 (Fig. 5 A) in array 22aa, 2ay and its decoder, and a chip.Peripheral circuit chip 40 is at least
Contain address/data converter 49 outside a chip (Fig. 5 B).Because three-dimensional array chip 40 does not contain the converter 49, three-dimensional battle array
Row chip 40 is unable to complete independently basis function storage, but has higher array efficiency.Another pattern is cubical array
Chip 40 does not contain read/write electricity containing the outer address/data converter of chip, but with larger array efficiency pressure generator.
Peripheral circuit chip 40 contains read/write voltage generator.Similarly, three-dimensional array chip 40 is unable to complete independently and stores work(substantially
Can, but there is higher array efficiency.
Fig. 6 A- Fig. 6 B are second of separation 3D-OTP 50 allocation models.It contains three-dimensional array chip 30 and periphery electricity
Road chip 40.Three-dimensional array chip 30 contains multiple 3D-OTP arrays 22aa, 2ay and its decoder (Fig. 6 A).Peripheral circuit core
Piece 40 at least contains a read/write voltage generator 41 and an address/data converter 49 (Fig. 6 B).Due to three-dimensional array chip
40 do not contain read/write voltage generator 41 and address/data converter 49, and three-dimensional array chip 40 is unable to complete independently and deposited substantially
Function is stored up, but there is higher array efficiency.
Fig. 7 A- Fig. 7 C are the third separation 3D-OTP 50 allocation models.It contains three-dimensional array chip 30 and two weeks
Side circuit chip 40,40*.Three-dimensional array chip 30 contains multiple 3D-OTP arrays 22aa, 2ay and its decoder (Fig. 7 A).The
One peripheral circuit chip 40 at least contains a read/write voltage generator 41 (Fig. 7 B).Second peripheral circuit chip 40* at least contains
One address/data converter 49 (Fig. 7 C).Similarly, because three-dimensional array chip 40 does not contain the He of read/write voltage generator 41
Address/data converter 49, three-dimensional array chip 40 is unable to complete independently basis function storage, but is imitated with higher array
Rate.Meanwhile first peripheral circuit chip 40 can optimize according to analog circuit, and the second peripheral circuit chip 40* can be according to number
Circuit optimization.
Fig. 8 A- Fig. 8 B are the 4th kind of separation 3D-OTP allocation models.Its embodiment similar to Fig. 6 A- Fig. 6 B.Uniquely
Difference is that three-dimensional array chip 30 also contains a Serial-Parallel Converter (SerDes) (Fig. 8 A), and it is by inside chip 30
Parallel digital signal (such as address/data/instruction) is converted into the serial digital signals outside chip 30；Meanwhile peripheral circuit core
Piece 40 also contains a Serial-Parallel Converter (Fig. 8 B), and it is by parallel digital signal (such as address/data/refer to inside chip 40
Order etc.) it is converted into the serial digital signals outside chip 40.Increased number of leads is needed to reduce by this conversion, during encapsulation
A lot, this can reduce packaging cost.
Fig. 9 A- Fig. 9 B are the circuit block diagrams of two kinds of peripheral circuit chips 40 for supporting more three-dimensional array chips.Fig. 9 A week
Side circuit chip 40 contains multiple address/data converter 49a, 49b ... 49w (or read/write voltage generator).Each address/
Data converter (such as 49a) is that corresponding three-dimensional array chip (such as 30a) changes address/data.Fig. 9 B peripheral circuit chip
40 also contain multiple read/write voltage generator 41a, 41b ... 41w.Each read/write voltage generator (such as 41a) is corresponding three
Tie up array chip (such as 30a) and read/write voltage is provided.
Figure 10 A- Figure 10 C are the sectional views of three kinds of separation 3D-OTP encapsulation (or modules) 60.Point in Figure 10 A- Figure 10 B
It is a kind of multi-chip package (MCP) from 3D-OTP 60.Wherein, the 3D-OTP multi-chip packages 60 in Figure 10 A are independent containing two
Chip：One three-dimensional array chip 30 and a peripheral circuit chip 40.Wherein, chip 30 is stacked on the top of chip 40, and is located at
In same encapsulating shell 61.Lead (bond wire) 65 is that chip 30 and 40 provides electrical connection.Except lead, weldering can also be used
Ball (solder bump) etc..In order to guarantee data security, chip 30 and 40 is preferably enclosed in a moulding compound (molding
Compound) in 57.
3D-OTP multi-chip packages 60 in Figure 10 B contain three single chips：Two three-dimensional array chips 30a, 30b
With peripheral circuit chip 40.In the present embodiment, chip 30a, 30b is stacked on chip 40.In other embodiments, chip
40 can be stacked on chip 30a, 30b, or chip 40 is stacked Face to face with chip 30a, 30b, or the He of chip 40
Chip 30a, 30b are placed side by side.
Separation 3D-OTP in Figure 10 C is a 3D-OTP multi-chip modules (MCM) 60, and it contains a framework 76.The frame
Frame 76 contains two individually encapsulation：Cubical array encapsulation 72 and peripheral circuit encapsulation 74.Wherein, cubical array encapsulation 72 contains
Two three-dimensional array chips 30a, 30b, and peripheral circuit encapsulation 64 contains peripheral circuit chip 40.Framework 76 is also cubical array
Encapsulation 72 and peripheral circuit encapsulation 74 provide electrical connection (not shown).
Figure 11 A- Figure 11 C are the circuit diagrams of three kinds of read/write voltage generators 41.Read/write voltage generator 41 is preferred
DC-DC converter (DC-DC converter).DC-DC converter includes booster and reducing transformer.Booster
Output voltage is higher than input voltage, and the input voltage of reducing transformer is lower than input voltage.The example of booster includes charge pump
(charge pump, Figure 11 A) and Boost (Boost converter, Figure 11 B) etc..The example of reducing transformer includes low
Dropout regulator (low dropout, Figure 11 C) and Buck converters (Buck converter) etc..
Read/write voltage generator 41 in Figure 11 A includes a charge pump 71, its output voltage VoutMore than input voltage Vin。
It is, in general, that charge pump 71 also contains one or more electric capacity.Read/write voltage generator 41 in Figure 11 B includes a high frequency
Boost 73, its output voltage VoutMore than input voltage Vin.Boost 73 also contains inductance.The inductance is best
It is a thin inductance, to meet the requirement of storage card or solid state hard disc to thickness.Read/write voltage generator 41 in Figure 11 C includes
One low dropout voltage regulator 75, its output voltage VoutLess than input voltage Vin.It is, in general, that low dropout voltage regulator 75 also contains one
Individual or multiple electric capacity.
Figure 12 A- Figure 12 B represent two components of address/data converter 49 respectively：Address translator 43 and data turn
Parallel operation 45.Figure 12 A represent a kind of address translator 43.Logical address 57A from main frame is converted into three-dimensional array chip by it
30 physical address 58A.Address translator 43 contains a memory 94 of processor 92 and one.Memory 94 stores an address and reflected
The trouble block table 84 of firing table 82 and one.These state tables 82,84 are stored in read-only storage (ROM) when flat.Added when in use
It is downloaded in random access memory (RAM).Here, read-only storage can a kind of nonvolatile memory (NVM), such as flash memory
Reservoir.For an address/data converter 49 for supporting more three-dimensional array chips (30a, 30b ... 30w in such as Fig. 2 D)
Say, memory 94 is all three-dimensional array chip 30a, 30b ... 30w storage states tables 82,84,86, and it is by all cubical arrays
Chip 30a, 30b ... 30w share.
In the various state tables 82,84 of memory 94, address mapping table 82 is stored between logical address and physical address
Mapping；Trouble block table 84 stores the address of faulty memory block in three-dimensional memory array.Here, " memory block " refers to store
The allocation unit of device, its size can be from a storage members to all storages member in a three-dimensional memory array.
In read procedure, once processor 92 receives the logical address 57A for the memory block for needing to read, it reflects from address
Corresponding physical address 58A is obtained in firing table 82.During writing, once processor 92 receive need the memory block that writes it
Logical address 57A, it selected from address mapping table 82 and trouble block table 84 a vacant, fault-free and it is less use deposit
Block is stored up to write data.The address of the selected memory block is physical address.
Figure 12 B represent a kind of data converter 45.Logical data 57D from main frame is converted into three-dimensional array chip by it
30 physical data 58D, or the physical data 58D of three-dimensional array chip 30 is converted into output to the logical data of main frame
57D.Data converter 45 contains error checking correction (ECC) encoder 96 and an ECC decoder 98.ECC encoder 96 will
The logical data 57D of input is converted into storing the physical data 58D of three-dimensional memory array.ECC decoder 98 will be from three-dimensional
The physical data 58D read in storage array is converted into logical data 57D to be output.In this process, physical data 58D
In error bit be examined and correction.It is adapted to 3D-OTP ECC encryption algorithms to include Reed-Solomon codes, Golay codes, BCH
Code, multidimensional parity code and Hamming code etc..
It should be appreciated that on the premise of not away from the spirit and scope of the present invention, can be to the form and details of the present invention
It is modified, this simultaneously applies the spirit of the present invention without prejudice to them.Therefore, except the spirit according to appended claims,
The present invention should not be restricted by any restrictions.
Claims (10)
- A kind of 1. electrical programming memory of the three-dimensional of separation（3D-OTP）(50), it is characterised in that including：One contains the three-dimensional array chip (30) of an at least 3D-OTP arrays (36), and the 3D-OTP arrays (36) are containing multiple mutual The 3D-OTP storage members of stacking；One address/data converter chip (40), the address/data converter chip (40) contain the 3D-OPT arrays (36) An at least address/data converter, the three-dimensional array chip (30) are free of the address/data converter；The means that the three-dimensional array chip (30) and the address/data converter chip (40) are coupled；The rear end film number of plies of the three-dimensional array chip (30) is the interconnection line layer of the address/data converter chip (40) Several at least twice；The three-dimensional array chip (30) is two different cores with the address/data converter chip (40) Piece.
- A kind of 2. electrical programming memory of the three-dimensional of separation（3D-OTP）(50), it is characterised in that including：One contains the three-dimensional array chip (30) of an at least 3D-OTP arrays (36), and the 3D-OTP arrays (36) are containing multiple mutual The 3D-OTP storage members of stacking；One address/data converter chip (40), the address/data converter chip (40) contain the 3D-OPT arrays (36) An at least address/data converter, the three-dimensional array chip (30) are free of the address/data converter；The means that the three-dimensional array chip (30) and the address/data converter chip (40) are coupled；The rear end film number of plies of the three-dimensional array chip (30) is more than the interconnection line of the address/data converter chip (40) The number of plies；The interconnection line number of plies of the address/data converter chip (40) is more than the interconnection line of the three-dimensional array chip (30) The number of plies；The three-dimensional array chip (30) is two different chips with the address/data converter chip (40).
- A kind of 3. electrical programming memory of the three-dimensional of separation（3D-OTP）(50), it is characterised in that including：One contains the three-dimensional array chip (30) of an at least 3D-OTP arrays (36), and the 3D-OTP arrays (36) are containing multiple mutual The 3D-OTP storage members of stacking；One address/data converter chip (40), the address/data converter chip (40) contain the 3D-OPT arrays (36) An at least address/data converter, the three-dimensional array chip (30) are free of the address/data converter；The means that the three-dimensional array chip (30) and the address/data converter chip (40) are coupled；The interconnection material of the three-dimensional array chip (30) is different from the interconnection line of the address/data converter chip (40) Material；The three-dimensional array chip (30) is two different chips with the address/data converter chip (40).
- 4. according to the memory described in claim 1,2 or 3, it is further characterized in that：The 3D-OTP storages member is anti-molten containing one Cortina (1**).
- 5. according to the memory described in claim 1,2 or 3, it is further characterized in that：The separation 3D-OTP is storage card, solid-state At least one of hard disk, multi-chip package and multi-chip module.
- 6. according to the memory described in claim 1,2 or 3, it is further characterized in that：Contain another three-dimensional array chip, the ground Location/data converter chip contains another address/data converter of another three-dimensional array chip.
- 7. according to the memory described in claim 1,2 or 3, it is further characterized in that：The address/data converter chip (40) Contain a read/write voltage generator.
- 8. according to the memory described in claim 1,2 or 3, it is further characterized in that：The address/data converter chip (40) Contain an address/data converter.
- 9. memory according to claim 3, is further characterized in that：The address/data converter chip (40) is contained High Speed Interconnect Lines material.
- 10. memory according to claim 3, is further characterized in that：The three-dimensional array chip (30) is mutual containing high temperature Link material.
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| CN201610640347.1A CN107689377A (en) | 2016-08-06 | 2016-08-06 | Electrical programming memory of three-dimensional containing separation address/data converter |
| US15/333,116 US9666300B2 (en) | 2011-09-01 | 2016-10-24 | Three-dimensional one-time-programmable memory comprising off-die address/data-translator |
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| CN201610640347.1A CN107689377A (en) | 2016-08-06 | 2016-08-06 | Electrical programming memory of three-dimensional containing separation address/data converter |
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