CN111581150A - Method for reconstructing GPIO (general purpose input/output) function in MCU (microprogrammed control unit) - Google Patents
Method for reconstructing GPIO (general purpose input/output) function in MCU (microprogrammed control unit) Download PDFInfo
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- CN111581150A CN111581150A CN202010341120.3A CN202010341120A CN111581150A CN 111581150 A CN111581150 A CN 111581150A CN 202010341120 A CN202010341120 A CN 202010341120A CN 111581150 A CN111581150 A CN 111581150A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The invention discloses a method for reconstructing GPIO function in MCU, comprising the following steps of S1: packaging and defining the MCU; step S2: judging whether the MCU defined by encapsulation has a vacant port; step S3: judging whether the vacant ports of the MCU defined by encapsulation need multifunctional multiplexing or not; step S4: and performing multifunctional multiplexing packaging on the MCU. The invention discloses a method for reconstructing GPIO functions in an MCU, which carries out reconfigurable design on all ports during design and finally can package the ports, so that when a user can use a port MCU with the reconfigurable design, all ports and internal functions of the MCU can be used. For example, pin1 is composed of 3 chip pads and packaged together, pin1 can select a single pad output driving capability of pad1, and can select 2 pad output driving capabilities of pad1+ pad2, and can select 3 pad output driving capabilities of pad1+ pad2+ pad3, so that the user can obtain the maximum resource utilization.
Description
Technical Field
The invention belongs to the technical field of port reconstruction of single-chip microcomputers, and particularly relates to a General-purpose input/output (GPIO) function reconstruction method in an MCU (microprogrammed control Unit).
Background
The cost of the current MCU is very high, and the MCU is basically a strategy of selling more than one object in order to meet different market demands and marketing means. For example, the same MCU die may be packaged into different packaging forms, such as LQFP64, LQFP48, LQFP32, TSSOP20, and the like.
However, under different packaging forms, all ports are not packaged, which means that a user can only use the packaged ports but cannot use the ports that are not packaged, which greatly reduces the resources available to the user and even prevents some important functions from being used.
The publication number is: CN101419485B, the subject name of which is an invention patent of a wearable computer mainboard with changeable functions, the technical proposal discloses that' the changeable function chip is connected to an internal memory of X86 system-level SOC, VGA, LVDS, HDMI, DVI, LAN, USB, IDE, CF, SATA, SPI, LPC, PCI, GPIO, Smbus, I2C, MMC, SD, COM or LPT bus; the variable function chip externally realizes USB, LAN, VGA, LVDS, HDMI, DVI, GPIO, Smbus, I2C, IDE, CF, SATA, MMC, SD, COM, LPT or headset interfaces; the Flash/EEPROM is used as an external configuration chip of the variable function chip and is used for storing the programming file in the variable function chip; the variable function chip is provided with a required power supply by the system voltage regulator; the variable function chip realizes the online upgrade and expansion of the wearable computer mainboard on the hardware level of the system comprehensive control function, the user-defined logic function, the coprocessor and bus function and the interface function; the variable function chip internally comprises a configuration module group, an interface module group, a storage module group, an on-chip CPU, an on-chip bus controller, a display core module, a system comprehensive control module and a self-defined logic function module; the on-line upgrade and expansion of the wearable computer mainboard on the hardware levels of a system comprehensive control function, a self-defined logic function, a coprocessor and bus function and an interface function are realized through the cooperative coordination of the modules; the attached module group comprises a voltage adjusting module, a clock module, a JTAG bus module and a JTAG switching module; wherein the voltage regulation module: the pulse sequence is used for generating a pulse sequence with a certain duty ratio, turning on or off an MOS tube or a triode outside a chip, providing PWM voltage for the variable function chip or other parts of the system, controlling the turning on or off of the external MOS tube or the triode, carrying out power supply enabling or power-on time sequence management and providing various voltages required by the variable function chip; the clock module is used for: various clocks required by the variable function chip are provided or clock signals are provided for an external system through a phase-locked loop PLL or frequency division and frequency multiplication circuit structure in the chip; the JTAG bus module: providing support for programming and downloading a variable function chip through a bus circuit structure which accords with a JTAG protocol in a chip; the JTAG switching module: through the JTAG protocol and the conversion circuit structure of the USB, COM, LPT and LPC/SPI protocols, the support that the JTAG bus in the variable function chip is connected to the corresponding interface or bus is provided; the system comprehensive control module: the system is used for detecting and controlling the current states of various parts of the system and sending related information to the X86 system SOC to provide upper-layer application support; the system comprehensive control module consists of an ITP/DXP test module, a BIOS information feedback module, a welding spot test module, a power supply switching and charging management module, an accelerometer measurement module, a heat sensor measurement module, a decision support module, a keyboard scanning and coding module, a system dormancy control module, a voltage regulator enabling and state monitoring module, a volume control module, an LCD brightness control module, an infinite device switch module, a shift register, a USB interface module, an SPI controller and a register group; the ITP/DXP testing module is connected to DXP interfaces of a CPU and a north-south bridge integrated chip, a BIOS information feedback module is connected with the BIOS chip through an LPC or SPI bus to translate the current feedback state of the BIOS, a power switching and charging management module is connected with a battery and an adapter, an accelerometer measuring module is connected with an accelerometer, a heat sensor measuring module is connected with a heat sensor, a keyboard scanning and coding module is connected with a system keyboard matrix, a system dormancy control module is connected with a power management part of the north-south bridge integrated chip, a voltage regulator enables the state monitoring module to be connected with a system power supply module, a volume control module is connected with a system loudspeaker, an LCD brightness control module is connected with an LCD of an LVDS interface, and a wireless device switch module is connected with a wireless communication module; the system-level SOC includes: an X86 processor, an X86 chipset, and a display core, wherein the X86 chipset includes north and south bridge controllers that may be integrated in a north-south bridge integrated chip.
Taking the above invention patent as an example, the technical problem solved is: the method is different from the technical problems solved by the invention in view of the variable application requirements of the wearable computer and the defects of the prior art that the functions are single and the performance upgrading and function expanding are inconvenient. Therefore, the above problems are further improved.
Disclosure of Invention
The invention mainly aims to provide a method for reconstructing GPIO functions in an MCU (microprogrammed control Unit), which can perform reconfigurable design on all ports during design and finally package the ports, so that a user can use all the ports and internal functions of the MCU when using the port MCU with the reconfigurable design.
The invention also aims to provide a method for reconstructing the GPIO function in the MCU, under the condition that the MCU port cannot be packaged out under certain small packages to cause the function waste of the MCU port, a user can use each port function of the MCU as much as possible under the small package form.
The invention also aims to provide a method for reconstructing the GPIO function in the MCU, which can package all the pins during packaging, and then configure the pins into different functional ports by using software, so that a user can use all the internal resources of the MCU to the maximum extent, and the competitiveness of the MCU is increased. For example, pin1 is composed of 3 chip pads and packaged together, pin1 can select a single pad output driving capability of pad1, and can select 2 pad output driving capabilities of pad1+ pad2, and can select 3 pad output driving capabilities of pad1+ pad2+ pad3, so that the user can obtain the maximum resource utilization.
In order to achieve the above purpose, the present invention provides a method for reconstructing GPIO functions in an MCU, which is used to completely encapsulate ports in the MCU, and comprises the following steps:
step S1: packaging definition is carried out on the MCU (firstly, whether the ports are packaged by the packaging definition (namely common packaging) which is just started by the MCU is checked);
step S2: judging whether the MCU defined by the package has a spare port (if the package definition of the MCU just started encapsulates all the ports, the MCU can directly encapsulate all the ports according to the just started package definition, and all the ports and internal functions of the MCU can be used);
step S3: judging whether the vacant ports of the MCU defined by the encapsulation need multifunctional multiplexing (if the MCU does not encapsulate all the ports at the beginning, namely, the vacant ports exist, but the user does not need all the ports or internal functions when using, the MCU encapsulation method directly defines the MCU encapsulation at the beginning, does not need multifunctional multiplexing encapsulation, and can flexibly select according to the requirements of the user);
step S4: and performing multifunctional multiplexing packaging on the MCU.
As a further preferable embodiment of the above technical means, step S2 is specifically implemented as the following steps:
step S2.1: if the MCU is judged to have a spare port, executing the step S3;
step S2.2: and if the MCU is judged to have no spare port, the MCU is subjected to common packaging.
As a further preferable embodiment of the above technical means, step S3 is specifically implemented as the following steps:
step S3.1: if the spare port of the MCU needs multifunctional multiplexing, executing step S4;
step S3.2: and if the spare port of the MCU does not need multifunctional multiplexing, performing common packaging on the MCU.
As a further preferable embodiment of the above technical means, step S4 is specifically implemented as the following steps:
step S4.1: configuring at least two ports of the MCU into a function enabling port during packaging and routing (during MCU packaging);
step S4.2: the remaining internal functions (N-1) in the MCU are configured to either emulate ports or high impedance input states.
As a further preferable technical solution of the above technical solution, in step S4, the Y port, the IE port, and the CS port of the MCU are electrically connected to the first unit through the level shifting unit, respectively;
the PU port of the MCU is electrically connected with the switch through the level conversion unit;
the DR end, the A end and the OE end of the MCU are electrically connected with the second unit through the level conversion unit respectively;
the PD end of the MCU is electrically connected with the switch through the level conversion unit.
Drawings
Fig. 1 is a flow diagram of a method for reconstructing GPIO functions in an MCU according to the present invention.
Fig. 2 is a schematic diagram of port reconfiguration of the method for reconfiguring GPIO functions in an MCU according to the present invention.
Fig. 3 is a schematic diagram of a package after port reconfiguration of LQFP80 of the method for reconfiguring GPIO functions in an MCU according to the present invention.
Fig. 4 is a schematic diagram of a package after port reconfiguration of LQFP32 of the method for reconfiguring GPIO functions in an MCU according to the present invention.
Fig. 5 is a schematic diagram of a conventional MCU port package.
FIG. 6 is a schematic diagram of MCU port encapsulation of the method for reconstructing GPIO function in MCU of the present invention.
Detailed Description
The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.
Referring to fig. 1 of the drawings, fig. 1 is a schematic flow diagram of a method for reconfiguring a GPIO function in an MCU of the present invention, fig. 2 is a schematic port reconfiguration diagram of the method for reconfiguring a GPIO function in an MCU of the present invention, fig. 3 is a schematic packaging diagram of a reconstructed port of LQFP80 of the method for reconfiguring a GPIO function in an MCU of the present invention, fig. 4 is a schematic packaging diagram of a reconstructed port of LQFP32 of the method for reconfiguring a GPIO function in an MCU of the present invention, fig. 5 is a schematic packaging diagram of an existing MCU port, and fig. 6 is a schematic packaging diagram of an MCU port of the method for reconfiguring a GPIO function in an MCU of.
In the preferred embodiment of the present invention, those skilled in the art should note that MCU, GPIO, etc. referred to in the present invention can be regarded as the prior art.
Preferred embodiments.
The invention discloses a method for reconstructing GPIO (general purpose input/output) functions in an MCU (microprogrammed control Unit), which is used for completely packaging ports in the MCU and comprises the following steps:
step S1: packaging definition is carried out on the MCU (firstly, whether the ports are packaged by the packaging definition (namely common packaging) which is just started by the MCU is checked);
step S2: judging whether the MCU defined by the package has a spare port (if the package definition of the MCU just started encapsulates all the ports, the MCU can directly encapsulate all the ports according to the just started package definition, and all the ports and internal functions of the MCU can be used);
step S3: judging whether the vacant ports of the MCU defined by the encapsulation need multifunctional multiplexing (if the MCU does not encapsulate all the ports at the beginning, namely, the vacant ports exist, but the user does not need all the ports or internal functions when using, the MCU encapsulation method directly defines the MCU encapsulation at the beginning, does not need multifunctional multiplexing encapsulation, and can flexibly select according to the requirements of the user);
step S4: and performing multifunctional multiplexing packaging on the MCU.
Specifically, step S2 is implemented as the following steps:
step S2.1: if the MCU is judged to have a spare port, executing the step S3;
step S2.2: and if the MCU is judged to have no spare port, the MCU is subjected to common packaging.
More specifically, step S3 is specifically implemented as the following steps:
step S3.1: if the spare port of the MCU needs multifunctional multiplexing, executing step S4;
step S3.2: and if the spare port of the MCU does not need multifunctional multiplexing, performing common packaging on the MCU.
Further, step S4 is implemented as the following steps (taking PA00 as an example, the reconfigurable ports of the present invention are at least 2):
step S4.1: configuring at least two ports of the MCU into a function enabling port during packaging and routing (during MCU packaging);
step S4.2: the remaining internal functions (N-1) in the MCU are configured to either emulate ports or high impedance input states.
Further, in step S4, the Y port, the IE port, and the CS port of the MCU are electrically connected to the first unit D1 through Level shifters (Level shifters), respectively;
the PU port of the MCU is electrically connected with the switch S1 through the level conversion unit;
the DR end, the A end and the OE end of the MCU are respectively electrically connected with the second unit D2 through the level conversion unit;
the PD terminal of the MCU is electrically connected to the switch S2 through the level shifting unit.
Preferably, as shown in fig. 3 and 4, the same MCU die (wafer die) is packaged into a package of LQFP80 and LQFP32, when the MCU packaged by the present invention is used, all pins can be packaged when the LQFP32 is packaged, and then the MCU packaged by the present invention is configured into different functional ports by software, so that a user can use all internal resources of the MCU to the maximum extent, and the competitiveness of the MCU can be increased.
Preferably, as shown in fig. 5, the description of the black circles in the photo of the current chip in the industry is that the description of the packaged pin is used without the black circles and is not packaged for use, and the packaged pin is actually used by the user but is wasted.
Preferably, as shown in fig. 6, the package schematic diagram after the present patent is used, the black circles are illustrated as being used when the package is out, and multiple signal lines are sealed together, so that a user really uses all pins without waste.
It should be noted that the technical features such as MCU and GPIO related to the present patent application should be regarded as the prior art, and the specific structure, the operation principle, the control mode and the spatial arrangement mode of the technical features may be selected conventionally in the field, and should not be regarded as the invention point of the present patent, and the present patent is not further specifically described in detail.
It will be apparent to those skilled in the art that modifications and equivalents may be made in the embodiments and/or portions thereof without departing from the spirit and scope of the present invention.
Claims (5)
1. A method for reconstructing GPIO function in MCU is used for packaging all ports in MCU, and is characterized by comprising the following steps:
step S1: packaging and defining the MCU;
step S2: judging whether the MCU defined by encapsulation has a vacant port;
step S3: judging whether the vacant ports of the MCU defined by encapsulation need multifunctional multiplexing or not;
step S4: and performing multifunctional multiplexing packaging on the MCU.
2. The method for reconstructing the GPIO function in the MCU according to claim 1, wherein the step S2 is implemented as the following steps:
step S2.1: if the MCU is judged to have a spare port, executing the step S3;
step S2.2: and if the MCU is judged to have no spare port, the MCU is subjected to common packaging.
3. The method for reconstructing the GPIO function in the MCU according to claim 2, wherein the step S3 is implemented as the following steps:
step S3.1: if the spare port of the MCU needs multifunctional multiplexing, executing step S4;
step S3.2: and if the spare port of the MCU does not need multifunctional multiplexing, performing common packaging on the MCU.
4. The method for reconstructing the GPIO function in the MCU according to any one of claims 1 or 3, wherein the step S4 is implemented as the following steps:
step S4.1: configuring at least two ports of the MCU into a function enabling port when packaging and routing;
step S4.2: the remaining internal functions in the MCU are configured to either emulate ports or high impedance input states.
5. The method of claim 4, wherein in step S4, the Y port, the IE port and the CS port of the MCU are electrically connected to the first unit through a level shifting unit, respectively;
the PU port of the MCU is electrically connected with the switch through the level conversion unit;
the DR end, the A end and the OE end of the MCU are electrically connected with the second unit through the level conversion unit respectively;
the PD end of the MCU is electrically connected with the switch through the level conversion unit.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596765A (en) * | 1994-10-19 | 1997-01-21 | Advanced Micro Devices, Inc. | Integrated processor including a device for multiplexing external pin signals |
| CN101419485A (en) * | 2008-11-24 | 2009-04-29 | 电子科技大学 | Function-variable portable computer mainboard |
| CN103576576A (en) * | 2013-10-16 | 2014-02-12 | 宏景电子(芜湖)有限公司 | Reuse method for automobile body controller MCU port |
| CN103678226A (en) * | 2012-09-24 | 2014-03-26 | 炬力集成电路设计有限公司 | General purpose input/output (GPIO) port reuse circuit and method of chip |
| US20150187410A1 (en) * | 2013-12-28 | 2015-07-02 | Christopher J Nelson | Testing a wide functional interface of a device integrated on an sip without dedicated test pins |
| CN107807574A (en) * | 2017-11-02 | 2018-03-16 | 中电科技集团重庆声光电有限公司 | Multifunctional interface circuit based on integrative packaging |
| CN108445293A (en) * | 2018-05-29 | 2018-08-24 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip port impedance test device and measurement method |
| US10262973B1 (en) * | 2015-12-03 | 2019-04-16 | Marvell International Ltd. | Modular chip with redundant interfaces |
-
2020
- 2020-04-27 CN CN202010341120.3A patent/CN111581150B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596765A (en) * | 1994-10-19 | 1997-01-21 | Advanced Micro Devices, Inc. | Integrated processor including a device for multiplexing external pin signals |
| CN101419485A (en) * | 2008-11-24 | 2009-04-29 | 电子科技大学 | Function-variable portable computer mainboard |
| CN103678226A (en) * | 2012-09-24 | 2014-03-26 | 炬力集成电路设计有限公司 | General purpose input/output (GPIO) port reuse circuit and method of chip |
| CN103576576A (en) * | 2013-10-16 | 2014-02-12 | 宏景电子(芜湖)有限公司 | Reuse method for automobile body controller MCU port |
| US20150187410A1 (en) * | 2013-12-28 | 2015-07-02 | Christopher J Nelson | Testing a wide functional interface of a device integrated on an sip without dedicated test pins |
| US10262973B1 (en) * | 2015-12-03 | 2019-04-16 | Marvell International Ltd. | Modular chip with redundant interfaces |
| CN107807574A (en) * | 2017-11-02 | 2018-03-16 | 中电科技集团重庆声光电有限公司 | Multifunctional interface circuit based on integrative packaging |
| CN108445293A (en) * | 2018-05-29 | 2018-08-24 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip port impedance test device and measurement method |
Non-Patent Citations (2)
| Title |
|---|
| 徐明亮主编: "《嵌入式系统基础项目化教程》", 31 May 2017 * |
| 赵忠伟: "基于HDTV网络MEPG-2复用器的设计和实现", 《电视技术》 * |
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