CN111564554A - Limited phase change unit and preparation method thereof - Google Patents

Limited phase change unit and preparation method thereof Download PDF

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Publication number
CN111564554A
CN111564554A CN202010426144.9A CN202010426144A CN111564554A CN 111564554 A CN111564554 A CN 111564554A CN 202010426144 A CN202010426144 A CN 202010426144A CN 111564554 A CN111564554 A CN 111564554A
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phase change
dielectric layer
change material
electrode
groove
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CN111564554B (en
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钟旻
陈寿面
李铭
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Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
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Shanghai IC R&D Center Co Ltd
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Priority to PCT/CN2020/138318 priority patent/WO2021232781A1/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • H10N70/231Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/841Electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/841Electrodes
    • H10N70/8413Electrodes adapted for resistive heating

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  • Semiconductor Memories (AREA)

Abstract

The invention discloses a limited phase change unit which comprises a bottom electrode, a phase change material layer and a top electrode which are connected from bottom to top, wherein the phase change material layer is of at least one side wall structure formed by adopting a method of depositing a phase change material film on a side wall, so that the contact area of the bottom electrode and the phase change material can be greatly reduced, the power consumption of the phase change unit is reduced, the damage of an etching process to the phase change material is avoided, the reliability of a device is improved, the full phase change operation can be realized, and the consistency of the resistance value of the whole column of the phase change unit is favorably improved.

Description

Limited phase change unit and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing processes, in particular to a limiting type phase change unit and a preparation method thereof.
Background
With the emergence of a series of novel information technologies such as big data, internet of things, cloud computing and artificial intelligence, the requirements of high read-write speed, low power consumption, high storage density, long service life, high reliability and the like are provided for the memory.
At present, the memory mode of the memory is mainly Dynamic Random Access Memory (DRAM) and Flash memory (Flash). The NAND Flash has high integration level and low cost, but has slow speed and short service life. Although DRAM is fast and has a long lifetime, it loses data after power is lost, and it is costly.
Therefore, the development of a new storage technology has become a focus of research in recent years. The novel storage technology has the advantages of both DRAM and NAND Flash, namely, the read-write speed is comparable to that of DRAM, the novel storage technology is similar to NAND Flash in cost and nonvolatile aspects, and the phase change memory is one of the novel storage technologies. In recent years, the phase change memory unit has a wide prospect in the application of an artificial intelligence and storage and computation integrated chip.
Existing phase change memory cells are generally divided into two categories: one is a mushroom-type phase change cell, as shown in fig. 1, the phase change material has a large volume, and only the phase change material region (the semi-circular dotted line region in the figure) in contact with the bottom electrode undergoes phase change, so that the power consumption of the device is high, and the size of the device is large. The other type is a limited phase change unit, as shown in fig. 2, which is used in a 3D phase change memory, and a small-sized phase change material layer is formed by photolithography and etching processes of a phase change material, and the phase change material undergoes complete phase change. The device has small size and low power consumption, but has higher requirements on photoetching and etching processes, and the etching process can damage the side wall of the small-size phase-change material, thereby influencing the performance and reliability of the device.
Therefore, a novel phase change unit structure needs to be invented, and various requirements of high density, low device power consumption and simple preparation process can be met simultaneously.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a limited phase change unit and a preparation method thereof.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a limited phase change unit comprises a bottom electrode, a phase change material layer and a top electrode which are connected from bottom to top; wherein the phase change material layer is at least one sidewall structure formed by sidewall deposition.
Further, the bottom electrode comprises a heating electrode.
Further, a heating electrode is arranged between the bottom electrode and the phase change material layer.
Further, the heating electrode is at least one sidewall structure formed by sidewall deposition.
Further, the bottom electrode is connected with a substrate.
Furthermore, a dielectric layer is arranged on the substrate, and the limiting type phase change unit is embedded in the dielectric layer.
A preparation method of a restricted phase change unit comprises the following steps:
s01: providing a substrate, depositing a first dielectric layer on the substrate, and forming a bottom electrode in the substrate and the first dielectric layer;
s02: depositing a second dielectric layer on the first dielectric layer, and forming a through first groove structure in the second dielectric layer corresponding to the bottom electrode;
s03: depositing a phase change material on the surface of the side wall of the first groove, and connecting the lower end of the phase change material with the bottom electrode;
s04: depositing a third dielectric layer on the second dielectric layer, filling the first groove with the third dielectric layer, and flattening to expose the upper end of the phase change material on the side wall of the first groove to form a phase change material layer with a side wall structure;
s05: and correspondingly forming a top electrode on the third dielectric layer.
Further, when there are a plurality of bottom electrodes, the method further includes: in step S03, the phase change material between the bottom electrodes is disconnected; in step S05, a plurality of top electrodes corresponding to the bottom electrodes are formed on the third dielectric layer.
Further, the bottom electrode comprises a heating electrode.
A preparation method of a restricted phase change unit comprises the following steps:
s11: providing a substrate, depositing a first dielectric layer on the substrate, and forming a bottom electrode in the substrate and the first dielectric layer;
s12: depositing a second dielectric layer on the first dielectric layer, and respectively forming a through second groove structure in the second dielectric layer corresponding to the bottom electrode;
s13: depositing a heating electrode material on the surface of the side wall of the second groove, and connecting the lower end of the heating electrode material with the bottom electrode;
s14: depositing a third dielectric layer on the second dielectric layer, filling the second groove with the third dielectric layer, and flattening to expose the upper end of the heating electrode material on the side wall of the second groove, so as to form an annular heating electrode with a side wall structure;
s15: depositing a fourth dielectric layer on the third dielectric layer, and forming a through third groove structure in the fourth dielectric layer corresponding to the bottom electrode;
s16: depositing a phase change material on the surface of the side wall of the third groove, and connecting the lower end of the phase change material with the heating electrode;
s17: depositing a fifth dielectric layer on the fourth dielectric layer, filling the third groove with the fifth dielectric layer, and flattening to expose the upper end of the phase change material on the side wall of the third groove to form a phase change material layer with a side wall structure;
s18: and correspondingly forming a top electrode on the fifth dielectric layer.
Further, when the bottom electrode and the heating electrode are a plurality of corresponding ones, the method further includes: in step S17, the phase change material between the bottom electrodes is disconnected; in step S18, a plurality of top electrodes corresponding to the bottom electrodes are formed on the fifth dielectric layer.
Further, in step S16, at least two connection points exist between the lower end of the phase change material and the upper end of the heating electrode.
According to the technical scheme, the limited phase change unit is prepared by adopting the method of depositing the phase change material film on the side wall, so that the contact area between the bottom electrode and the phase change material can be greatly reduced, and the power consumption of the phase change unit is reduced. Meanwhile, the side wall type phase change layer avoids damage to the phase change material caused by the traditional etching process, and the reliability of the device is improved. In addition, the thickness of the side wall type phase change material can be very thin (less than 10nm), full phase change operation can be realized, and the consistency of the resistance value of the phase change unit array is favorably improved. The preparation method can realize the reduction of the unit size of the phase change unit, realize high-density storage, has simpler manufacturing process and can be compatible with the existing standard CMOS process.
Drawings
Fig. 1-2 are schematic diagrams of a conventional phase change unit structure.
FIG. 3 is a schematic diagram of a confined phase change cell according to a preferred embodiment of the invention.
Fig. 4-9 are schematic diagrams of process steps for fabricating a confined phase change cell of fig. 3.
FIG. 10 is a schematic diagram of a confined phase change cell according to a second embodiment of the present invention.
FIGS. 11-17 are schematic diagrams of process steps for fabricating a confined phase change cell of FIG. 10.
Detailed Description
The core idea of the invention is to provide a limited phase change unit structure and a preparation method thereof, wherein the limited phase change unit comprises a bottom electrode, a phase change material layer and a top electrode which are connected from bottom to top, the phase change material layer is at least one side wall structure formed by adopting a method of depositing a phase change material film on a side wall, the contact area of the bottom electrode and the phase change material can be greatly reduced, the power consumption of the phase change unit is reduced, the damage of an etching process to the phase change material is avoided, the reliability of a device is improved, the full phase change operation can be realized, and the consistency of the resistance value of the whole column of the phase change unit is favorably improved.
The preparation method can realize the reduction of the unit size of the phase change unit, realize high-density storage, has simpler manufacturing process and can be compatible with the existing standard CMOS process.
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the present invention, please refer to fig. 3, in which fig. 3 is a schematic structural diagram of a confined phase change cell according to a preferred embodiment of the present invention. As shown in fig. 3 (a top view, a cross-sectional view along the direction of the double-dashed line in the figure, the same applies below), a confined phase change cell of the present invention can be built on a substrate 101. One to many dielectric layers, such as a first dielectric layer, a second dielectric layer, and a third dielectric layer 102, 104, 107, may be disposed on the substrate 101. The confinement type phase change unit can be embedded in the dielectric layer.
The substrate 101 may include a semiconductor material such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a silicon germanium substrate, or a fully depleted silicon-on-insulator (FDSOI) substrate. Substrate 101 may also be an integrated circuit, including an integrated circuit with gate transistors such as transistors, diodes, etc.
Please refer to fig. 3. The bottom electrodes 103 may be disposed in the substrate 101 and the first dielectric layer 102 simultaneously, and one or more of them may be disposed. For example, the lower portions of the four bottom electrodes 103 shown in the figure may be located in the substrate 101, and the upper portions are exposed from the surface of the substrate 101 and located in the first dielectric layer 102. The bottom electrode 103 may comprise a heater electrode (not shown).
The bottom electrode can be made of at least one electrode material. For example, the bottom electrode 103 may be a tungsten electrode, but is not limited thereto.
The bottom electrode 103 may be a via, ring, or sidewall structure. In this embodiment, the bottom electrode 103 has a structure of four through holes (Via1 to Via 4).
The phase change material layer 106 is a sidewall structure, the phase change material layer 106 may be formed on the plurality of bottom electrodes 103 at the same time, and the phase change material layer 106 may adopt an arc-shaped body structure, an L-shaped structure, or the like longitudinally disposed on the upper surface of the bottom electrodes 103. When an L-shaped structure is adopted, the horizontal bottom edge of the L-shaped structure is connected to the upper surface of the bottom electrode 103, and the upper end of the vertical sidewall of the L-shaped structure is correspondingly connected to the lower end of the top electrode 108.
In this embodiment, the phase change material layer 106 of an arc-shaped sidewall structure formed on the plurality of bottom electrodes 103 at the same time is used. The arc-shaped body cambered surfaces of the phase change material layers 106 connected to the upper surfaces of the two bottom electrodes Via2 and Via4 are arranged oppositely; the arc-shaped body arc surfaces of the phase change material layers 106 connected on the upper surfaces of the two bottom electrodes Via1 and Via3 are arranged oppositely.
The thickness of the phase change material layer 106 of the arc-shaped sidewall structure formed in this way is relatively thin (can be less than 10nm), and the volume is relatively small. Therefore, during the operation of the phase change unit, full phase change can be realized. Meanwhile, the phase change material layer 106 with the arc-shaped sidewall structure is formed on the plurality of bottom electrodes 103 at one time, so that the size of the phase change unit can be reduced, and the high density of the phase change unit is realized.
The material of the phase change material layer 106 may be at least one of a GeTe-Sb2Te3 system, a GeTe-SnTe system, a Sb2Te system, an In3SbTe2 system, an Sb doped system, a Sc doped system, Ag, In, Al, In, C, S, Se, N, Cu, a W element GeTe-Sb2Te3 system, a Sc doped system, Ag, In, Al, In, S, Se, N, Cu, a W element GeTe-SnTe system, a Sc doped system, Ag, In, Al, In, C, S, Se, a W element Sb2Te system, a Sc doped system, Ag, In, Al, In, C, Se, N, Cu, a W element In3 Te2 system, a sbsc doped system, Ag, In, Al, In, C, S, Se, N, Cu, W element Sb doped system.
A method of fabricating a confined phase change cell such as that of fig. 3 according to the present invention is further described with reference to the following detailed description and accompanying fig. 4-9.
The preparation method of the limited phase change unit can comprise the following steps:
s01: as shown in fig. 4, a first dielectric layer 102 is deposited on a substrate 101, and four via-type bottom electrodes 103 are formed in the substrate 101 and the first dielectric layer 102. Wherein, the bottom half of the bottom electrode 103 can be located in the substrate 101, and the upper half can be located in the first dielectric layer 102.
In this embodiment, the bottom electrode 103 may be a tungsten electrode via. The bottom electrode 103 may comprise a heater electrode.
S02: as shown in fig. 5, a second dielectric layer 104 is deposited on the first dielectric layer 102 and the bottom electrode 103, and a first groove 105 structure penetrating the second dielectric layer 104 is formed in the second dielectric layer 104 at a position corresponding to the bottom electrode 103.
The first groove 105 may take one of a circular shape, an elliptical shape, a rectangular shape, and a polygonal shape in a plan view. In the present embodiment, a circular first groove 105 is formed in the second dielectric layer 104. The first groove 105 intersects all four bottom electrodes 103.
S03: as shown in fig. 6, a phase change material layer 106 film is deposited in the first groove 105, and the phase change material layer 106 film is connected to the bottom electrode 103. The phase change material layer 106 may be deposited by atomic layer deposition, chemical vapor deposition, or high density plasma chemical vapor deposition (HDP CVD).
In the present embodiment, a phase change material layer 106 is deposited on the sidewall of the first groove 105 by high density plasma chemical vapor deposition. Because the HDP CVD deposition mode is an alternating deposition-etching-deposition-etching mode, the phase change material layer 106 film can be deposited only on the sidewall of the first groove 105, and no film is deposited on the bottom of the first groove 105, so that the deposited phase change material layer 106 film is in a three-dimensional annular shape. The bottom of the three-dimensional annular phase-change material layer 106 is connected with the upper surfaces of the four bottom electrodes 103.
S04: as shown in fig. 7, the phase change material layer 106 film on the upper surface of the adjacent bottom electrode 103 is broken by photolithography and etching the phase change material layer 106 film.
From the top view, the circular phase change material layer 106 is separated into four arc-shaped phase change material layer 106 films by the photolithography and etching processes.
S05: as shown in fig. 8, the phase change material layer 106 with a vertical sidewall structure is formed on the sidewall of the first groove 105 by depositing the third dielectric layer 107, filling the first groove 105, and grinding the third dielectric layer 107 and the phase change material layer 106 film on the surface of the third dielectric layer 107 until the upper surface of the second dielectric layer 104 is exposed, even if the upper end of the phase change material layer 106 film on the sidewall of the first groove 105 is exposed.
From the top view, four arc-shaped phase change material layers 106 are formed in the first groove 105 by depositing the third dielectric layer 107 and grinding the third dielectric layer 107 and the phase change material layers 106.
S06: as shown in fig. 9, a top electrode metal layer is deposited on the third dielectric layer 107, and a top electrode 108 is formed by photolithography and etching processes.
The confined phase change cell disclosed in the above embodiments includes, from bottom to top, a bottom electrode 103, an arc-shaped phase change material layer 106, and a top electrode 108. The phase change material layers 106 of the four arc-shaped side wall structures are formed on the four bottom electrodes 103 at the same time, and correspond to one another to form four restriction type phase change units. The cambered surfaces of the phase change material layers 106 connected with the upper surfaces of the two bottom electrodes Via2 and Via4 are oppositely arranged; the cambered surfaces of the phase change material layers 106 connected with the upper surfaces of the two bottom electrodes Via1 and Via3 are oppositely arranged. The phase change material layer 106 of the arc-shaped body side wall structure is thin (< 10nm) and small in size, so that full phase change can be achieved in the phase change unit operation process. Meanwhile, the phase change material layers 106 with the arc-shaped side wall structures are formed on the bottom electrodes 103 at one time, so that the size of the phase change unit can be reduced, and the high density of the phase change unit is realized. And the process is simpler and compatible with the standard CMOS process.
In the following detailed description of the present invention, please refer to fig. 10, in which fig. 10 is a schematic structural diagram of a confined phase change cell according to a second preferred embodiment of the present invention. As shown in fig. 10, the difference from the embodiment of fig. 3 is that in this embodiment, a heating electrode 205 is disposed in a dielectric layer between a bottom electrode 203 and a phase-change material layer 208, a lower end of the heating electrode 205 is connected to the bottom electrode 203, and an upper end of the heating electrode 205 is connected to the phase-change material layer 208. The heater electrode 205 is also at least one sidewall structure formed by sidewall deposition. The number of the heating electrodes 205 corresponds to the number of the bottom electrodes 203. The heater electrode 205 may be a ring or L-shaped sidewall structure. Other structures of this embodiment can be understood with reference to the above description of the embodiment of fig. 3.
A method of making a confined phase change cell such as that of fig. 10 according to the present invention is further described with reference to the following detailed description and accompanying fig. 11-17.
The preparation method of the limited phase change unit can comprise the following steps:
s11: as shown in fig. 11, a first dielectric layer 202 is deposited on a substrate 201, and four via-type bottom electrodes 203 are formed in the substrate 101 and the first dielectric layer 202. Wherein the bottom half of the bottom electrode 203 is located in the substrate 201, and the top half is located in the first dielectric layer 202. In this embodiment, the bottom electrode 203 may be a tungsten electrode via, and the diameter may be 30 to 50nm, for example, 40 nm.
S12: as shown in fig. 12, a second dielectric layer 204 is deposited on the first dielectric layer 202 and the bottom electrodes 203, and four heating electrodes 205 penetrating the second dielectric layer 204 are formed in the second dielectric layer 204 at positions corresponding to the respective bottom electrodes 203. The heater electrode 205 may have a ring or L-shaped configuration.
In the present embodiment, the heating electrode 205 has a ring shape. The heating electrode 205 is formed by forming a second recess (or via hole) in the second dielectric layer 204, depositing a heating electrode material on the sidewall surface of the second recess, and connecting the lower end of the heating electrode material to the upper surface of the bottom electrode 203; and depositing a third dielectric layer on the second dielectric layer 204, filling the second groove, and patterning to expose the upper end of the heating electrode material on the sidewall of the second groove, thereby forming an annular or L-shaped heating electrode 205 with a sidewall structure. Wherein, the bottom edge of the heating electrode 205 (or the horizontal bottom edge of the L-shaped structure) is connected to the upper surface of the bottom electrode 203, and the upper end of the heating electrode 205 is used for being correspondingly connected to the lower end of the phase-change material layer.
In this embodiment, a through hole is formed on each bottom electrode 203, and then a heating electrode material is deposited on the inner sidewall of the through hole by using a high density plasma chemical vapor deposition method, where the HDP CVD deposition method is a deposition-etching-deposition-etching method, so that a film of the heating electrode material can be deposited only on the inner sidewall of the through hole, and no film is deposited on the bottom of the through hole, so that the deposited heating electrode is in a three-dimensional ring shape. The bottom of the heating electrode 205 in the shape of a three-dimensional circular ring is connected with the upper surface of the bottom electrode 203.
S13: as shown in fig. 13, a fourth dielectric layer 206 is deposited on the second dielectric layer 204, the third dielectric layer and the heating electrode 205, and a third through-hole 207 structure is formed in the fourth dielectric layer 206 at a position corresponding to the bottom electrode 203.
The third groove 207 may have one of a circular shape, an oval shape, a rectangular shape, or another polygonal shape in a plan view.
In this embodiment, a diamond-shaped third recess 207 is formed in the fourth dielectric layer 206. The diamond-shaped third grooves 207 intersect with all four annular heater electrodes 205.
S14: as shown in fig. 14, a phase-change material layer 208 is deposited in the third groove 207, and the heater electrode 205 is connected to the phase-change material layer 208.
The phase-change material layer 208 may be deposited by atomic layer deposition, chemical vapor deposition, or high density plasma chemical vapor deposition (HDP CVD). In the present embodiment, a phase change material layer 208 is deposited on the sidewalls of the third recess 207 by high density plasma chemical vapor deposition. The HDP CVD deposition method is a deposition-etch-deposition-etch method, so that the phase-change material layer 208 film can be deposited only on the sidewalls of the third groove 207, and no film is deposited on the bottom of the third groove 207, so that the deposited phase-change material layer 208 film is in a diamond ring shape in a top view.
Each ring-shaped heating electrode 205 is connected to at least one portion of the phase-change material layer 208 film. In this embodiment, each ring-shaped heating electrode 205 is connected to 2 portions of the thin film of the phase-change material layer 208.
S15: as shown in fig. 15, the phase change material layer 208 film on the upper surface of the adjacent heater electrode 205 is broken by photolithography and etching the phase change material layer 208 film.
In the present embodiment, the film of phase change material layer 208 above Via1 and Via2, Via2 and Via3, Via3 and Via4, Via4 and Via1 are broken by photo-etching and etching the film of phase change material layer 208.
S16: as shown in fig. 16, a fifth dielectric layer 209 is deposited on the fourth dielectric layer 206, the third recess 207 is filled, and the phase-change material layer 208 films on the surfaces of the fifth dielectric layer 209 and the fifth dielectric layer 209 are ground until the upper end of the phase-change material layer 208 film on the sidewall of the third recess 207 is exposed, and a phase-change material layer 208 with a vertical sidewall structure is formed on each sidewall of the third recess 207. Each phase-change material layer 208 forms two sidewall structures that are connected in a dog-ear state, such that each heater electrode 205 is connected to at least one of the sidewall structures of the phase-change material layer 208.
In this embodiment, each phase change unit has a phase change layer with 2 sidewall structures, that is, each annular heater electrode 205 is connected to the phase change material layer 208 with 2 sidewall structures at the same time, so that the contact area is increased, and the reliability of the device formed by the small-sized phase change material layer can be effectively ensured.
S17: as shown in fig. 17, a top electrode metal layer is deposited on the fifth dielectric layer 209, and a top electrode 210 is formed by photolithography and etching processes.
The confined phase change cell disclosed in the above embodiments includes, from bottom to top, a bottom electrode 203, a ring-shaped heating electrode 205, a phase change material layer 208, and a top electrode 210. Each of the ring-shaped heating electrodes 205 is connected to a phase change material layer 208 having a 2-side wall structure. The area where each heater electrode 205 and phase-change material layer 208 intersect is relatively very small (less than 10nm in size in any direction), and thus a full phase change can be achieved during the phase-change cell operation. Meanwhile, the phase-change material layers 208 with a plurality of sidewall structures are formed on the plurality of bottom electrodes 203 at a time, so that the size of a single phase-change unit can be reduced, and high density of the phase-change unit is realized. And the process is simpler and compatible with the standard CMOS process.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims (12)

1. A limited phase change unit is characterized by comprising a bottom electrode, a phase change material layer and a top electrode which are connected from bottom to top; wherein the phase change material layer is at least one sidewall structure formed by sidewall deposition.
2. The confined phase change cell of claim 1, wherein the bottom electrode comprises a heater electrode.
3. The confined phase change cell of claim 1, wherein a heater electrode is disposed between the bottom electrode and the phase change material layer.
4. The confined phase change cell of claim 3, wherein the heater electrode is at least one sidewall structure formed by sidewall deposition.
5. The confined phase change cell of claim 1, wherein the bottom electrode is coupled to a substrate.
6. The phase-change cell of claim 5, wherein a dielectric layer is disposed on the substrate, and the phase-change cell is embedded in the dielectric layer.
7. A preparation method of a limited phase change unit is characterized by comprising the following steps:
s01: providing a substrate, depositing a first dielectric layer on the substrate, and forming a bottom electrode in the substrate and the first dielectric layer;
s02: depositing a second dielectric layer on the first dielectric layer, and forming a through first groove structure in the second dielectric layer corresponding to the bottom electrode;
s03: depositing a phase change material on the surface of the side wall of the first groove, and connecting the lower end of the phase change material with the bottom electrode;
s04: depositing a third dielectric layer on the second dielectric layer, filling the first groove with the third dielectric layer, and flattening to expose the upper end of the phase change material on the side wall of the first groove to form a phase change material layer with a side wall structure;
s05: and correspondingly forming a top electrode on the third dielectric layer.
8. The method of claim 7, wherein when there are a plurality of bottom electrodes, the method further comprises: in step S03, the phase change material between the bottom electrodes is disconnected; in step S05, a plurality of top electrodes corresponding to the bottom electrodes are formed on the third dielectric layer.
9. The method of claim 7, wherein the bottom electrode comprises a heater electrode.
10. A preparation method of a limited phase change unit is characterized by comprising the following steps:
s11: providing a substrate, depositing a first dielectric layer on the substrate, and forming a bottom electrode in the substrate and the first dielectric layer;
s12: depositing a second dielectric layer on the first dielectric layer, and respectively forming a through second groove structure in the second dielectric layer corresponding to the bottom electrode;
s13: depositing a heating electrode material on the surface of the side wall of the second groove, and connecting the lower end of the heating electrode material with the bottom electrode;
s14: depositing a third dielectric layer on the second dielectric layer, filling the second groove with the third dielectric layer, and flattening to expose the upper end of the heating electrode material on the side wall of the second groove, so as to form an annular heating electrode with a side wall structure;
s15: depositing a fourth dielectric layer on the third dielectric layer, and forming a through third groove structure in the fourth dielectric layer corresponding to the bottom electrode;
s16: depositing a phase change material on the surface of the side wall of the third groove, and connecting the lower end of the phase change material with the heating electrode;
s17: depositing a fifth dielectric layer on the fourth dielectric layer, filling the third groove with the fifth dielectric layer, and flattening to expose the upper end of the phase change material on the side wall of the third groove to form a phase change material layer with a side wall structure;
s18: and correspondingly forming a top electrode on the fifth dielectric layer.
11. The method of claim 10, wherein when there are a plurality of bottom electrodes and heating electrodes, the method further comprises: in step S17, the phase change material between the bottom electrodes is disconnected; in step S18, a plurality of top electrodes corresponding to the bottom electrodes are formed on the fifth dielectric layer.
12. The method of claim 10, wherein in step S16, there are at least two connection points between the lower end of the phase-change material and the upper end of the heating electrode.
CN202010426144.9A 2020-05-19 2020-05-19 Limited phase change unit and preparation method thereof Active CN111564554B (en)

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PCT/CN2020/138318 WO2021232781A1 (en) 2020-05-19 2020-12-22 Limited phase change unit and manufacturing method therefor

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