WO2021232781A1 - Limited phase change unit and manufacturing method therefor - Google Patents

Abstract

A limited phase change unit, comprising from bottom to top: a bottom electrode (103), a phase change material layer (106), and a top electrode (108) which are connected. The phase change material layer (106) is at least one side wall structure formed by using a method for depositing a phase change material thin film on a side wall, so that the contact area of the bottom electrode (103) and a phase change material can be greatly reduced, the power consumption of the phase change unit is reduced, the damage of an etching process to the phase change material is avoided, the reliability of a device is improved, a full phase change operation can be implemented, and the resistance value consistency of the whole column of the phase change unit is facilitated to improved.

Description

Restricted phase change unit and preparation method thereof

cross reference

This application claims the priority of the Chinese patent application with the application number 202010426144.9 filed on May 19, 2020. The content of the above application is included here by reference.

Technical field

The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a constrained phase change unit and a preparation method thereof.

Background technique

With the emergence of a series of new information technologies such as big data, the Internet of Things, cloud computing, and artificial intelligence, high read and write speed, low power consumption, high storage density, long service life, and high reliability are required for memory.

At present, memory storage methods are mainly dynamic random access memory (Dynamic Random Access Memory, DRAM) and flash memory (Flash). Among them, NAND Flash has high integration and low cost, but its speed is slow and its lifespan is short. Although DRAM is fast and has a long lifespan, data will be lost after a power failure, and the cost is high.

Therefore, the development of a new type of storage technology has become a research hotspot in the industry in recent years. This new type of storage technology must have the advantages of DRAM and NAND Flash at the same time, that is, the read and write speed can match DRAM, and it is similar to NAND Flash in terms of cost and non-volatility. Phase change memory is one of the new types of storage technology. A member of the. In recent years, phase-change memory units have broad prospects in the application of artificial intelligence and storage-computing integrated chips.

The existing phase change memory cells are generally divided into two types: one is a mushroom-type phase change cell. As shown in Figure 1, the phase change material has a relatively large volume, and only the phase change material area in contact with the bottom electrode (semi-circle in the figure) The dashed line area) has a phase change, the power consumption of the device is higher, and the device size is larger. The other is a constrained phase change unit, as shown in Figure 2, used in a 3D phase change memory. Through photolithography and etching of the phase change material, a small size phase change material layer is formed, and the phase change material is processed Complete phase change. The device is small in size and low in power consumption, but has high requirements for photolithography and etching processes, and the etching process will damage the sidewall of the small-sized phase change material, which affects the performance and reliability of the device.

Therefore, there is a need to invent a new type of phase change unit structure that can simultaneously meet the multiple requirements of high density, low device power consumption, and simple manufacturing process.

Summary of the invention

The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a restricted phase change unit and a preparation method thereof.

In order to achieve the above objective, the technical solution of the present invention is as follows:

A constrained phase change unit includes a bottom electrode, a phase change material layer and a top electrode connected from bottom to top; wherein the phase change material layer is at least one sidewall structure formed by sidewall deposition.

Further, the bottom electrode includes a heating electrode.

Further, a heating electrode is provided between the bottom electrode and the phase change material layer.

Further, the heating electrode is at least one sidewall structure formed by sidewall deposition.

Further, the bottom electrode is connected to a substrate.

Further, a dielectric layer is provided on the substrate, and the constrained phase change unit is embedded in the dielectric layer.

A method for preparing a restricted phase change unit includes the following steps:

S01: Provide a substrate, deposit a first dielectric layer on the substrate, and form a bottom electrode in the substrate and the first dielectric layer;

S02: Depositing a second dielectric layer on the first dielectric layer, and forming a through first groove structure in the second dielectric layer corresponding to the position of the bottom electrode;

S03: Deposit a phase change material on the sidewall surface of the first groove, and connect the lower end of the phase change material with the bottom electrode;

S04: Depositing a third dielectric layer on the second dielectric layer, filling and planarizing the first groove, so that the upper end of the phase change material on the sidewall of the first groove is exposed to form Phase change material layer with sidewall structure;

S05: Correspondingly form a top electrode on the third dielectric layer.

Further, when there are multiple bottom electrodes, it further includes: in step S03, disconnecting the phase change material between each of the bottom electrodes; in step S05, forming on the third dielectric layer A plurality of top electrodes corresponding to the bottom electrode.

Further, the bottom electrode includes a heating electrode.

A method for preparing a restricted phase change unit includes the following steps:

S11: providing a substrate, depositing a first dielectric layer on the substrate, and forming a bottom electrode in the substrate and the first dielectric layer;

S12: Depositing a second dielectric layer on the first dielectric layer, and respectively forming a through second groove structure in the second dielectric layer corresponding to the position of the bottom electrode;

S13: Depositing a heating electrode material on the sidewall surface of the second groove, and connecting the lower end of the heating electrode material with the bottom electrode;

S14: Depositing a third dielectric layer on the second dielectric layer, filling and planarizing the second groove, so that the upper end of the heating electrode material on the sidewall of the second groove is exposed to form Annular heating electrode with side wall structure;

S15: Depositing a fourth dielectric layer on the third dielectric layer, and forming a through third groove structure in the fourth dielectric layer corresponding to the position of the bottom electrode;

S16: Depositing a phase change material on the sidewall surface of the third groove, and connecting the lower end of the phase change material with the heating electrode;

S17: Depositing a fifth dielectric layer on the fourth dielectric layer, filling and planarizing the third groove, so that the upper end of the phase change material on the sidewall of the third groove is exposed to form Phase change material layer with sidewall structure;

S18: Correspondingly form a top electrode on the fifth dielectric layer.

Further, when there are multiple corresponding bottom electrodes and heating electrodes, the method further includes: in step S17, disconnecting the phase change material between the bottom electrodes; in step S18, A plurality of top electrodes corresponding to the bottom electrodes are formed on the fifth dielectric layer.

Further, in step S16, there are at least two connection points between the lower end of the phase change material and the upper end of the heating electrode.

It can be seen from the above technical solutions that the present invention prepares a confined phase change unit by using a method of depositing a phase change material film on the sidewall, which can greatly reduce the contact area between the bottom electrode and the phase change material, thereby reducing the phase change unit. Power consumption. At the same time, the sidewall type phase change layer avoids damage to the phase change material caused by the traditional etching process, and improves the reliability of the device. In addition, the thickness of the sidewall type phase change material can be very thin (<10nm), which can realize full phase change operation, which is beneficial to improve the resistance uniformity of the entire array of phase change units. By adopting the preparation method of the present invention, the cell size of the phase change unit can be reduced, high-density storage can be realized, and the manufacturing process is relatively simple, which is compatible with the existing standard CMOS process.

Description of the drawings

Figures 1 to 2 are schematic diagrams of an existing phase change unit structure.

3 is a schematic diagram of the structure of a constrained phase change unit according to the first preferred embodiment of the present invention.

4 to 9 are schematic diagrams of the process steps for preparing a constrained phase change unit of FIG. 3.

10 is a schematic diagram of the structure of a constrained phase change unit according to the second preferred embodiment of the present invention.

11-17 are schematic diagrams of the process steps for preparing a constrained phase change unit of FIG. 10.

Detailed ways

The core idea of the present invention is to provide a constrained phase change unit structure and a preparation method thereof. The constrained phase change unit includes a bottom electrode, a phase change material layer and a top electrode connected from bottom to top, and the phase change material layer is the adopting side. At least one sidewall structure formed by the method of depositing a phase change material film on the wall can greatly reduce the contact area between the bottom electrode and the phase change material, reduce the power consumption of the phase change unit, and avoid damage to the phase change material caused by the etching process. The reliability of the device is improved, and the full phase change operation can be realized, which is beneficial to improve the resistance consistency of the entire column of the phase change unit.

By adopting the preparation method of the present invention, the cell size of the phase change unit can be reduced, high-density storage can be realized, and the manufacturing process is relatively simple, which is compatible with the existing standard CMOS process.

The specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

It should be noted that in the following specific embodiments, when the embodiments of the present invention are described in detail, in order to clearly show the structure of the present invention for ease of description, the structure in the drawings is not drawn in accordance with the general scale. Partial enlargement, deformation, and simplification of processing have been implemented. Therefore, this should not be interpreted as a limitation of the present invention.

In the following specific embodiments of the present invention, please refer to FIG. 3, which is a schematic diagram of a constrained phase change unit structure according to a preferred embodiment 1 of the present invention. As shown in Figure 3 (the bottom of the figure is the top view structure, the top of the figure is the cross-sectional structure along the direction of the double dashed line in the bottom of the figure, the same below), a constrained phase change unit of the present invention can be built on a substrate 101 . The substrate 101 may be provided with one to multiple dielectric layers, such as a first dielectric layer, a second dielectric layer, and a third dielectric layer 102, 104, 107. The constrained phase change unit can be embedded in the dielectric layer.

The substrate 101 may include a semiconductor material, such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a silicon germanium substrate, or a fully depleted silicon-on-insulator (FDSOI) substrate. The substrate 101 may also be an integrated circuit, including an integrated circuit having a gate tube such as a triode, a diode, and the like.

Please refer to Figure 3. The bottom electrode 103 can be located in the substrate 101 and the first dielectric layer 102 at the same time, and one or more can be provided. For example, the lower part of the four bottom electrodes 103 shown in the figure may be located in the substrate 101, and the upper part may be exposed on the surface of the substrate 101 and located in the first dielectric layer 102. The bottom electrode 103 may include a heating electrode (not shown in the figure).

The bottom electrode can be made of at least one electrode material. For example, the material of the bottom electrode 103 can be a tungsten electrode or the like, but it is not limited thereto.

The bottom electrode 103 may be a through hole, a ring shape, or a sidewall structure. In this embodiment, a bottom electrode 103 with a structure of four through holes (Via1 to Via4) is used.

The phase change material layer 106 has a sidewall structure. The phase change material layer 106 can be formed on a plurality of bottom electrodes 103 at the same time.形结构 etc. When the L-shaped structure is adopted, the horizontal bottom side of the L-shaped structure is connected to the upper surface of the bottom electrode 103, and the upper end of the vertical sidewall of the L-shaped structure is correspondingly connected to the lower end of the top electrode 108.

In this embodiment, a phase change material layer 106 with an arc-shaped sidewall structure formed on a plurality of bottom electrodes 103 at the same time is used. The arcs of the phase change material layer 106 connected on the upper surfaces of the two bottom electrodes Via2 and Via4 are arranged opposite to each other; the arcs of the phase change material layer 106 connected on the upper surfaces of the two bottom electrodes Via1 and Via3 The curved surfaces of the body are set relative to each other.

The thickness of the phase change material layer 106 of the arc-shaped sidewall structure formed in this way is relatively thin (may be less than 10 nm), and the volume is relatively small. Therefore, during the operation of the phase change unit, a full phase change can be realized. At the same time, the phase change material layer 106 of the arc-shaped sidewall structure is simultaneously formed on the multiple bottom electrodes 103 at one time, which can reduce the size of the phase change unit and realize the high density of the phase change unit.

The material of the phase change material layer 106 can be GeTe-Sb ₂ Te ₃ system, GeTe-SnTe system, Sb ₂ Te system, In ₃ SbTe ₂ system, Sb doped system, doped Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements GeTe-Sb ₂ Te ₃ system, doped Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements GeTe-SnTe system _{, Sb 2} Te system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W, doped Sc, Ag, In, Al, In, C, S, Se, N At least one of the In ₃ SbTe ₂ system of Cu and W elements, and the Sb doping system of doped Sc, Ag, In, Al, In, C, S, Se, N, Cu, and W elements.

Hereinafter, a method for preparing the constrained phase change unit shown in FIG. 3 according to the present invention will be further described through specific embodiments and accompanying drawings 4 to 9.

The method for preparing a restricted phase change unit of the present invention may include the following steps:

S01: As shown in FIG. 4, a first dielectric layer 102 is deposited on the substrate 101, and four through-hole bottom electrodes 103 are formed in the substrate 101 and the first dielectric layer 102. Wherein, the lower half of the bottom electrode 103 can be located in the substrate 101, and the upper half can be located in the first dielectric layer 102.

In this embodiment, the bottom electrode 103 may be a tungsten electrode through hole. The bottom electrode 103 may include a heating electrode.

S02: As shown in FIG. 5, a second dielectric layer 104 is deposited on the first dielectric layer 102 and the bottom electrode 103, and a first dielectric layer 104 penetrating through the second dielectric layer 104 is formed in the second dielectric layer 104 corresponding to the position of the bottom electrode 103. A groove 105 structure.

From a plan view, the first groove 105 may adopt one of a circle, an ellipse, a rectangle, and a polygon. In this embodiment, a circular first groove 105 is formed in the second dielectric layer 104. The first groove 105 and the four bottom electrodes 103 all intersect.

S03: As shown in FIG. 6, a thin film of the phase change material layer 106 is deposited in the first groove 105, and the thin film of the phase change material layer 106 is connected to the bottom electrode 103. The thin film of the phase change material layer 106 may be deposited by atomic layer deposition, chemical vapor deposition, or high-density plasma chemical vapor deposition (HDP CVD).

In this embodiment, the phase change material layer 106 thin film is deposited on the sidewall of the first groove 105 by means of high-density plasma chemical vapor deposition. Since the HDP CVD deposition method is an alternate method of deposition-etching-deposition-etching, the thin film of the phase change material layer 106 can be deposited only on the sidewalls of the first groove 105, and on the sidewall of the first groove 105 There is no film deposition on the bottom, so that the deposited phase change material layer 106 film has a three-dimensional circular ring shape. The bottom of the three-dimensional annular phase change material layer 106 is connected to the upper surfaces of the four bottom electrodes 103.

S04: As shown in FIG. 7, the phase change material layer 106 film on the upper surface of the adjacent bottom electrode 103 is disconnected by photolithography and etching of the phase change material layer 106 film.

From the top view, the annular phase change material layer 106 film is divided into four arc-shaped phase change material layer 106 films through photolithography and etching processes.

S05: As shown in FIG. 8, the first groove 105 is filled by depositing the third dielectric layer 107, and the third dielectric layer 107 is ground until the upper surface of the second dielectric layer 104 is exposed, even though the first groove The upper end of the film of the phase change material layer 106 on the sidewall of 105 is exposed, so that a phase change material layer 106 having a vertical sidewall structure is formed on the sidewall of the first groove 105.

From a plan view, by depositing the third dielectric layer 107 and grinding the third dielectric layer 107 and the phase change material layer 106, four arc-shaped phase change material layers 106 are formed in the first groove 105.

S06: As shown in FIG. 9, a top electrode metal layer is deposited on the third dielectric layer 107, and the top electrode 108 is formed through photolithography and etching processes.

A constrained phase change unit disclosed in the above embodiment includes a bottom electrode 103, an arc-shaped phase change material layer 106, and a top electrode 108 in order from bottom to top. Four phase change material layers 106 with arc-shaped sidewall structures are formed on the four bottom electrodes 103 at the same time, corresponding to each other to form four constrained phase change units. Wherein, the arc surfaces of the phase change material layer 106 connected to the upper surfaces of the two bottom electrodes Via2 and Via4 are arranged opposite to each other; the arc surfaces of the phase change material layer 106 connected to the upper surfaces of the two bottom electrodes Via1 and Via3 are arranged opposite to each other. The phase change material layer 106 of the arc-shaped sidewall structure has a relatively thin thickness (<10 nm) and a small volume, so that a full phase change can be realized during the operation of the phase change unit. At the same time, forming multiple arc-shaped sidewall structure phase change material layers 106 on multiple bottom electrodes 103 at one time can reduce the size of the phase change unit and achieve a high density of the phase change unit. And the craft is relatively simple, compatible with standard CMOS craft.

In the following specific embodiments of the present invention, please refer to FIG. 10, which is a schematic diagram of the structure of a constrained phase change unit according to the second preferred embodiment of the present invention. As shown in FIG. 10, the difference from the embodiment in FIG. 3 is that in this embodiment, the heating electrode 205 is arranged in the dielectric layer between the bottom electrode 203 and the phase change material layer 208, and the lower end of the heating electrode 205 is connected to the bottom electrode 203. , The upper end of the heating electrode 205 is connected to the phase change material layer 208. The heating electrode 205 is also at least one sidewall structure formed by sidewall deposition. The number of heating electrodes 205 corresponds to the number of bottom electrodes 203 one-to-one. The heating electrode 205 may have a ring-shaped or L-shaped sidewall structure. The other structure of this embodiment can be understood with reference to the above description of the embodiment in FIG. 3.

Hereinafter, a method for preparing the constrained phase change unit shown in FIG. 10 according to the present invention will be further described through specific embodiments and FIGS. 11-17.

The method for preparing a restricted phase change unit of the present invention may include the following steps:

S11: As shown in FIG. 11, a first dielectric layer 202 is deposited on the substrate 201, and four through-hole bottom electrodes 203 are formed in the substrate 101 and the first dielectric layer 202. Wherein, the lower half of the bottom electrode 203 can be located in the substrate 201, and the upper half can be located in the first dielectric layer 202. In this embodiment, the bottom electrode 203 may be a tungsten electrode through hole, and the diameter may be 30-50 nm, for example, it may be 40 nm.

S12: As shown in FIG. 12, a second dielectric layer 204 is deposited on the first dielectric layer 202 and the bottom electrode 203, and a second dielectric layer 204 is formed in the second dielectric layer 204 corresponding to the position of each bottom electrode 203. A heating electrode 205. The heating electrode 205 may have a ring-shaped or L-shaped structure.

In this embodiment, the heating electrode 205 has a ring shape. The heating electrode 205 is formed by first forming a second groove (or through hole) in the second dielectric layer 204, depositing the heating electrode material on the sidewall surface of the second groove, and making the heating electrode material The lower end is connected to the upper surface of the bottom electrode 203; a third dielectric layer is deposited on the second dielectric layer 204 to fill the second groove and pattern it so that the upper end of the heating electrode material on the sidewall of the second groove is exposed , The heating electrode 205 having a ring or L-shaped structure with a sidewall structure is formed. Wherein, the bottom edge of the heating electrode 205 (or the horizontal bottom edge of the L-shaped structure) is connected to the upper surface of the bottom electrode 203, and the upper end of the heating electrode 205 is used for subsequent corresponding connection to the lower end of the phase change material layer.

In this embodiment, a through hole is formed on each bottom electrode 203, and then a high-density plasma chemical vapor deposition method is used to deposit the heating electrode material on the inner side wall of the through hole. The HDP CVD deposition method is deposition-etching -Deposition-etching method, so that the heating electrode material film can be deposited only on the inner sidewall of the through hole, and no film is deposited on the bottom of the through hole, so that the deposited heating electrode has a three-dimensional ring shape. The bottom of the three-dimensional circular heating electrode 205 is connected to the upper surface of the bottom electrode 203.

S13: As shown in FIG. 13, a fourth dielectric layer 206 is deposited on the second dielectric layer 204, the third dielectric layer and the heating electrode 205, and a through third dielectric layer 206 is formed in the fourth dielectric layer 206 corresponding to the position of the bottom electrode 203. The groove 207 structure.

From a plan view, the third groove 207 may be circular, elliptical, rectangular, or other polygonal shapes.

In this embodiment, a diamond-shaped third groove 207 is formed in the fourth dielectric layer 206. The diamond-shaped third groove 207 and the four ring-shaped heating electrodes 205 all intersect.

S14: As shown in FIG. 14, a thin film of the phase change material layer 208 is deposited in the third groove 207, so that the heating electrode 205 and the thin film of the phase change material layer 208 are connected.

The thin film of the phase change material layer 208 may be deposited by atomic layer deposition, chemical vapor deposition, or high-density plasma chemical vapor deposition (HDP CVD). In this embodiment, a thin film of the phase change material layer 208 is deposited on the sidewall of the third groove 207 by means of high-density plasma chemical vapor deposition. The HDP CVD deposition method is a deposition-etch-deposition-etch method, so the phase change material layer 208 can be deposited only on the sidewalls of the third groove 207, but not on the bottom of the third groove 207 Thin film deposition makes the deposited phase change material layer 208 thin film in a rhombus ring shape when viewed from above.

Each ring-shaped heating electrode 205 is connected to at least one part of the phase change material layer 208 thin film. In this embodiment, each ring-shaped heating electrode 205 and the phase change material layer 208 film have two parts connected.

S15: As shown in FIG. 15, the thin film of the phase change material layer 208 on the upper surface of the adjacent heating electrode 205 is disconnected by photolithography and etching.

In this embodiment, the phase change material layer 208 film on Via1 and Via2, Via2 and Via3, Via3 and Via4, Via4 and Via1 is disconnected by photolithography and etching of the phase change material layer 208 film.

S16: As shown in FIG. 16, a fifth dielectric layer 209 is deposited on the fourth dielectric layer 206, the third groove 207 is filled, and the fifth dielectric layer 209 is ground until the phase on the sidewall of the third groove 207 The upper end of the film of the variable material layer 208 is exposed, and a phase change material layer 208 with a vertical sidewall structure is formed on the sidewalls of the third groove 207. Each phase change material layer 208 forms two sidewall structures connected in a cornered state, so that each heating electrode 205 is connected to at least one of the sidewall structures of the phase change material layer 208.

In this embodiment, each phase change unit has two phase change layers with sidewall structures, that is, each ring-shaped heating electrode 205 is connected to the phase change material layer 208 with two sidewall structures at the same time, which increases the contact area. , Can effectively ensure the reliability of the device formed by the small-sized phase change material layer.

S17: As shown in FIG. 17, a top electrode metal layer is deposited on the fifth dielectric layer 209, and the top electrode 210 is formed through photolithography and etching processes.

A constrained phase change unit disclosed in the above embodiment includes a bottom electrode 203, a ring-shaped heating electrode 205, a phase change material layer 208, and a top electrode 210 from bottom to top. Each ring-shaped heating electrode 205 is connected to a phase change material layer 208 having two sidewall structures. The intersecting area of each heating electrode 205 and the phase change material layer 208 is relatively very small (the size in any direction is less than 10 nm), so during the operation of the phase change unit, a full phase change can be realized. At the same time, forming multiple sidewall structure phase change material layers 208 on multiple bottom electrodes 203 at one time can reduce the size of a single phase change unit and achieve a high density of phase change units. And the craft is relatively simple, compatible with standard CMOS craft.

The above are only the preferred embodiments of the present invention, and the described embodiments are not intended to limit the scope of protection of the present invention. Therefore, all equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the same reasoning. Within the protection scope of the present invention.

Claims (12)

1. A constrained phase change unit, characterized in that it comprises a bottom electrode, a phase change material layer and a top electrode connected from bottom to top; wherein the phase change material layer is at least one sidewall formed by sidewall deposition structure.
2. The constrained phase change unit according to claim 1, wherein the bottom electrode comprises a heating electrode.
3. The constrained phase change unit according to claim 1, wherein a heating electrode is provided between the bottom electrode and the phase change material layer.
4. The constrained phase change unit according to claim 3, wherein the heating electrode is at least one sidewall structure formed by sidewall deposition.
5. The constrained phase change unit according to claim 1, wherein the bottom electrode is connected to a substrate.
6. The confinement phase change unit according to claim 5, wherein a dielectric layer is provided on the substrate, and the confinement phase change unit is embedded in the dielectric layer.
7. A method for preparing a restricted phase change unit is characterized in that it comprises the following steps:

   S01: Provide a substrate, deposit a first dielectric layer on the substrate, and form a bottom electrode in the substrate and the first dielectric layer;

   S02: Depositing a second dielectric layer on the first dielectric layer, and forming a through first groove structure in the second dielectric layer corresponding to the position of the bottom electrode;

   S03: Deposit a phase change material on the sidewall surface of the first groove, and connect the lower end of the phase change material with the bottom electrode;

   S04: Depositing a third dielectric layer on the second dielectric layer, filling and planarizing the first groove, so that the upper end of the phase change material on the sidewall of the first groove is exposed to form Phase change material layer with sidewall structure;

   S05: Correspondingly form a top electrode on the third dielectric layer.
8. The method for preparing a constrained phase change unit according to claim 7, characterized in that, when there are multiple bottom electrodes, the method further comprises: in step S03, the phase change material between the bottom electrodes Disconnect; In step S05, a plurality of top electrodes corresponding to the bottom electrodes are formed on the third dielectric layer.
9. 7. The method for preparing a constrained phase change unit according to claim 7, wherein the bottom electrode comprises a heater electrode.
10. A method for preparing a restricted phase change unit is characterized in that it comprises the following steps:

    S11: providing a substrate, depositing a first dielectric layer on the substrate, and forming a bottom electrode in the substrate and the first dielectric layer;

    S12: Depositing a second dielectric layer on the first dielectric layer, and respectively forming a through second groove structure in the second dielectric layer corresponding to the position of the bottom electrode;

    S13: Depositing a heating electrode material on the sidewall surface of the second groove, and connecting the lower end of the heating electrode material with the bottom electrode;

    S14: Depositing a third dielectric layer on the second dielectric layer, filling and planarizing the second groove, so that the upper end of the heating electrode material on the sidewall of the second groove is exposed to form Annular heating electrode with side wall structure;

    S15: Depositing a fourth dielectric layer on the third dielectric layer, and forming a through third groove structure in the fourth dielectric layer corresponding to the position of the bottom electrode;

    S16: Depositing a phase change material on the sidewall surface of the third groove, and connecting the lower end of the phase change material with the heating electrode;

    S17: Depositing a fifth dielectric layer on the fourth dielectric layer, filling and planarizing the third groove, so that the upper end of the phase change material on the sidewall of the third groove is exposed to form Phase change material layer with sidewall structure;

    S18: Correspondingly form a top electrode on the fifth dielectric layer.
11. The method for preparing a constrained phase change unit according to claim 10, wherein when the bottom electrode and the heating electrode are correspondingly multiple, the method further comprises: in step S17, the bottom electrode The phase change material in between is disconnected; in step S18, a plurality of top electrodes corresponding to the bottom electrode are formed on the fifth dielectric layer.
12. The method for preparing a constrained phase change unit according to claim 10, wherein in step S16, there are at least two connection points between the lower end of the phase change material and the upper end of the heating electrode.

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