CN111564470A - Three-dimensional resistive random access memory and manufacturing method thereof - Google Patents
Three-dimensional resistive random access memory and manufacturing method thereof Download PDFInfo
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- CN111564470A CN111564470A CN202010425143.2A CN202010425143A CN111564470A CN 111564470 A CN111564470 A CN 111564470A CN 202010425143 A CN202010425143 A CN 202010425143A CN 111564470 A CN111564470 A CN 111564470A
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- 239000000463 material Substances 0.000 claims abstract description 65
- 238000002955 isolation Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000003860 storage Methods 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000007772 electrode material Substances 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
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- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 230000015654 memory Effects 0.000 description 29
- 230000010354 integration Effects 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 5
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
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- 238000013459 approach Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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Abstract
The invention discloses a three-dimensional resistive random access memory, which comprises: the device comprises a substrate, a plurality of layers of horizontal conductive electrodes formed on the substrate, and an isolation medium layer formed between the horizontal conductive electrodes; two resistive random access memory layers are vertically arranged between the horizontal conductive electrode and the isolation dielectric layer, vertical conductive electrodes connected with the resistive random access memory layers are arranged on the inner sides of the two resistive random access memory layers, the side walls of the resistive random access memory layers are connected with the end portions of the horizontal conductive electrodes through gating material layers arranged on the same layer as the horizontal conductive electrodes, and the isolation dielectric layer separates the gating material layers from top to bottom. The three-dimensional resistive random access memory has the self-gating characteristic, can effectively improve the storage density, is compatible with a CMOS (complementary metal oxide semiconductor) process, and is beneficial to popularization and application. The invention also discloses a manufacturing method of the three-dimensional resistive random access memory.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a three-dimensional resistive random access memory and a manufacturing method thereof.
Background
Memory is one of the core components of modern information technology, and the global market has exceeded $ 700 billion. The amount of data required to be stored and processed in the big data era has increased at about 60% per year, reaching 40ZB in 2020. Therefore, it is necessary to develop a high-speed, high-density, low-power-consumption memory technology, expand the memory-logic fusion function thereof, and develop an efficient computing system.
With the arrival of the big data era, the two-dimensional architecture for improving the storage density of mass data in a planar micro mode is far from meeting the requirements of data explosion type growth on high density and high capacity of a storage, and three-dimensional integration gradually becomes the mainstream development trend of the future storage technology.
At present, the main three-dimensional memory on the market is 3D NAND Flash, and the mainstream technology is 64-96 layers. It is expected that 128-layer 3D NAND Flash will also come into the world soon and be used on a large scale.
With the development of integrated circuits along with moore's law, the speed of signal processing chips such as CPUs is faster and faster, but the working speed of mainstream memories cannot be correspondingly increased. The problem of "storage walls" is therefore increasingly apparent and exacerbated. The development speed of the memory is faster, the power consumption is lower, and the density is higher, wherein various new memories are expected.
The resistive random access memory is a novel memory suitable for low-power consumption and low-cost application, and can be three-dimensionally integrated. Common three-dimensional integration approaches include planar stacked three-dimensional integration and vertical three-dimensional integration. The vertical three-dimensional integration mode has obvious advantages in the case of integration with a large number of layers because the vertical three-dimensional integration mode can realize three-dimensional integration by using fewer photomasks. Because of the leakage channel crosstalk in the cross array, it is necessary to connect the resistive switching device and the gating device in series or to prepare a self-gating resistive switching device having self-gating. For vertical three-dimensional integration, a self-selecting resistive switching device with self-gating is preferred.
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional three-dimensional resistive random access memory. As shown in fig. 1, in the prior art, since the gate material layer 06 and the resistance change memory layer 07 in the self-gating device are both placed upright, it is difficult to pattern them in the longitudinal direction. However, if the gate material layer 06 and the resistance change memory layer 07 are not patterned, reliability problems will be caused subsequently, and the service life of the memory device is affected.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a three-dimensional resistive random access memory and a manufacturing method thereof, so as to solve the problems of electric leakage, reliability and the like of the conventional self-selection RRAM in vertical three-dimensional integration, realize a high-density three-dimensional RRAM and reduce the cost of a unit area memory.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a three-dimensional resistive random access memory comprising:
the device comprises a substrate, a plurality of layers of horizontal conductive electrodes formed on the substrate, and an isolation medium layer formed between the horizontal conductive electrodes; two resistive random access memory layers are vertically arranged between the horizontal conductive electrode and the isolation dielectric layer, vertical conductive electrodes connected with the resistive random access memory layers are arranged on the inner sides of the two resistive random access memory layers, the side walls of the resistive random access memory layers are connected with the end portions of the horizontal conductive electrodes through gating material layers arranged on the same layer as the horizontal conductive electrodes, and the isolation dielectric layer separates the gating material layers from top to bottom.
Further, an insulating medium layer is arranged between the substrate and the plurality of horizontal conductive electrodes.
Furthermore, a protective dielectric layer is arranged on the plurality of horizontal conductive electrodes and is separated by the resistance change storage layer.
A manufacturing method of a three-dimensional resistive random access memory comprises the following steps:
step S01: providing a substrate, and alternately forming a plurality of layers of horizontal conductive electrodes and isolation medium layers on the substrate;
step S02: forming a trench downwards to penetrate through the plurality of layers of horizontal conductive electrodes and the isolation dielectric layer;
step S03: processing the end part of the horizontal conductive electrode exposed on the side wall of the groove, and forming a gating material layer between the surface of the side wall of the groove and the horizontal conductive electrode;
step S04: and forming a resistance change storage layer along the inner wall of the groove, and forming a vertical conductive electrode on the resistance change storage layer.
Further, in step S03, the processing the end portion of the horizontal conductive electrode exposed on the trench sidewall includes: removing part of the horizontal conductive electrode material exposed on the side wall of the groove, forming a concave structure on the side wall of the groove, and then forming a gating material layer in the concave structure.
Further, removing part of the horizontal conductive electrode material by adopting a chemical etching or wet etching method to form a concave structure.
Further, growing a gating material in the concave structure by adopting an atomic layer deposition method, and then removing the gating material on the side wall of the isolation medium layer by adopting dry etching to form a gating material layer embedded in the concave structure.
And further, when the gating material on the side wall of the isolation medium layer is removed by adopting dry etching, the isolation medium layer is aligned with the side wall surface of the gating material layer.
Further, oxidizing the end material of the horizontal conductive electrode exposed in the concave structure in an oxidation mode to form an oxide layer of the horizontal conductive electrode material as the gating material layer.
Further, step S01 includes: before forming a plurality of horizontal conductive electrodes and isolation dielectric layers, an insulating dielectric layer is formed on the silicon substrate, and a protective dielectric layer is formed on the uppermost horizontal conductive electrode.
According to the technical scheme, the end material of the horizontal conductive electrode is removed, the inner concave structure is formed on the side wall of the groove, the gating material is filled in the inner concave structure, or the end material of the horizontal conductive electrode in the inner concave structure is directly oxidized, the formed oxide layer is used as the gating material, the imaging of the gating material is realized, meanwhile, the isolation dielectric layer is flush with the surface of the side wall of the gating material layer, the flatness of the surface of the resistive random access memory layer formed on the side wall of the groove is realized, the electric leakage is avoided, the reliability of the memory device is improved, and finally the high-density and high-reliability three-dimensional resistive random access memory is realized.
Drawings
Fig. 1 is a schematic structural diagram of a conventional three-dimensional resistive random access memory.
Fig. 2 is a schematic structural diagram of a three-dimensional resistive random access memory according to a preferred embodiment of the invention.
Fig. 3 is a flow chart illustrating a method for manufacturing a three-dimensional resistive random access memory according to a preferred embodiment of the invention.
Fig. 4 to 8 are schematic views of process steps of manufacturing a three-dimensional resistive random access memory according to a preferred embodiment of the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the invention, please refer to fig. 2, and fig. 2 is a schematic diagram of a three-dimensional resistive random access memory according to a preferred embodiment of the invention. As shown in fig. 2, the three-dimensional resistive random access memory of the present invention may include:
a silicon substrate 01;
the device comprises a plurality of layers of horizontal conductive electrodes 031-033 formed on a silicon substrate 01, and isolation medium layers 041-042 formed among the horizontal conductive electrodes 031-033.
In this embodiment, three horizontal conductive electrodes 031-033 and two isolation dielectric layers 041-042 arranged between the three horizontal conductive electrodes 031-033 are disposed on the silicon substrate 01.
In addition, an insulating medium layer 02 can be arranged between the silicon substrate 01 and the lowest horizontal conductive electrode 031 of the multiple horizontal conductive electrodes 031-033, and a protective medium layer 05 can be arranged on the highest horizontal conductive electrode 033 of the multiple horizontal conductive electrodes 031-033.
One or more U-shaped resistive memory layers 09 (shown as two U-shaped resistive memory layers 09) are vertically arranged between each layer of horizontal conductive electrodes 031-033 and each isolation dielectric layer 041-042 (including the protection dielectric layer 05). The upper end of the U-shaped resistance change storage layer 09 can be flush with the surface of the protective dielectric layer 05; the lower end of the U-shaped resistive memory layer 09 is located on the insulating dielectric layer 02.
Please refer to fig. 2. A vertical conductive electrode 10 is arranged in the U-shaped resistance change memory layer 09; the vertical conductive electrode 10 is connected to the inner side of the resistance change memory layer 09. Meanwhile, a gating material layer 08 is arranged between the outer side wall of the resistive memory layer 09 and the end parts of the horizontal conductive electrodes 031-033; the resistive memory layer 09, the gating material layer 08 and the horizontal conductive electrodes 031-033 are connected in sequence. In addition, the gating material layer 08 and the horizontal conductive electrodes 031-033 are disposed in the same layer, so that the isolation dielectric layers 041-042 separate the gating material layer 08 into, for example, three layers as shown in the figure.
In fact, one resistive memory layer 09 is respectively formed on two vertical sides of the U-shape of the resistive memory layer 09, that is, each layer of horizontal conductive electrodes 031-033 and the isolation dielectric layers 041-042 (including the protection dielectric layer 05) are separated by two vertically arranged resistive memory layers 09.
In this embodiment, the lower ends of the two vertically arranged resistance change memory layers 09 are connected by extending the material thereof, so that one U-shaped resistance change memory layer 09 is formed. But not limited thereto, the lower ends of the two vertically arranged resistance change memory layers 09 may be disconnected from each other.
The following describes a method for manufacturing a three-dimensional resistive random access memory in detail by using a specific embodiment and with reference to the accompanying drawings.
Referring to fig. 3 in combination with fig. 4 to 8, fig. 3 is a flow chart illustrating a method for manufacturing a three-dimensional resistive random access memory according to a preferred embodiment of the invention, and fig. 4 to 8 are process steps illustrating the method for manufacturing a three-dimensional resistive random access memory according to a preferred embodiment of the invention. As shown in fig. 3, a method for manufacturing a three-dimensional resistive random access memory according to the present invention can be used to manufacture the above three-dimensional resistive random access memory structure shown in fig. 2, and may include the following steps:
step S01: providing a substrate, and alternately forming a plurality of layers of horizontal conductive electrodes and isolating medium layers on the substrate.
Please refer to fig. 4. A silicon substrate 01 may be used, and an insulating dielectric layer 02 may be deposited on the silicon substrate 01.
Then, horizontal conductive electrodes 031-033 and isolation dielectric layers 041-042 are sequentially deposited on the insulating dielectric layer 02 to form three layers of horizontal conductive electrodes 031-033 and two layers of isolation dielectric layers 041-042, for example, and the three layers of horizontal conductive electrodes 031-033 are isolated from each other by the isolation dielectric layers 041-042. Finally, a protective dielectric layer 05 is deposited over the third horizontal conductive electrode 033.
The substrate 01 may be a silicon wafer on which fabrication of the desired processing circuitry has been completed and then the resistive random access memory fabrication is started.
In this embodiment, a 12-inch silicon wafer can be used as the substrate 01, and 800 to 1200 angstroms, for example, 1000 angstroms of silicon dioxide can be deposited on the silicon wafer substrate 01 as the insulating dielectric layer 02.
Then, horizontal conductive electrodes 031-033 material and isolation dielectric layers 041-042 material are deposited in sequence.
In this embodiment, 200-400 angstroms, such as 300 angstroms, of Ti can be deposited as the horizontal conductive electrodes 031-033 material, and 400-600 angstroms, such as 500 angstroms, of silicon dioxide can be deposited as the isolation dielectric layers 041-042 material. Finally, 900-1100 angstroms, for example 1000 angstroms, of silicon dioxide can be deposited as a protective dielectric layer 05 to form three horizontal conductive electrodes 031-033 spaced apart from each other in the horizontal direction.
Step S02: and forming a groove downwards to penetrate through the plurality of layers of horizontal conductive electrodes and the isolation dielectric layer.
Please refer to fig. 5. The three-layer horizontal conductive electrodes 031-033 may be etched by using photolithography and etching processes, and the grooves 11 may be formed in the three-layer horizontal conductive electrodes 031-033.
In this embodiment, the dry etching is used to etch the protective dielectric layer 05, the isolation dielectric layers 041 to 042 and the horizontal conductive electrodes 031 to 033 in the multilayer thin film, and the etching is stopped on the insulating dielectric layer 02. Therefore, three layers of horizontal conductive electrodes 031-033 in the horizontal direction are patterned and serve as one electrode terminal of the resistive random access memory.
Step S03: and processing the end part of the horizontal conductive electrode exposed on the side wall of the groove, and forming a gating material layer between the surface of the side wall of the groove and the horizontal conductive electrode.
Please refer to fig. 6. As an optional implementation mode, the end parts of the horizontal conductive electrodes 031-033 exposed on the side walls of the trench 11 are processed, and the method comprises the following steps:
and removing partial horizontal conductive electrodes 031-033 exposed on the side wall of the groove 11 by adopting a chemical etching or wet etching method, and forming an inwards concave structure 12 on the side wall of the groove 11.
In the embodiment, wet chemical liquid is adopted to transversely corrode Ti horizontal conductive electrodes 031-033 with the depth of 5nm, so as to form a transverse concave structure 12 with the depth of 5 nm.
Please refer to fig. 7. Then, a gate material layer 08 material is grown in the recessed structure 12 using an atomic layer deposition method.
And then, removing the gating material layer 08 material which also grows on the side walls (namely the side walls of the groove 11) of the isolation medium layers 041 to 042 by adopting a dry etching method, so that the isolation medium layers 041 to 042 are flush with the side wall surfaces of the gating material layer 08 material, and forming the gating material layer 08 embedded in the concave structure 12.
In this embodiment, a gate material of titanium oxide with a thickness of 10nm is deposited by using an atomic layer, and then the gate material growing on the sidewalls of the isolation dielectric layers 041 to 042 is removed by using dry etching to form a gate material layer 08 of titanium oxide embedded in the recessed structure 12, so that the exposed surface of the formed titanium oxide and the exposed surfaces of the isolation dielectric layers 041 to 042 are formed on the same plane in the vertical direction, and thus, the subsequent material of the resistive memory layer 09 can be deposited on a vertically flat surface, thereby avoiding electric leakage and improving the reliability of the memory device.
As other optional embodiments, the end portions of the horizontal conductive electrodes 031 to 033 exposed on the side walls of the trench 11 are processed, and the method may further include: and directly oxidizing the exposed end part titanium material of the horizontal conductive electrode in the concave structure into titanium oxide by adopting an oxidation mode to form a titanium oxide gating material layer.
Step S04: and forming a resistance change storage layer along the inner wall of the groove, and forming a vertical conductive electrode on the resistance change storage layer.
Please refer to fig. 8. Depositing a resistance change storage layer 09 material in the groove 11, and then continuously depositing a vertical conductive electrode 10 material on the resistance change storage layer 09 material to fill the groove 11.
Then, redundant materials of the resistive memory layer 09 and the vertical conductive electrode 10 on the surface of the structure are removed, and the U-shaped resistive memory layer 09 and the vertical conductive electrode 10 located in the U-shaped resistive memory layer 09 are formed.
The vertical conductive electrode 10 serves as the other electrode terminal of the resistance change memory.
In the embodiment, an ALD (atomic layer deposition) deposited hafnium oxide film is used as a material of the resistive memory layer 09; then, adopting PVD to deposit TaN as a vertical conductive electrode 10 material; and then, removing the redundant resistive random access memory layer 09 material and the vertical conductive electrode 10 material on the surface by adopting a CMP (chemical mechanical polishing) process.
Then, the horizontal conductive electrodes 031-033 and the vertical conductive electrodes 10 may be respectively connected to the corresponding interconnection lines formed, so that an operation electrical signal may be applied to the resistive random access memory, and the three-dimensional resistive random access memory may be manufactured.
In summary, in the three-dimensional resistive random access memory and the manufacturing method thereof provided by the invention, the gating materials are manufactured in the concave structure, so that the gating materials are mutually isolated, the surface of the resistive random access memory layer is flat, the leakage current in the three-dimensional resistive random access memory array is reduced, the reliability of the device is improved, the high-density three-dimensional resistive random access memory and the manufacturing method thereof are realized, and the cost is favorably reduced.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A three-dimensional resistive random access memory, comprising:
the device comprises a substrate, a plurality of layers of horizontal conductive electrodes formed on the substrate, and an isolation medium layer formed between the horizontal conductive electrodes; two resistive random access memory layers are vertically arranged between the horizontal conductive electrode and the isolation dielectric layer, vertical conductive electrodes connected with the resistive random access memory layers are arranged on the inner sides of the two resistive random access memory layers, the side walls of the resistive random access memory layers are connected with the end portions of the horizontal conductive electrodes through gating material layers arranged on the same layer as the horizontal conductive electrodes, and the isolation dielectric layer separates the gating material layers from top to bottom.
2. The three-dimensional resistive random access memory according to claim 1, wherein an insulating medium layer is arranged between the substrate and the multilayer horizontal conductive electrode.
3. The three-dimensional resistive random access memory according to claim 1, wherein a protective dielectric layer is arranged on the plurality of horizontal conductive electrodes, and the protective dielectric layer is separated by the resistive random access memory layer.
4. A manufacturing method of a three-dimensional resistive random access memory is characterized by comprising the following steps:
step S01: providing a substrate, and alternately forming a plurality of layers of horizontal conductive electrodes and isolation medium layers on the substrate;
step S02: forming a trench downwards to penetrate through the plurality of layers of horizontal conductive electrodes and the isolation dielectric layer;
step S03: processing the end part of the horizontal conductive electrode exposed on the side wall of the groove, and forming a gating material layer between the surface of the side wall of the groove and the horizontal conductive electrode;
step S04: and forming a resistance change storage layer along the inner wall of the groove, and forming a vertical conductive electrode on the resistance change storage layer.
5. The method for manufacturing the three-dimensional resistive random access memory according to claim 4, wherein the step S03 of processing the end portion of the horizontal conductive electrode exposed on the side wall of the trench includes: removing part of the horizontal conductive electrode material exposed on the side wall of the groove, forming a concave structure on the side wall of the groove, and then forming a gating material layer in the concave structure.
6. The manufacturing method of the three-dimensional resistive random access memory according to claim 5, wherein a chemical etching method or a wet etching method is adopted to remove a part of the horizontal conductive electrode material to form a concave structure.
7. The manufacturing method of the three-dimensional resistive random access memory according to claim 5, wherein a gating material is grown in the concave structure by adopting an atomic layer deposition method, and then the gating material on the side wall of the isolation medium layer is removed by adopting dry etching to form a gating material layer embedded in the concave structure.
8. The manufacturing method of the three-dimensional resistive random access memory according to claim 7, wherein when the gate material on the sidewall of the isolation dielectric layer is removed by dry etching, the isolation dielectric layer is aligned with the sidewall surface of the gate material layer.
9. The manufacturing method of the three-dimensional resistive random access memory according to claim 5, wherein an oxidation manner is adopted to oxidize the material at the end of the horizontal conductive electrode exposed in the concave structure to form an oxide layer of the horizontal conductive electrode material as the gate material layer.
10. The method for manufacturing the three-dimensional resistive random access memory according to claim 4, wherein the step S01 further comprises: before forming a plurality of horizontal conductive electrodes and isolation dielectric layers, an insulating dielectric layer is formed on the silicon substrate, and a protective dielectric layer is formed on the uppermost horizontal conductive electrode.
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| CN113421963A (en) * | 2021-06-10 | 2021-09-21 | 北京大学 | Low-power-consumption three-dimensional resistive random access memory |
| WO2021232780A1 (en) * | 2020-05-19 | 2021-11-25 | 上海集成电路研发中心有限公司 | Three-dimensional resistive random access memory and manufacturing method |
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| WO2017185326A1 (en) * | 2016-04-29 | 2017-11-02 | 中国科学院微电子研究所 | Self-gating resistive storage device and method for fabrication thereof |
| CN108987407A (en) * | 2018-07-12 | 2018-12-11 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
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| CN104485418A (en) * | 2014-12-26 | 2015-04-01 | 中国科学院微电子研究所 | Self-gating resistive random access memory unit and preparation method thereof |
| CN111564470A (en) * | 2020-05-19 | 2020-08-21 | 上海集成电路研发中心有限公司 | Three-dimensional resistive random access memory and manufacturing method thereof |
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| CN105826468A (en) * | 2016-04-29 | 2016-08-03 | 中国科学院微电子研究所 | Self-gating resistive random access memory device and preparation method thereof |
| WO2017185326A1 (en) * | 2016-04-29 | 2017-11-02 | 中国科学院微电子研究所 | Self-gating resistive storage device and method for fabrication thereof |
| CN110678987A (en) * | 2016-10-18 | 2020-01-10 | 美光科技公司 | Semiconductor device and method of manufacturing the same |
| CN108987407A (en) * | 2018-07-12 | 2018-12-11 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
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| WO2021232780A1 (en) * | 2020-05-19 | 2021-11-25 | 上海集成电路研发中心有限公司 | Three-dimensional resistive random access memory and manufacturing method |
| CN113421963A (en) * | 2021-06-10 | 2021-09-21 | 北京大学 | Low-power-consumption three-dimensional resistive random access memory |
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Effective date of registration: 20201209 Address after: No. 497, Gauss Road, Zhangjiang, Pudong New Area, Shanghai, 201210 Applicant after: SHANGHAI IC R & D CENTER Co.,Ltd. Applicant after: Shanghai IC equipment Material Industry Innovation Center Co.,Ltd. Address before: No. 497, Gauss Road, Zhangjiang, Pudong New Area, Shanghai, 201210 Applicant before: SHANGHAI IC R & D CENTER Co.,Ltd. |
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