CN113421963A - Low-power-consumption three-dimensional resistive random access memory - Google Patents
Low-power-consumption three-dimensional resistive random access memory Download PDFInfo
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- CN113421963A CN113421963A CN202110647502.3A CN202110647502A CN113421963A CN 113421963 A CN113421963 A CN 113421963A CN 202110647502 A CN202110647502 A CN 202110647502A CN 113421963 A CN113421963 A CN 113421963A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
- H10N70/8845—Carbon or carbides
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
Abstract
The invention discloses a low-power-consumption three-dimensional resistive random access memory, wherein a graphene barrier layer is inserted between an electrode of the resistive random access memory and a resistive film, the graphene barrier layer is a graphene film prepared by a chemical vapor deposition method, and a small number of nano defect holes exist in the graphene film. The graphene barrier layer can limit the movement of electrode metal to the resistance change layer, so that the metal can only pass through a small number of defect holes, and the growth of metal conductive filaments is limited. Therefore, the device can only form thinner and fewer metal conductive filaments in the data writing process, so that the data erasing current is greatly reduced in the data erasing process, and the power consumption of the resistive random access memory is obviously reduced.
Description
Technical Field
The invention belongs to the technical field of Non-volatile memories (Non-volatile memories) in semiconductors (semiconductors) and CMOS (complementary metal oxide semiconductor) ultra-large-scale integrated circuits (ULSI), and particularly relates to a device structure design of a low-power-consumption three-dimensional resistive access Memory (REST random access Memory).
Background
Memory is an important component of computer architecture for the storage of data. In recent decades, memory technology has been developed rapidly, and the performance of memory capacity, density, speed, etc. has been improved rapidly. Currently, the mainstream technology of the non-volatile memory is flash memory (flash), which has great advantages in storage speed compared with a mechanical hard disk, and thus, the non-volatile memory is widely applied to the fields of hard disks, u disks and the like. However, as the feature storage is continuously reduced to the nano-scale node, many irrational effects faced by flash are increasingly severe, which prevents further reduction of the size and makes it difficult to further increase the capacity. Therefore, in recent years, various new nonvolatile memories, such as a magnetic memory (MRAM), a phase change memory (PRAM), a ferroelectric memory (FeRAM), a resistance change memory (RRAM), and the like, have been widely noticed and researched. Among them, RRAM is a strong competitor of the next generation of non-volatile memory due to its advantages of simple structure, fast read/write speed, high integration, etc. The storage density is an important performance index of the memory, and the three-dimensional stacking is an important way for improving the storage density. However, the current 3D RRAM technology has many disadvantages to prevent its application, and one of the important problems is the high storage power consumption of the 3D RRAM. The defect limits the industrial application of the three-dimensional resistive random access memory, and particularly the application in the fields of wearable and the like with higher requirements on low power consumption. Therefore, reducing the storage power consumption of the 3D RRAM is of great significance for its industrial application. The present invention proposes a solution to this problem.
The metal conductive filament type RRAM is a very important type of RRAM, and has an ultra-high on-off ratio, and the writing and storing processes of data are completed by the growth and breakage of the metal conductive filament. Initially, the resistive layer is free of metal conductive filaments, and the device is in a high resistance state. When the voltage applied to the top electrode is larger than the writing voltage, the metal of the top electrode enters the resistance change layer under the action of the electric field, a metal conductive filament connected with the top electrode and the bottom electrode is formed in the resistance change layer, and the device is changed from a high resistance state to a low resistance state, so that the data writing process is realized. After that, when the negative voltage applied on the top electrode is larger than the erasing voltage, the metal conductive filament will be broken due to the action of joule heat and electric field, and the device is changed from the low resistance state to the high resistance state, so as to realize the erasing function of data. Since the metal conductive filament formed in the data writing process is often thicker, the metal conductive filament needs larger joule heat to break in the data erasing process, and thus larger power consumption is consumed. The present invention proposes a solution to this problem.
Disclosure of Invention
The invention provides a low-power-consumption three-dimensional resistive random access memory with a graphene barrier layer structure, which is expected to reduce the power consumption of the three-dimensional resistive random access memory.
Aiming at the problem that the metal conductive thin-wire type three-dimensional resistive random access memory is high in power consumption, the low-power-consumption three-dimensional resistive random access memory is prepared by inserting the graphene barrier layer between the electrode and the resistive film. Good graphene is prepared with excellent impermeability, and even the smallest gas molecules hydrogen and helium are difficult to pass through. However, the graphene thin film prepared by Chemical Vapor Deposition (CVD) has a small amount of nano-defect pores (pore diameter: about 10nm, density: 1/μm)2). The graphene barrier layer prepared by CVD can limit the movement of electrode metal to the resistance change layer, so that the metal can only pass through a small number of defect holes, and the growth of metal conductive filaments is limited. Therefore, the device can only form thinner and fewer metal conductive filaments in the data writing process, so that the metal conductive filaments can be broken only by less Joule heat in the data erasing process, and the purpose of reducing the power consumption of the device is achieved.
The technical scheme adopted by the invention is as follows:
a low-power-consumption three-dimensional resistive random access memory comprises a substrate, and a three-dimensional resistive random access memory and an isolation medium which are positioned on the substrate, wherein the number of layers of the three-dimensional resistive random access memory is more than or equal to 2; the three-dimensional resistive random access memory comprises a single device, a lower electrode, a resistive thin film, a graphene barrier layer and an upper electrode, or comprises the lower electrode, the graphene barrier layer, the resistive thin film and the upper electrode from bottom to top in sequence, namely the graphene barrier layer is positioned between the resistive thin film and the upper electrode or the lower electrode, and the graphene barrier layer is a graphene film prepared by a chemical vapor deposition method.
Further, the graphene barrier layer is prepared by a high-temperature low-pressure CVD method and is transferred to the sample by a wet method.
Preferably, the graphene barrier layer has a thickness of a monolayer to 20nm, wherein a small number of nano-defect pores present therein have a pore size of about 10nm and a density of about 1/μm2。
Alternatively, the upper and lower electrodes may be made of various metal materials, such as W, Pt, Au, Al, Cu, Ag, Ni, TiN, and the like. The thickness of the electrode is preferably 10 to 200 nm.
Alternatively, the resistive film can adopt transition metal oxide and other oxides, such as TaOx、HfOx、SiOxOr SrTiO3Etc.; organic materials such as parylene-C and the like may also be used. Preferably, the thickness of the resistive film is 5-50 nm.
Alternatively, the isolation medium can be SiO2、Si3N4Inorganic compounds such as AlN; organic materials such as parylene-C and the like may also be used.
Alternatively, the substrate can adopt Si and SiO2The substrate may be a hard substrate, or a flexible organic substrate such as parylene-C, PET, or a composite substrate composed of substrates of different materials.
According to the three-dimensional resistive random access memory provided by the invention, the graphene film prepared by the chemical vapor deposition method is inserted between the electrode and the resistive random access film, so that the data erasing current can be greatly reduced in the data erasing process, and the power consumption of the resistive random access memory is obviously reduced.
Drawings
Fig. 1 is a schematic structural diagram of a low-power-consumption three-dimensional resistive random access memory prepared according to an embodiment of the present invention.
FIG. 2 is a schematic structural diagram of a control sample.
Fig. 3 is a schematic structural diagram of a single device of the low-power-consumption three-dimensional resistive random access memory prepared according to the embodiment of the invention.
FIG. 4 is a schematic diagram of a single device structure of a control sample.
Fig. 5 is a schematic view of current-voltage (I-V) characteristics of the resistance change process of the Al/graphene/parylene-C/W device obtained by using a conventional DC Sweep method.
FIG. 6 is a schematic view of current-voltage (I-V) characteristics of a resistance change process of an Al/parylene-C/W device obtained by a conventional DC Sweep method.
FIG. 7 is a graph of data erase current versus statistics for Al/graphene/parylene-C/W devices and Al/parylene-C/W devices.
FIG. 8 is a graph of data erase power versus statistics for Al/graphene/parylene-C/W devices and Al/parylene-C/W devices.
Detailed Description
The invention is further described below with reference to the drawings and the specific embodiments.
The low-power-consumption three-dimensional resistive random access memory of the embodiment adopts an Al/graphene/parylene-C/W structure, the substrate is parylene-C/Si, and the number of layers is two, including: the multilayer thin film transistor comprises an upper electrode 1(Al), a graphene barrier layer 2(graphene), a resistive film 3(parylene-C), a lower electrode 4(W), an isolation medium 5, a flexible substrate 6(parylene-C) and a Si substrate 7, as shown in FIGS. 1 and 3. For comparison, the structure of the control sample is Al/parylene-C/W structure, the substrate is parylene-C/Si, the number of layers is two, and the graphene barrier layer 2(graphene) is reduced, as shown in FIG. 2 and FIG. 4.
The procedure for the preparation of the examples and the control samples was as follows:
1) preparing a 10 mu m flexible substrate 6 on a Si substrate 7 by polymer chemical vapor deposition (polymer CVD), wherein the material of the flexible substrate is parylene-C;
2) preparing a lower electrode 4 of a patterned 100nm first-layer device by photoetching, sputtering and stripping, wherein the material is W;
3) preparing a 100nm isolation medium 5 by polymer CVD and Chemical Mechanical Polishing (CMP), wherein the material is parylene-C;
4) preparing a 40nm resistance change film 3 by polymer CVD, wherein the material is parylene-C;
5) transferring a graphene film (with the thickness of about 10nm) prepared by high-temperature low-pressure CVD to the sample obtained in the step 3) by using a wet transfer technology to serve as a graphene barrier layer 2; the control sample did not have this step;
6) preparing an upper electrode 1 of a patterned 50nm first-layer device and a lower electrode 4 of a 50nm second-layer device through photoetching, sputtering and stripping, wherein the materials are Al and W respectively;
7) repeating the step 3 to the step 5;
8) preparing an electrode lead-out hole by photoetching and oxygen plasma etching;
9) preparing an upper electrode 1 of a patterned 100nm second-layer device by photoetching, sputtering and stripping, wherein the material is Al;
10) the 100nm isolation medium 5 was prepared by polymer CVD, Chemical Mechanical Polishing (CMP) and the material was parylene-C.
The current-voltage (I-V) characteristics of the Al/graphene/parylene-C/W device and the Al/parylene-C/W device of the comparison sample in the resistance change process are obtained by adopting a traditional DC Sweep mode, and are shown in FIGS. 5 and 6. Compared with a control sample, the current of the Al/graphene/parylene-C/W device is greatly reduced in the data erasing process. FIG. 7 is a graph of data erase current versus statistical results for Al/graphene/parylene-C/W devices and comparative sample Al/parylene-C/W devices, wherein the increase of the graphene barrier layer can reduce the data erase current by about 50 times. Fig. 8 is a comparison statistical result of data erasing power consumption of the Al/graphene/parylene-C/W device and the comparative sample Al/parylene-C/W device, and the increase of the graphene blocking layer can reduce the data erasing power consumption by about 15 times. The above results prove that the technical scheme of the invention can effectively reduce the power consumption of the resistive random access memory.
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person skilled in the art can modify the technical solution of the present invention or substitute the same without departing from the spirit and scope of the present invention, and the scope of the present invention should be determined by the claims.
Claims (9)
1. A low-power-consumption three-dimensional resistive random access memory comprises a substrate, and a three-dimensional resistive random access memory and an isolation medium which are positioned on the substrate, wherein the number of layers of the three-dimensional resistive random access memory is more than or equal to 2; the three-dimensional resistive random access memory is characterized in that a single device of the three-dimensional resistive random access memory sequentially comprises a lower electrode, a resistive film, a graphene barrier layer and an upper electrode from bottom to top, or comprises the lower electrode, the graphene barrier layer, the resistive film and the upper electrode, namely the graphene barrier layer is positioned between the resistive film and the upper electrode or the lower electrode, and the graphene barrier layer is a graphene film prepared by a chemical vapor deposition method.
2. The low-power-consumption three-dimensional resistive random access memory according to claim 1, wherein the graphene barrier layer is obtained by preparing a graphene thin film by a chemical vapor deposition method and transferring the graphene thin film to a sample by a wet transfer method.
3. The low-power-consumption three-dimensional resistive random access memory according to claim 1, wherein the graphene barrier layer has a thickness ranging from a single layer to 20 nm.
4. The low-power-consumption three-dimensional resistive random access memory according to claim 1, wherein the graphene blocking layer has nano-defect holes with a pore diameter of about 10nm and a density of about 1/μm2。
5. The low-power-consumption three-dimensional resistive random access memory according to claim 1, wherein the upper electrode and the lower electrode are made of one or more of the following materials: w, Pt, Au, Al, Cu, Ag, Ni and TiN.
6. The low-power-consumption three-dimensional resistive random access memory according to claim 1, wherein the upper electrode and the lower electrode have a thickness of 10-200 nm.
7. The low-power-consumption three-dimensional resistive random access memory according to claim 1, wherein the resistive random film is made of an oxide or an organic material.
8. The low-power-consumption three-dimensional resistive random access memory according to claim 1, wherein the resistive thin film has a thickness of 5-50 nm.
9. The low-power-consumption three-dimensional resistive random access memory according to claim 1, wherein the substrate is a hard substrate or a flexible organic substrate, or a composite substrate composed of substrates of different materials.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630719A (en) * | 2009-07-24 | 2010-01-20 | 北京大学 | Resistive random access memory and manufacturing method thereof |
| CN101976676A (en) * | 2010-09-13 | 2011-02-16 | 北京大学 | Three-dimensional nonvolatile memory array and preparation method thereof |
| CN102222512A (en) * | 2010-04-13 | 2011-10-19 | 北京大学 | Flexible organic resistive random access memory and manufacturing method thereof |
| CN102610755A (en) * | 2012-03-26 | 2012-07-25 | 北京大学 | Ultra-low-power organic resistance changing memory device and manufacturing method thereof |
| CN104810476A (en) * | 2015-05-07 | 2015-07-29 | 中国科学院微电子研究所 | Non-volatile resistive switching memory device and manufacturing method thereof |
| CN105990520A (en) * | 2015-02-05 | 2016-10-05 | 中国科学院微电子研究所 | Nonvolatile resistive random access memory device and preparation method thereof |
| CN105990519A (en) * | 2015-02-05 | 2016-10-05 | 中国科学院微电子研究所 | Nonvolatile resistive random access memory device and preparation method thereof |
| CN109494301A (en) * | 2018-10-30 | 2019-03-19 | 兰州大学 | A kind of method and its resistance-variable storing device improving resistance-variable storing device stability |
| CN111564470A (en) * | 2020-05-19 | 2020-08-21 | 上海集成电路研发中心有限公司 | Three-dimensional resistive random access memory and manufacturing method thereof |
-
2021
- 2021-06-10 CN CN202110647502.3A patent/CN113421963A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630719A (en) * | 2009-07-24 | 2010-01-20 | 北京大学 | Resistive random access memory and manufacturing method thereof |
| CN102222512A (en) * | 2010-04-13 | 2011-10-19 | 北京大学 | Flexible organic resistive random access memory and manufacturing method thereof |
| CN101976676A (en) * | 2010-09-13 | 2011-02-16 | 北京大学 | Three-dimensional nonvolatile memory array and preparation method thereof |
| CN102610755A (en) * | 2012-03-26 | 2012-07-25 | 北京大学 | Ultra-low-power organic resistance changing memory device and manufacturing method thereof |
| CN105990520A (en) * | 2015-02-05 | 2016-10-05 | 中国科学院微电子研究所 | Nonvolatile resistive random access memory device and preparation method thereof |
| CN105990519A (en) * | 2015-02-05 | 2016-10-05 | 中国科学院微电子研究所 | Nonvolatile resistive random access memory device and preparation method thereof |
| CN104810476A (en) * | 2015-05-07 | 2015-07-29 | 中国科学院微电子研究所 | Non-volatile resistive switching memory device and manufacturing method thereof |
| CN109494301A (en) * | 2018-10-30 | 2019-03-19 | 兰州大学 | A kind of method and its resistance-variable storing device improving resistance-variable storing device stability |
| CN111564470A (en) * | 2020-05-19 | 2020-08-21 | 上海集成电路研发中心有限公司 | Three-dimensional resistive random access memory and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| QINGYU CHEN等: "Low Power Parylene-Based Memristors with a Graphene Barrier Layer for Flexible Electronics Applications", 《ADVANCED ELECTRONIC MATERIALS》 * |
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