WO2021232780A1

WO2021232780A1 - Three-dimensional resistive random access memory and manufacturing method

Info

Publication number: WO2021232780A1
Application number: PCT/CN2020/138316
Authority: WO
Inventors: 左青云; 李铭
Original assignee: 上海集成电路研发中心有限公司; 上海集成电路装备材料产业创新中心有限公司
Priority date: 2020-05-19
Filing date: 2020-12-22
Publication date: 2021-11-25
Also published as: CN111564470A

Abstract

A three-dimensional resistive random access memory and a manufacturing method therefor. The three-dimensional resistive random access memory comprises: a plurality of layers of horizontal conductive electrodes (031, 032, 033) formed on a substrate (01), and isolating dielectric layers (041, 042) formed between layers of the horizontal conductive electrodes (031, 032, 033); and two resistance-variable storage layers (09), which run through the horizontal conductive electrodes (031, 032, 033) and the isolating dielectric layers (041, 042), and are vertical to the substrate (01), wherein inner sides of the two resistance-variable storage layers (09) are provided with vertical conductive electrodes (10) that are connected to the resistance-variable storage layers (09), side walls of the resistance-variable storage layers (09) and end parts of the horizontal conductive electrodes (031, 032, 033) are connected by means of gating material layers (08) that are arranged in the same layer as the horizontal conductive electrodes (031, 032, 033), and the gating material layers (08) are separated vertically by means of the isolating dielectric layers (041, 042). The three-dimensional resistive random access memory has a self-gating characteristic, can effectively improve storage density, is compatible with a CMOS process, and facilitates the popularization and application thereof.

Description

Three-dimensional resistive random access memory and manufacturing method

cross reference

This application claims the priority of the Chinese patent application with the application number 202010425143.2 filed on May 19, 2020. The content of the above application is included here by reference.

Technical field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a three-dimensional resistive random access memory and a manufacturing method.

Background technique

Resistive random access memory is a new type of memory suitable for low-power, low-cost applications, and can be integrated in three dimensions. Common three-dimensional integration methods include plane-stacked three-dimensional integration and vertical three-dimensional integration. Among them, the vertical three-dimensional integration method can achieve three-dimensional integration with fewer photomasks, so it has obvious advantages when integrating more layers. Due to the leakage channel crosstalk in the cross array, it is necessary to connect the resistive switching device and the gate device in series or prepare a self-selective resistive switching device with self-gating. For vertical three-dimensional integration, self-selective resistive switching devices with self-gating are the first choice.

Please refer to FIG. 1, which is a schematic diagram of a conventional three-dimensional resistive random access memory structure. As shown in FIG. 1, in the prior art, since the gate material layer 06 and the resistive memory layer 07 in the self-gate device are both erected, it is difficult to pattern them vertically. However, if the gate material layer 06 and the resistive memory layer 07 are not patterned, reliability problems will follow and affect the life of the storage device.

Summary of the invention

The purpose of the present invention is to overcome the above-mentioned shortcomings in the prior art, and provide a three-dimensional resistive random access memory and a manufacturing method to solve the current leakage and reliability problems of the existing self-selective RRAM in vertical three-dimensional integration, and to achieve high-density three-dimensional RRAM , To reduce the cost of memory per unit area.

In order to achieve the above objective, the technical solution of the present invention is as follows:

A three-dimensional resistive random access memory, including:

A multilayer horizontal conductive electrode formed on a substrate, and an isolation dielectric layer formed between the horizontal conductive electrodes of each layer; passing through the horizontal conductive electrode and the isolation dielectric layer and vertically disposed on two sides of the substrate A resistance-switching storage layer, the inside of the two resistance-switching storage layers are provided with vertical conductive electrodes connected to the resistance-switching storage layer, and the sidewalls of the resistance-switching storage layer pass between the end of the horizontal conductive electrode Connected to the gate material layer provided in the same layer as the horizontal conductive electrode, the isolation dielectric layer separates the gate material layer up and down, and the sidewall of the isolation dielectric layer connected to the resistive storage layer and The sidewalls of the gate material layer are flush.

Further, an insulating dielectric layer is provided between the substrate and the multi-layer horizontal conductive electrode.

Further, a protective medium layer is provided on the multilayer horizontal conductive electrode, and the protective medium layer is separated by the resistive storage layer.

A method for manufacturing a three-dimensional resistive random access memory includes the following steps:

Step S01: providing a substrate on which multiple horizontal conductive electrodes and isolation dielectric layers are alternately formed;

Step S02: forming a trench downward through the multi-layer horizontal conductive electrode and the isolation dielectric layer;

Step S03: processing the end of the horizontal conductive electrode exposed on the sidewall of the trench to form a gate material layer between the surface of the sidewall of the trench and the horizontal conductive electrode;

Step S04: forming a resistive memory layer along the inner wall of the trench, and forming a vertical conductive electrode on the resistive memory layer.

Further, in step S03, when the end of the horizontal conductive electrode exposed on the sidewall of the trench is processed, it includes: first removing a part of the horizontal conductive electrode exposed on the sidewall of the trench, and A concave structure is formed on the sidewall of the trench, and then a gate material layer is formed in the concave structure.

Further, a chemical etching or wet etching method is used to remove part of the horizontal conductive electrode to form a concave structure.

Further, an atomic layer deposition method is used to grow a gate material in the recessed structure and the sidewall of the isolation dielectric layer, and then dry etching is used to remove the gate located on the sidewall of the isolation dielectric layer Material to form a gate material layer embedded in the concave structure.

Further, when dry etching is used to remove the gate material located on the sidewall of the isolation dielectric layer, the surface of the isolation dielectric layer and the sidewall of the gate material layer are flush.

Further, an oxidation method is used to oxidize the end of the horizontal conductive electrode exposed in the concave structure to form an oxide layer of the horizontal conductive electrode material as the gate material layer.

Further, in step S01, it further includes: forming an insulating dielectric layer on the silicon substrate, and forming a protective dielectric layer on the uppermost horizontal conductive electrode before forming the multi-layer horizontal conductive electrode and the isolation dielectric layer.

It can be seen from the above technical solution that the present invention forms a concave structure on the sidewall of the trench by removing the end material of the horizontal conductive electrode, and fills the gate material in the concave structure, or directly removes the concave structure The end of the middle horizontal conductive electrode is oxidized, and the formed oxide layer is used as the gate material to realize the patterning of the gate material. At the same time, the sidewall of the isolation dielectric layer connected to the resistive memory layer and the selection The sidewalls of the pass material layer are flush, which realizes the flatness of the surface of the resistive storage layer formed on the sidewalls of the trench, avoids leakage, improves the reliability of the storage device, and finally realizes a high-density, high-reliability three-dimensional resistance Variable memory.

Description of the drawings

FIG. 1 is a schematic diagram of the structure of an existing three-dimensional resistive random access memory.

2 is a schematic diagram of a three-dimensional resistive random access memory structure according to a preferred embodiment of the present invention.

FIG. 3 is a schematic flowchart of a method for manufacturing a three-dimensional resistive random access memory according to a preferred embodiment of the present invention.

4 to 8 are schematic diagrams of process steps in manufacturing a three-dimensional resistive random access memory according to a preferred embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

It should be noted that in the following specific embodiments, when the embodiments of the present invention are described in detail, in order to clearly show the structure of the present invention for ease of description, the structure in the drawings is not drawn in accordance with the general scale. Partial enlargement, deformation, and simplification of processing have been implemented. Therefore, this should not be interpreted as a limitation of the present invention.

In the following specific embodiments of the present invention, please refer to FIG. 2, which is a schematic diagram of a three-dimensional resistive random access memory structure according to a preferred embodiment of the present invention. As shown in FIG. 2, a three-dimensional resistive random access memory of the present invention may include:

Silicon substrate 01;

Multi-layer horizontal conductive electrodes 031 to 033 formed on the silicon substrate 01, and isolation dielectric layers 041 to 042 formed between the horizontal conductive electrodes 031 to 033 of each layer.

In this embodiment, it is shown that three layers of horizontal conductive electrodes 031 to 033 are provided on the silicon substrate 01, and two isolation dielectric layers 041 to 042 are provided between the three layers of horizontal conductive electrodes 031 to 033.

In addition, an insulating dielectric layer 02 can also be provided between the silicon substrate 01 and the bottom horizontal conductive electrode 031 of the multilayer horizontal conductive electrodes 031 to 033. A protective dielectric layer 05 may also be provided on the conductive electrode 033.

Among them, one or more U-shaped resistive storage layers 09 (shown as two U-shaped resistive The variable memory layer 09), the resistive memory layer 09 penetrates the horizontal conductive electrodes 031 to 033 and the isolation dielectric layers 041 to 042 (including the protective dielectric layer 05) and is vertically arranged on the silicon substrate 01. The upper end of the U-shaped resistive storage layer 09 may be flush with the surface of the protective dielectric layer 05; the lower end of the U-shaped resistive storage layer 09 is located on the insulating dielectric layer 02.

Please refer to Figure 2. A vertical conductive electrode 10 is provided inside the U-shape of the resistive memory layer 09; the vertical conductive electrode 10 is connected to the inner side of the resistive memory layer 09. At the same time, a gate material layer 08 is provided between the outer sidewall of the resistive memory layer 09 and the ends of the horizontal conductive electrodes 031 to 033; the resistive memory layer 09, the gate material layer 08 and the horizontal conductive electrodes 031 to 033 are in sequence. connect. In addition, the gate material layer 08 is arranged in the same layer as the horizontal conductive electrodes 031 to 033, and the sidewalls of the isolation dielectric layer 041 to 042 connected to the resistive memory layer 09 and the sidewalls of the gate material layer 08 are flat. Therefore, the isolation dielectric layers 041 to 042 separate the gate material layer 08 up and down into three layers as shown in the figure, for example.

In fact, a resistive memory layer 09 is formed on the U-shaped vertical sides of the resistive memory layer 09, namely, each layer of horizontal conductive electrodes 031 to 033 and isolation dielectric layers 041 to 042 (including protective dielectric layer 05). ) Is separated by two resistive storage layers 09 vertically arranged.

In this embodiment, the lower ends of the two vertically arranged resistive memory layers 09 can be connected by the extension of their materials, thereby forming a U-shaped resistive memory layer 09. But it is not limited to this, and the lower ends of the two vertically arranged resistive storage layers 09 can also be disconnected.

In the following, a method for manufacturing a three-dimensional resistive random access memory of the present invention will be described in detail through specific implementations in conjunction with the accompanying drawings.

Please refer to FIG. 3 in conjunction with FIG. 4 to FIG. 8. FIG. 3 is a schematic flowchart of a method for manufacturing a three-dimensional resistive random access memory according to a preferred embodiment of the present invention, and FIGS. 4 to 8 are diagrams of a preferred embodiment of the present invention. A schematic diagram of the process steps in manufacturing a three-dimensional resistive random access memory. As shown in FIG. 3, a method for manufacturing a three-dimensional resistive random access memory of the present invention can be used to fabricate the above-mentioned three-dimensional resistive random access memory structure as shown in FIG. 2, and may include the following steps:

Step S01: Provide a substrate, and alternately form multiple horizontal conductive electrodes and isolation dielectric layers on the substrate.

Please refer to Figure 4. A silicon wafer substrate 01 can be used, and an insulating dielectric layer 02 is first deposited on the silicon substrate 01.

Then, on the insulating dielectric layer 02, the horizontal conductive electrodes 031 to 033 and the isolation dielectric layer 041 to 042 are sequentially deposited to form, for example, three layers of horizontal conductive electrodes 031 to 033 and two isolation dielectric layers 041 to 042, three layers The horizontal conductive electrodes 031 to 033 are separated from each other by isolation dielectric layers 041 to 042. Finally, another protective dielectric layer 05 is deposited on the third layer of horizontal conductive electrode 033.

The substrate 01 may be a silicon wafer on which the required processing circuit manufacturing has been completed, and then the resistive random access memory manufacturing is started on it.

In this embodiment, a 12-inch silicon wafer can be used as the substrate 01, and 800-1200 angstroms, for example, 1000 angstroms of silicon dioxide can be deposited on the silicon wafer substrate 01 as the insulating dielectric layer 02.

Then, alternately deposit the horizontal conductive electrodes 031 to 033 material and the isolation dielectric layer 041 to 042 material.

In this embodiment, 200-400 angstroms, such as 300 angstroms, of Ti can be deposited as the horizontal conductive electrode 031-033 material, and 400-600 angstroms, such as 500 angstroms of silicon dioxide can be deposited as the isolation dielectric layer 041～042. Material. Finally, 900-1100 angstroms, for example 1000 angstroms of silicon dioxide can be deposited as the protective dielectric layer 05 to form three layers of horizontal conductive electrodes 031 to 033 that are isolated from each other in the horizontal direction.

Step S02: forming a trench that penetrates the multilayer horizontal conductive electrodes and the isolation dielectric layer downward.

Please refer to Figure 5. Photolithography and etching processes can be used to etch the three layers of horizontal conductive electrodes 031 to 033, and the trenches 11 are formed in the three layers of horizontal conductive electrodes 031 to 033.

In this embodiment, dry etching is used to etch the protective dielectric layer 05, the isolation dielectric layers 041 to 042, and the horizontal conductive electrodes 031 to 033 in the multilayer film, and stop on the insulating dielectric layer 02. As a result, three layers of horizontal conductive electrodes 031 to 033 in the horizontal direction are patterned and used as one of the electrode terminals of the resistive random access memory.

Step S03: processing the end of the horizontal conductive electrode exposed on the sidewall of the trench to form a gate material layer between the surface of the sidewall of the trench and the horizontal conductive electrode.

Please refer to Figure 6. As an optional implementation manner, processing the ends of the horizontal conductive electrodes 031 to 033 exposed on the sidewall of the trench 11 may include:

A chemical etching or wet etching method is used to remove part of the horizontal conductive electrodes 031 to 033 exposed on the sidewall of the trench 11 to form a concave structure 12 on the sidewall of the trench 11.

In this embodiment, a wet chemical solution is used to laterally etch Ti horizontal conductive electrodes 031 to 033 with a depth of 5 nm to form a concave structure 12 with a depth of 5 nm in the lateral direction.

Please refer to Figure 7. Then, an atomic layer deposition method is used to grow the gate material layer 08 in the concave structure 12 and the sidewalls of the isolation dielectric layers 041 to 042.

Next, a dry etching method is used to remove the gate material layer 08 that has also grown on the sidewalls of the isolation dielectric layers 041 to 042 (that is, the sidewalls of the trench 11), so that the isolation dielectric layers 041 to 042 are connected to the gate The sidewall surfaces of the material layer 08 are flush, forming a gate material layer 08 embedded in the concave structure 12.

In this embodiment, an atomic layer is used to deposit 10nm titanium oxide gate material, and then dry etching is used to remove the gate material grown on the sidewalls of the isolation dielectric layer 041 to 042 to form a recessed structure 12 embedded in it. In the titanium oxide gate material layer 08, the exposed surface of the formed titanium oxide and the exposed surface of the isolation dielectric layer 041～042 are formed on the same plane in the vertical direction, so that the material of the subsequent resistive memory layer 09 can be It is deposited on a vertical flat surface to avoid leakage and improve the reliability of the storage device.

As another optional implementation manner, the ends of the horizontal conductive electrodes 031 to 033 exposed on the sidewalls of the trench 11 are processed, and the method may further include: oxidizing the exposed ends of the horizontal conductive electrodes in the concave structure The titanium material in the part is directly oxidized to titanium oxide to form a titanium oxide gate material layer, and an oxide layer of the horizontal conductive electrode material is formed by directly oxidizing the exposed end part of the horizontal conductive electrode in the concave structure as the gate transparent material. Material layer. The gate material layer formed by this method is only formed at the exposed end of the horizontal conductive electrode in the concave structure.

Please refer to Figure 8. Deposit the resistive memory layer 09 material in the trench 11, and then continue to deposit the vertical conductive electrode 10 material on the resistive memory layer 09 material to fill the trench 11 up.

Then, the excess resistive memory layer 09 material and the material of the vertical conductive electrode 10 on the surface of the resistive random access memory are removed to form a U-shaped resistive memory layer 09 and the vertical conductive inside the U-shape of the resistive memory layer 09极10。 Electrode 10.

The vertical conductive electrode 10 serves as another electrode terminal of the resistive random access memory.

In this embodiment, ALD is used to deposit a hafnium oxide film as the resistive memory layer 09 material; then PVD is used to deposit TaN as the material for the vertical conductive electrode 10; then the CMP process is used to remove the excess resistive memory layer on the surface of the resistive memory 09 material and vertical conductive electrode 10 material.

After that, the horizontal conductive electrodes 031 to 033 and the vertical conductive electrodes 10 can be respectively connected to the corresponding interconnection lines formed, so that operating electrical signals can be applied to the resistive random access memory to complete the manufacturing of the three-dimensional resistive random access memory.

In summary, in the above-mentioned three-dimensional resistive random access memory and manufacturing method provided by the present invention, the gate material is fabricated in a concave structure, so that the gate materials are isolated from each other, and the surface of the resistive memory layer is flattened, reducing the three-dimensional The leakage current in the resistive random access memory array improves the reliability of the device, realizes a high-density three-dimensional resistive random access memory and its manufacturing, and is beneficial to reducing costs.

The above are only the preferred embodiments of the present invention, and the described embodiments are not intended to limit the scope of protection of the present invention. Therefore, any equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the same reasoning. Within the protection scope of the present invention.

Claims

A three-dimensional resistive random access memory, which is characterized in that it comprises:

A multilayer horizontal conductive electrode formed on a substrate, and an isolation dielectric layer formed between each layer of horizontal conductive electrodes; two resistive transformers that penetrate the horizontal conductive electrode and the isolation dielectric layer and are perpendicular to the substrate Storage layer, the inner sides of the two resistive storage layers are provided with vertical conductive electrodes connecting the resistive storage layers, and the sidewalls of the resistive storage layers and the ends of the horizontal conductive electrodes pass through with the The horizontal conductive electrode is connected to the gate material layer arranged in the same layer, the isolation dielectric layer separates the gate material layer from top to bottom, and the sidewall of the isolation dielectric layer connected to the resistive memory layer and the selection The sidewalls of the pass material layer are flush.
The three-dimensional resistive random access memory according to claim 1, wherein an insulating dielectric layer is provided between the substrate and the multi-layer horizontal conductive electrode.
The three-dimensional resistive random access memory according to claim 1, wherein a protective dielectric layer is provided on the multi-layer horizontal conductive electrode, and the protective dielectric layer is separated by the resistive random access memory layer.
A method for manufacturing a three-dimensional resistive random access memory is characterized in that it comprises the following steps:

Step S01: Provide a substrate, and alternately form multiple horizontal conductive electrodes and isolation dielectric layers on the substrate;

Step S02: forming a trench downward through the multi-layer horizontal conductive electrode and the isolation dielectric layer;

Step S03: processing the end of the horizontal conductive electrode exposed on the sidewall of the trench to form a gate material layer between the surface of the sidewall of the trench and the horizontal conductive electrode;

Step S04: forming a resistive memory layer along the inner wall of the trench, and forming a vertical conductive electrode on the resistive memory layer.
The method for manufacturing a three-dimensional resistive random access memory according to claim 4, wherein in step S03, when processing the end of the horizontal conductive electrode exposed on the sidewall of the trench, it comprises: first removing the A portion of the horizontal conductive electrode exposed on the sidewall of the trench is formed with a recessed structure on the sidewall of the trench, and then a gate material layer is formed in the recessed structure.
The method for manufacturing a three-dimensional resistive random access memory according to claim 5, wherein a chemical etching or wet etching method is used to remove part of the horizontal conductive electrodes to form a concave structure.
The method for manufacturing a three-dimensional resistive random access memory according to claim 5, wherein an atomic layer deposition method is used to grow a gate material in the recessed structure and the sidewall of the isolation dielectric layer, and then a dry method is used. The gate material on the sidewall of the isolation dielectric layer is removed by etching to form a gate material layer embedded in the concave structure.
The method for manufacturing a three-dimensional resistive random access memory according to claim 7, wherein when dry etching is used to remove the gate material located on the sidewall of the isolation dielectric layer, the isolation dielectric layer and the gate The sidewall surfaces of the material layer are flush.
The method for manufacturing a three-dimensional resistive random access memory according to claim 5, wherein an oxidation method is used to oxidize the end of the horizontal conductive electrode exposed in the concave structure to form an oxide layer of the horizontal conductive electrode material , As the gate material layer.
The method for manufacturing a three-dimensional resistive random access memory according to claim 4, wherein in step S01, it further comprises: forming an insulating dielectric layer on the silicon substrate before forming a multilayer horizontal conductive electrode and an isolation dielectric layer, And a protective dielectric layer is formed on the uppermost horizontal conductive electrode.