CN111508951B - GGNMOS ESD protection device structure based on SOI technology - Google Patents

GGNMOS ESD protection device structure based on SOI technology Download PDF

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CN111508951B
CN111508951B CN202010339956.XA CN202010339956A CN111508951B CN 111508951 B CN111508951 B CN 111508951B CN 202010339956 A CN202010339956 A CN 202010339956A CN 111508951 B CN111508951 B CN 111508951B
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type doped
doped source
source drain
drain
polycrystalline grid
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CN111508951A (en
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顾祥
张庆东
纪旭明
郑重
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a GGNMOS ESD protection device structure based on an SOI process, which comprises an SAB layer, a P-type doped source drain SP, an N-type doped source drain SN, a polycrystalline grid POLY, a device active region TO and a contact hole W1, wherein the P-type doped source drain of a strip NMOS tube is segmented, the body contact of the device is designed between every two sections of the P-type doped source drain, the P-type doped source drain of the strip NMOS tube is segmented, the body contact of the device is designed between every two sections of the P-type doped source drain, the structure skillfully segments the N-type doped source drain of the strip NMOS tube, the segmentation respectively defines the ranges of the SN injection layer and the SP injection layer, and the process is realized through photoetching, so that the area is saved on one hand, and the body contact is more sufficient on the other hand; through TLP test evaluation, the ESD resistance of the device is obviously improved by more than 1.2 times compared with that of the traditional SOI GGNMOS device in the same area.

Description

GGNMOS ESD protection device structure based on SOI technology
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a GGNMOS ESD protection device structure based on an SOI process.
Background
ESD protection technology has been the focus of research in the field of microelectronics. Statistically, failures due to ESD are more than 37% of the failures in integrated circuits, and this ratio is increasing further as device feature sizes shrink.
The high speed, low leakage, good subthreshold characteristics, latch-up immunity and its low soft error rate provided by SOI technology have become one of the most competitive technologies in widespread use. Because the bottom of the SOI device is isolated by the thick buried oxide layer, the periphery of the device is also isolated by SiO2 through all media, and the SOI device is very sensitive to ESD stress on the one hand; on the other hand, compared with a bulk silicon device, the difficulty of applying the SOI MOS device to ESD design is also higher, because a trigger mechanism of the NMOS device is more complicated due to a body region existing in the SOI MOS device, and due to structural limitations, many structures which can be used for ESD protection in the bulk silicon technology, such as a thick field oxide device, a vertical PN junction, and the like, cannot be used in an SOI circuit. Therefore, ESD design of SOI circuits is a significant challenge of concern.
Disclosure of Invention
The invention aims to provide a GGNMOS ESD protection device structure based on an SOI process, so as to solve the problems that the failure caused by ESD in the prior art accounts for more than 37% of the failure of an integrated circuit, and the proportion is further increased along with the reduction of the characteristic size of the device.
In order to achieve the purpose, the invention provides the following technical scheme: a GGNMOS ESD protection device structure based on an SOI process comprises an SAB layer, a P-type doped source drain SP, an N-type doped source drain SN, a polycrystalline grid POLY, a device active region TO and a contact hole W1, wherein the P-type doped source drain of a strip NMOS tube is segmented, and the body contact of the device is designed between every two sections of the P-type doped source drain.
Preferably, the P-type doped source drain SP is H-type, N-type doped source drain SN is injected into the inner side of the P-type doped source drain SP, a polycrystalline grid POLY is injected between the two N-type doped source drain SNs, the polycrystalline grid POLY is N-type, an annular SAB layer is injected into the polycrystalline grid POLY, a device active region TO is injected into the P-type doped source drain SP, and contact holes W1 are formed in the N-type doped source drain SN positioned on the inner side of the SAB layer, the N-type doped source drain SN positioned on the outer side of the polycrystalline grid POLY and the P-type doped source drain SP.
Preferably, the SAB layer is used for removing metal silicide on the silicon surface and improving the source-drain resistance.
Preferably, the contact holes W1 are opened in 5 groups, and each group includes 3 contact holes.
Preferably, the distance from the side edge of the contact hole W1 positioned on the inner side of the SAB layer TO the inner side and the upper end side wall of the polycrystalline grid POLY is 3um, the distance from the contact hole W1 TO the inner side of the SAB layer is 0.25um, the distance from the side edge of the contact hole W1 positioned on the outer side of the N-type doped source drain SN positioned on the outer side of the polycrystalline grid POLY TO the outer side of the polycrystalline grid POLY is 0.5um, the distance between the two N-type doped source drain SNs is 0.38um, and the distance from the bottom of the N-type doped source drain SN TO the top of the device active region TO is 60 um.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the P-type doped source and drain of the strip-shaped NMOS tube are segmented, and the body contact of the device is designed between every two segments of P-type doped source and drain, so that the area is saved on one hand, and the body contact is more sufficient on the other hand; through TLP test evaluation, the ESD resistance of the device is obviously improved by more than 1.2 times compared with that of the traditional SOI GGNMOS device under the same area, and the specific conditions are shown in the following table and the figure.
Drawings
FIG. 1 is a top view of an embodiment of the present invention;
FIG. 2 is a schematic side view of an embodiment of the present invention;
FIG. 3 is an equivalent structure diagram of GGNMOS of the present invention;
FIG. 4 is a diagram illustrating the effect of a TLP test in the prior art;
FIG. 5 is a diagram illustrating the TLP test effect of the present invention.
In the figure: 1. p-type doped source drain SP; 2. a device active area TO; 3. n-type doped source drain SN; 4. a POLY-gate POLY; 5. a SAB layer; 6. and contacts hole W1.
Detailed Description
In order to solve the problem that the failure caused by ESD accounts for more than 37% of the failures of integrated circuits, and the proportion is further increased along with the reduction of the characteristic size of devices, a GGNMOS ESD protection device structure based on an SOI process is particularly provided. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring TO fig. 1, the present embodiment provides a GGNMOS ESD protection device structure based on an SOI process, including an SAB layer 5, a P-type doped source/drain SP1, an N-type doped source/drain SN3, a POLY gate POLY4, a device active region TO2, and a contact hole W16, where the P-type doped source/drain of a strip NMOS transistor is segmented, and a body contact of the device is designed between each two P-type doped source/drain.
The P-type doped source-drain SP1 is H-shaped, N-type doped source-drain SN3 is injected into the inner side of the P-type doped source-drain SP1, a polycrystalline grid POLY4 is injected between the two N-type doped source-drain SN3, the polycrystalline grid POLY4 is N-shaped, an annular SAB layer 5 is injected into the polycrystalline grid POLY4, a device active region TO2 is injected into the P-type doped source-drain SP1, the N-type doped source-drain SN3 positioned on the inner side of the SAB layer 5, the N-type doped source-drain SN3 positioned on the outer side of the polycrystalline grid POLY4 and the P-type doped source-drain SP1 are provided with contact holes W16, and the N-type doped source-drain SN3 positioned on the outer side of the gate POLY4 and the contact holes W1 positioned on the P-type doped source-drain SP1 are both opened on the side close TO the closed end of the POLY 4.
The contact holes W16 are provided with 5 groups, and each group is provided with 3.
The distance a from the side edge of the contact hole W16 positioned on the inner side of the SAB layer 5 TO the inner side and the upper end side wall of the polycrystalline grid POLY4 is 3um, the distance b from the contact hole W16 TO the inner side of the SAB layer 5 is 0.25um, the distance c from the side edge of the contact hole W16 positioned inside the N-type doped source drain SN3 positioned on the outer side of the polycrystalline grid POLY4 TO the outer side of the polycrystalline grid POLY4 is 0.5um, the distance d between the two N-type doped source drain SN3 is 0.38um, and the distance e from the bottom of the N-type doped source drain SN3 TO the top of the device active region TO2 is 60 um.
The SAB layer 5 is used for removing metal silicide on the surface of the silicon and improving the source-drain resistance; SP: p-type source-drain doping is used for body contact of the device; SN: and doping the N-type source and drain to form a device source and drain.
The invention mainly designs aiming at the layout structure of an ESD protection device, the P-type doped source and drain of a strip-type NMOS tube are segmented, the body contact of the device is designed between every two segments of P-type doped source and drain, the structure skillfully segments the N-type doped source and drain of the strip-type NMOS tube, the segmentation respectively defines the range of SN and SP injection layers, and the design is realized by photoetching on the process, so that the area is saved on one hand, and the body contact is more sufficient on the other hand; through TLP test evaluation, the ESD resistance of the device is obviously improved by more than 1.2 times compared with that of the traditional SOI GGNMOS device in the same area.
Effect comparison table:
structure of the product W(um) Vt1(V) Vhold(V) Vt2(V) It2(A) ESD(V)
Conventional structure 300 8 5.5 9.5 1.4 2100
Novel structure 300 8 5.5 8.5 1.9 2800
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (4)

1. The utility model provides a GGNMOS ESD protection device structure based on SOI technology, includes SAB layer (5), P type doping source drain SP (1), N type doping source drain SN (3), polycrystal gate POLY (4), device active area TO (2), contact hole W1(6), its characterized in that: segmenting the P-type doped source and drain of the strip NMOS tube, wherein the body contact of the device is designed between each two segments of P-type doped source and drain; the P-type doped source drain SP (1) is H-shaped, N-type doped source drain SN (3) is injected into the inner side of the P-type doped source drain SP (1), a polycrystalline grid POLY (4) is injected between the two N-type doped source drain SN (3), the polycrystalline grid POLY (4) is N-shaped, an annular SAB layer (5) is injected into the polycrystalline grid POLY (4), a device active area TO (2) is injected into the P-type doped source drain SP (1), the N-type doped source drain SN (3) positioned on the inner side of the SAB layer (5), the N-type doped source drain SN (3) positioned on the outer side of the polycrystalline grid POLY (4) and the P-type doped source drain SP (1) are provided with contact holes W1 (6).
2. The GGNMOS ESD protection device structure based on SOI process of claim 1, wherein: the SAB layer (5) is used for removing metal silicide on the silicon surface and improving the source-drain resistance.
3. The structure of the GGNMOS ESD protection device based on the SOI process of claim 1, wherein: and 5 groups of the contact holes W1(6) are formed, and each group is provided with 3 contact holes.
4. The GGNMOS ESD protection device structure based on SOI process of claim 1, wherein: the distance from the side edge of the contact hole W1(6) on the inner side of the SAB layer (5) TO the inner side and the upper end side wall of the polycrystalline grid POLY (4) is 3um, the distance from the contact hole W1(6) TO the inner side of the SAB layer (5) is 0.25um, the distance from the side edge of the contact hole W1(6) inside the N-type doped source drain SN (3) on the outer side of the polycrystalline grid POLY (4) TO the outer side of the polycrystalline grid POLY (4) is 0.5um, the distance between the two N-type doped source drain SNs (3) is 0.38um, and the distance from the bottom of the N-type doped source drain SN (3) TO the top of the device active region TO (2) is 60 um.
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CN113192987B (en) * 2021-04-27 2023-11-03 上海华虹宏力半导体制造有限公司 SOI body contact device structure and forming method thereof
CN113345866B (en) * 2021-05-31 2022-08-02 中国电子科技集团公司第五十八研究所 GGNMOS ESD protection device structure based on anti-radiation SOI technology

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CN103996679A (en) * 2014-06-12 2014-08-20 上海华力微电子有限公司 SOI NMOS ESD device and preparing method thereof
CN109216343A (en) * 2017-07-03 2019-01-15 无锡华润上华科技有限公司 Semiconductor device and its domain structure with electrostatic discharge protection structure

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US20060284256A1 (en) * 2005-06-17 2006-12-21 Taiwan Semiconductor Manufacturing Co. Layout structure for ESD protection circuits
CN107785362B (en) * 2016-08-29 2021-04-13 无锡华润上华科技有限公司 Layout structure for improving electrostatic discharge protection capability

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Publication number Priority date Publication date Assignee Title
CN103996679A (en) * 2014-06-12 2014-08-20 上海华力微电子有限公司 SOI NMOS ESD device and preparing method thereof
CN109216343A (en) * 2017-07-03 2019-01-15 无锡华润上华科技有限公司 Semiconductor device and its domain structure with electrostatic discharge protection structure

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