CN111508951A - GGNMOS ESD protection device structure based on SOI technology - Google Patents
GGNMOS ESD protection device structure based on SOI technology Download PDFInfo
- Publication number
- CN111508951A CN111508951A CN202010339956.XA CN202010339956A CN111508951A CN 111508951 A CN111508951 A CN 111508951A CN 202010339956 A CN202010339956 A CN 202010339956A CN 111508951 A CN111508951 A CN 111508951A
- Authority
- CN
- China
- Prior art keywords
- drain
- type doped
- doped source
- esd protection
- protection device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005516 engineering process Methods 0.000 title description 6
- 238000000034 method Methods 0.000 claims abstract description 13
- 230000008569 process Effects 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 5
- 238000012360 testing method Methods 0.000 abstract description 5
- 238000011156 evaluation Methods 0.000 abstract description 3
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a GGNMOS ESD protection device structure based on an SOI process, which comprises an SAB layer, P-type doped source-drain SP, N-type doped source-drain SN, a polycrystalline grid PO L Y, a device active region TO and a contact hole W1, wherein the P-type doped source-drain of a strip-type NMOS tube is segmented, the body contact of the device is designed between every two sections of P-type doped source-drain, the P-type doped source-drain of the strip-type NMOS tube is segmented, the body contact of the device is designed between every two sections of P-type doped source-drain, the structure skillfully segments the N-type doped source-drain of the strip-type NMOS tube, the segments define ranges for SN and SP injection layers respectively, the design is realized through photoetching in the process, on one hand, the body contact is more sufficient, and through T L P test evaluation, the ESD resistance of the same area is obviously improved by more than 1.2 times compared with the traditional SOI GGNMOS device.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a GGNMOS ESD protection device structure based on an SOI process.
Background
ESD protection technology has been the focus of research in the field of microelectronics. Statistically, failures due to ESD are more than 37% of the failures in integrated circuits, and this ratio is increasing further as device feature sizes shrink.
The high speed, low leakage, good subthreshold characteristics, latch-up immunity and its low soft error rate provided by SOI technology have become one of the most competitive technologies in widespread use. Because the bottom of the SOI device is isolated by the thick buried oxide layer, the periphery of the device is also isolated by SiO2 through all media, and the SOI device is very sensitive to ESD stress on the one hand; on the other hand, compared with a bulk silicon device, the difficulty of applying the SOI MOS device to ESD design is also higher, because a trigger mechanism of the NMOS device is more complicated due to a body region existing in the SOI MOS device, and due to structural limitations, many structures which can be used for ESD protection in the bulk silicon technology, such as a thick field oxide device, a vertical PN junction, and the like, cannot be used in an SOI circuit. Therefore, ESD design of SOI circuits is a significant challenge of concern.
Disclosure of Invention
The invention aims to provide a GGNMOS ESD protection device structure based on an SOI process, so as to solve the problems that the failure caused by ESD in the prior art accounts for more than 37% of the failure of an integrated circuit, and the proportion is further increased along with the reduction of the characteristic size of the device.
In order TO achieve the purpose, the invention provides the following technical scheme that the GGNMOS ESD protection device structure based on the SOI process comprises an SAB layer, a P-type doped source drain SP, an N-type doped source drain SN, a polycrystalline grid PO L Y, a device active region TO and a contact hole W1, wherein the P-type doped source drain of a strip-shaped NMOS tube is segmented, and the body contact of the device is designed between every two segments of the P-type doped source drain.
Preferably, the P-type doped source drain SP is H-shaped, N-type doped source drain SNs are injected into the inner side of the P-type doped source drain SP, a polycrystalline grid PO L Y is injected between the two N-type doped source drain SNs, the polycrystalline grid PO L Y is N-shaped, an annular SAB layer is injected into the polycrystalline grid PO L Y, an active device region TO is injected onto the P-type doped source drain SP, and contact holes W1 are formed in the N-type doped source drain SNs positioned on the inner side of the SAB layer, the N-type doped source drain SNs positioned on the outer side of the polycrystalline grid PO L Y, and the P-type doped source drain SP.
Preferably, the SAB layer is used for removing metal silicide on the silicon surface and improving the source-drain resistance.
Preferably, the contact holes W1 are opened in 5 groups, and each group includes 3 contact holes.
Preferably, the distance from the side edge of the contact hole W1 positioned on the inner side of the SAB layer TO the inner side and the upper end side wall of the polycrystalline grid PO L Y is 3um, the distance from the contact hole W1 TO the inner side of the SAB layer is 0.25um, the distance from the side edge of the contact hole W1 positioned inside the N-type doped source drain SN positioned on the outer side of the polycrystalline grid PO L Y TO the outer side of the polycrystalline grid PO L Y is 0.5um, the distance between the two N-type doped source drain SNs is 0.38um, and the distance from the bottom of the N-type doped source drain SN TO the top of the device active region TO is 60 um.
Compared with the prior art, the invention has the beneficial effects that:
the P-type doped source and drain of the strip-type NMOS tube are segmented, the body contact of the device is designed between every two segments of P-type doped source and drain, on one hand, the area is saved, on the other hand, the body contact is more sufficient, through T L P test evaluation, the ESD resistance of the device is obviously improved by more than 1.2 times compared with that of the traditional SOI GGNMOS device under the same area, and the specific conditions are shown in the following table and figure.
Drawings
FIG. 1 is a top view of an embodiment of the present invention;
FIG. 2 is a schematic side view of an embodiment of the present invention;
FIG. 3 is a GGNMOS equivalent structure diagram of the present invention;
FIG. 4 is a graph illustrating the effect of the prior art T L P test;
FIG. 5 is a graph showing the effect of the T L P test according to the present invention.
In the figure, 1, P-type doped source drain SP, 2, a device active region TO, 3, N-type doped source drain SN, 4, a polycrystalline grid PO L Y, 5, an SAB layer and 6 are in contact holes W1.
Detailed Description
In order to solve the problem that the failure caused by ESD accounts for more than 37% of the failure of an integrated circuit, and the proportion is further increased along with the reduction of the characteristic size of a device, a GGNMOS ESD protection device structure based on an SOI process is particularly provided. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring TO fig. 1, the present embodiment provides a GGNMOS ESD protection device structure based on an SOI process, including an SAB layer 5, a P-type doped source/drain SP1, an N-type doped source/drain SN3, a poly gate PO L Y4, a device active region TO2, and a contact hole W16, where the P-type doped source/drain of a strip NMOS transistor is segmented, and a body contact of the device is designed between each two P-type doped source/drain.
The P-type doped source drain SP1 is H-shaped, N-type doped source drain SN3 is injected into the inner side of the P-type doped source drain SP1, a polycrystalline grid PO L Y4 is injected between the two N-type doped source drain SN3, the polycrystalline grid PO L Y4 is N-shaped, an annular SAB layer 5 is injected into the polycrystalline grid PO L Y4, a device active region TO2 is injected on the P-type doped source drain SP1, contact holes W16 are formed in the N-type doped source drain SN3 positioned inside the SAB layer 5, the N-type doped source drain SN3 positioned outside the polycrystalline grid PO L Y4 and the P-type doped source drain SP1, and contact holes W1 on the N-type doped source drain SN3 positioned outside the polycrystalline grid PO L Y4 and the P-type doped source drain SP1 are arranged on one side close TO the closed end of the PO L Y4.
The contact holes W16 are provided with 5 groups, and each group is provided with 3.
The distance a from the side edge of the contact hole W16 positioned on the inner side of the SAB layer 5 TO the inner side and the upper end side wall of the polycrystalline grid PO L Y4 is 3um, the distance b from the contact hole W16 TO the inner side of the SAB layer 5 is 0.25um, the distance c from the side edge of the contact hole W16 positioned inside the N-type doped source drain SN3 positioned on the outer side of the polycrystalline grid PO L Y4 TO the outer side of the polycrystalline grid PO L Y4 is 0.5um, the distance d between the two N-type doped source drain SN3 is 0.38um, and the distance e from the bottom of the N-type doped source drain SN3 TO the top of the device active region TO2 is 60 um.
The SAB layer 5 is used for removing metal silicide on the surface of the silicon and improving the source-drain resistance; SP: p-type source-drain doping is used for body contact of the device; SN: and doping the N-type source and drain to form a device source and drain.
The invention mainly designs a layout structure of an ESD protection device, a P-type doped source drain of a strip-type NMOS tube is segmented, the body contact of the device is designed between every two segments of P-type doped source drain, the structure skillfully segments the N-type doped source drain of the strip-type NMOS tube, the segmentation respectively defines ranges for SN and SP injection layers, and the segmentation is realized by photoetching in the process, so that the design saves the area on one hand, and makes the body contact more sufficient on the other hand, and the ESD resistance of the device is obviously improved by more than 1.2 times compared with the traditional SOI GGNMOS device under the same area through T L P test and evaluation.
Effect comparison table:
| structure of the product | W(um) | Vt1(V) | Vhold(V) | Vt2(V) | It2(A) | ESD(V) |
| Conventional structure | 300 | 8 | 5.5 | 9.5 | 1.4 | 2100 |
| Novel structure | 300 | 8 | 5.5 | 8.5 | 1.9 | 2800 |
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. A GGNMOS ESD protection device structure based on an SOI process comprises an SAB layer (5), P-type doped source and drain SP (1), N-type doped source and drain SN (3), a polycrystalline grid PO L Y (4), a device active region TO (2) and a contact hole W1 (6), and is characterized in that the P-type doped source and drain of a strip-type NMOS tube are segmented, and the body contact of the device is designed between every two sections of the P-type doped source and drain.
2. The GGNMOS ESD protection device structure based on the SOI process according TO claim 1, wherein the P-type doped source-drain SP (1) is H-shaped, N-type doped source-drain SN (3) is injected into the inner side of the P-type doped source-drain SP (1), a polycrystalline grid PO L Y (4) is injected between the two N-type doped source-drain SN (3), the polycrystalline grid PO L Y (4) is N-shaped, an annular SAB layer (5) is injected into the polycrystalline grid PO L Y (4), a device active region TO (2) is injected into the P-type doped source-drain SP (1), and contact holes W1 (6) are formed in the N-type doped source-drain SN (3) positioned on the inner side of the SAB layer (5), the N-type doped source-drain SN (3) positioned on the outer side of the polycrystalline grid PO L Y (4) and the P-type doped source-drain SP (1).
3. The structure of GGNMOS ESD protection device based on SOI process according to claim 1 or 2, characterized in that: the SAB layer (5) is used for removing metal silicide on the silicon surface and improving the source-drain resistance.
4. The structure of claim 2, wherein the GGNMOS ESD protection device based on SOI process comprises: and 5 groups of the contact holes W1 (6) are formed, and each group is provided with 3 contact holes.
5. The GGNMOS ESD protection device structure based on SOI process of claim 2, wherein the distance from the side of the contact hole W1 (6) located inside the SAB layer (5) TO the inner side and upper end side wall of the poly-grid PO L Y (4) is 3um, the distance from the contact hole W1 (6) TO the inner side of the SAB layer (5) is 0.25um, the distance from the side of the contact hole W1 (6) located inside the N-type doped source drain SN (3) located outside the poly-grid PO L Y (4) TO the outer side of the poly-grid PO L Y (4) is 0.5um, the distance between the two N-type doped source drain SNs (3) is 0.38um, and the distance from the bottom of the N-type doped source drain SN (3) TO the top of the device active region TO (2) is 60 um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010339956.XA CN111508951B (en) | 2020-04-26 | 2020-04-26 | GGNMOS ESD protection device structure based on SOI technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010339956.XA CN111508951B (en) | 2020-04-26 | 2020-04-26 | GGNMOS ESD protection device structure based on SOI technology |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111508951A true CN111508951A (en) | 2020-08-07 |
| CN111508951B CN111508951B (en) | 2022-08-02 |
Family
ID=71873258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010339956.XA Active CN111508951B (en) | 2020-04-26 | 2020-04-26 | GGNMOS ESD protection device structure based on SOI technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111508951B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113192987A (en) * | 2021-04-27 | 2021-07-30 | 上海华虹宏力半导体制造有限公司 | SOI (silicon on insulator) body contact device structure and forming method thereof |
| CN113345866A (en) * | 2021-05-31 | 2021-09-03 | 中国电子科技集团公司第五十八研究所 | GGNMOS ESD protection device structure based on anti-radiation SOI technology |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060284256A1 (en) * | 2005-06-17 | 2006-12-21 | Taiwan Semiconductor Manufacturing Co. | Layout structure for ESD protection circuits |
| CN103996679A (en) * | 2014-06-12 | 2014-08-20 | 上海华力微电子有限公司 | SOI NMOS ESD device and preparing method thereof |
| CN109216343A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | Semiconductor device and its domain structure with electrostatic discharge protection structure |
| US20190198494A1 (en) * | 2016-08-29 | 2019-06-27 | Csmc Technologies Fab2 Co., Ltd. | Semiconductor device for enhancing electrostatic discharge protection and layout structure thereof |
-
2020
- 2020-04-26 CN CN202010339956.XA patent/CN111508951B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060284256A1 (en) * | 2005-06-17 | 2006-12-21 | Taiwan Semiconductor Manufacturing Co. | Layout structure for ESD protection circuits |
| CN103996679A (en) * | 2014-06-12 | 2014-08-20 | 上海华力微电子有限公司 | SOI NMOS ESD device and preparing method thereof |
| US20190198494A1 (en) * | 2016-08-29 | 2019-06-27 | Csmc Technologies Fab2 Co., Ltd. | Semiconductor device for enhancing electrostatic discharge protection and layout structure thereof |
| CN109216343A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | Semiconductor device and its domain structure with electrostatic discharge protection structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113192987A (en) * | 2021-04-27 | 2021-07-30 | 上海华虹宏力半导体制造有限公司 | SOI (silicon on insulator) body contact device structure and forming method thereof |
| CN113192987B (en) * | 2021-04-27 | 2023-11-03 | 上海华虹宏力半导体制造有限公司 | SOI body contact device structure and forming method thereof |
| CN113345866A (en) * | 2021-05-31 | 2021-09-03 | 中国电子科技集团公司第五十八研究所 | GGNMOS ESD protection device structure based on anti-radiation SOI technology |
| CN113345866B (en) * | 2021-05-31 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | GGNMOS ESD protection device structure based on anti-radiation SOI technology |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111508951B (en) | 2022-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6897536B2 (en) | ESD protection circuit | |
| CN100466249C (en) | Electrostatic discharge protecting circuit | |
| TWI397180B (en) | Lateral diffused metal oxide semiconductor (ldmos) devices with electrostatic discharge (esd) protection capability in integrated circuit | |
| US8912605B1 (en) | ESD protection circuit | |
| CN111508951B (en) | GGNMOS ESD protection device structure based on SOI technology | |
| WO2004075370A2 (en) | Minimum-dimension, fully-silicided mos driver and esd protection design for optimized inter-finger coupling | |
| CN102054865B (en) | MOS (Metal Oxide Semiconductor) transistor used as electrostatic protection structure and manufacturing method thereof | |
| CN102655149B (en) | PD SOI (partially-depleted silicon on insulator) technology-based body grid coupling ESD (electro-static discharge) protection structure | |
| US8703547B2 (en) | Thyristor comprising a special doped region characterized by an LDD region and a halo implant | |
| US9368629B2 (en) | Diode structure compatible with FinFET process | |
| US20150129977A1 (en) | Semiconductor electrostatic discharge protection apparatus | |
| JP2800702B2 (en) | Semiconductor device | |
| US7326998B1 (en) | Effective I/O ESD protection device for high performance circuits | |
| US8598625B2 (en) | ESD protection device with tunable design windows | |
| CN112466947B (en) | Field effect transistor based on electrostatic discharge protection structure | |
| US6278162B1 (en) | ESD protection for LDD devices | |
| CN102064173A (en) | Electrostatic protective device for silicon controlled rectifier | |
| CN113345866B (en) | GGNMOS ESD protection device structure based on anti-radiation SOI technology | |
| JP2024520102A (en) | GGNMOS TRANSISTOR STRUCTURE, ESD PROTECTION DEVICE AND CIRCUIT | |
| TWI682518B (en) | Electrostatic discharge protection device | |
| CN112071836B (en) | Grid-constrained silicon controlled rectifier and implementation method thereof | |
| CN103050493B (en) | Germanium policrystalline silicon Si-gate BiCMOS device and manufacture method | |
| CN113629052B (en) | ESD protection structure with adjustable trigger voltage and preparation method thereof | |
| CN116564961B (en) | LVTSCR device and chip electrostatic discharge circuit | |
| CN110690210B (en) | Grounded-gate N-type metal oxide semiconductor transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |