CN103050493B - Germanium policrystalline silicon Si-gate BiCMOS device and manufacture method - Google Patents
Germanium policrystalline silicon Si-gate BiCMOS device and manufacture method Download PDFInfo
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- CN103050493B CN103050493B CN201210325701.3A CN201210325701A CN103050493B CN 103050493 B CN103050493 B CN 103050493B CN 201210325701 A CN201210325701 A CN 201210325701A CN 103050493 B CN103050493 B CN 103050493B
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Abstract
The invention discloses the semiconductor device of a kind of germanium policrystalline silicon Si-gate BiCMOS, this device inside comprises HBT and cmos device, and in its cmos device, the grid structure of PMOS and NMOS is made up of gate oxide, polysilicon and germanium silicon.The invention also discloses the manufacture method of described germanium policrystalline silicon Si-gate BiCMOS device, when manufacturing the base of HBT, interlock system makes the grid of CMOS, decreases the use of one deck mask plate, reduces manufacturing process complexity.
Description
Technical field
The present invention relates to field of semiconductor manufacture, specifically relate to a kind of germanium policrystalline silicon Si-gate BiCMOS(BipolarComplementary Metal-Oxide-Semiconductor Transistor) device, the invention still further relates to the manufacture method of described germanium policrystalline silicon Si-gate BiCMOS device.
Background technology
Germanium silicium HBT (Heterojunction Bipolar Transistor) is the good selection of hyperfrequency device, and what first it utilized germanium silicon and silicon can be with difference, improves the Carrier Injection Efficiency of emitter region, the current amplification factor of increased device; Next utilizes the highly doped of germanium silicon outer base area, reduces base resistance, improves characteristic frequency; Germanium silicon technology is basic mutually compatible with silicon technology in addition, and therefore germanium silicium HBT has become one of main flow of hyperfrequency device.Germanium silicium HBT and cmos device is included in the BiCMOS of germanium policrystalline silicon Si-gate, generally when making the type device, the emitter of germanium silicium HBT and the grid of CMOS are completed by twice step, and manufacture craft is more complicated, employ two-layer mask plate simultaneously, be unfavorable for the reduction of manufacturing cost.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of germanium policrystalline silicon Si-gate BiCMOS device, and the base of its germanium silicium HBT and the grid of CMOS synchronously make.
Another technical problem to be solved by this invention is to provide the manufacture method of described germanium policrystalline silicon Si-gate BiCMOS device.
For solving the problem, a kind of germanium policrystalline silicon Si-gate BiCMOS device of the present invention, its inside comprises HBT and CMOS:
Described HBT, there is collector region between two shallow groove isolation structures in a silicon substrate, there is under collector region the counterfeit buried regions of N-type, surface of silicon on collector region is coated with germanium silicon, described germanium silicon covers whole collector region, and two ends extend on shallow groove isolation structure, between germanium silicon and shallow groove isolation structure, there are oxide layer and polysilicon in interval, connect with the shallow groove isolation structure germanium silicon upper surface of overlying regions of collector region is made to have step, step place is coated with oxide-film and nitride film, region between step and step has polysilicon, the two ends of described polysilicon and germanium silicon all have oxide side wall.
Described CMOS, comprise PMOS and NMOS, described PMOS device is near HBT, there is N-type trap between two shallow groove isolation structures, there is bottom N-type trap the counterfeit buried regions of N-type, in N-type trap, both sides have lightly-doped source drain region near the silicon face place of shallow groove isolation structure, lightly-doped source includes source-drain area in drain region respectively, covering gate oxide layer, polysilicon and germanium silicon successively on silicon face between lightly-doped source drain region, form the grid structure of PMOS, the raceway groove two ends of described grid structure have oxide side wall.
Described NMOS, there is P type trap between two shallow groove isolation structures, there is bottom P type trap the counterfeit buried regions of P type, in P type trap, both sides have lightly-doped source drain region near the silicon face place of shallow groove isolation structure, lightly-doped source includes source-drain area in drain region respectively, covering gate oxide layer, polysilicon and germanium silicon successively on silicon face between lightly-doped source drain region, form the grid structure of NMOS, the raceway groove two ends of described grid structure have oxide side wall.
At whole silicon face, there is inter-level dielectric, the emitter of HBT and base stage, the grid of PMOS and NMOS, source electrode, drain electrode are drawn by multiple contact hole respectively break-through inter-level dielectric, and the P type trap of the collector electrode of HBT and PMOS and NMOS and N-type trap are drawn by multiple dark contact hole more break-through inter-level dielectric and shallow groove isolation structure.
The manufacture method of a kind of germanium policrystalline silicon Si-gate BiCMOS device of the present invention, comprises following processing step:
Step 1: deposit layer of silicon dioxide and silicon nitride barrier in lightly doped P-type silicon substrate, shallow grooved-isolation technique is utilized to etch multiple groove to isolate HBT and CMOS district, carry out the counterfeit buried regions of N-type to HBT district and PMOS district to inject, carry out the counterfeit buried regions of P type to nmos area to inject, after filling silicon dioxide in shallow-trench isolation groove, carry out N-type trap injection to PMOS district, nmos area is carried out P type trap and is injected, and removes the barrier layer of whole substrate surface after completing.
Step 2: in whole surface of silicon successively deposit gate oxide and polysilicon, photoetching is opened HBT regional window and is carried out collector region injection.
Step 3: whole surface of silicon deposit germanium and silicon epitaxial, deposited oxide layer and nitration case successively again on germanium and silicon epitaxial, open oxide layer and the nitration case emitter window in HBT region by photoetching.
Step 4: deposit emitter region polysilicon also to emitter-polysilicon doping, makes to define region, emitter region with photoresist, etches away the polysilicon beyond region, emitter region, nitration case and oxide layer.
Step 5: remove photoresist, then the photoetching formation SiGe base of HBT and the germanium policrystalline silicon Si-gate of CMOS are carried out to germanium and silicon epitaxial.
Step 6: after carrying out the injection of light dope source and drain and the injection of PMOS light dope source and drain to NMOS, HBT and PMOS and NMOS grows formation oxide side wall simultaneously.
Step 7: P type source and drain is carried out to PMOS and injects and the injection of N-type source and drain carried out to NMOS, device surface deposit inter-level dielectric, and make contact hole and draw each electrode of HBT and CMOS and the N-type trap of CMOS and P type trap.
Preferably, in described step 2, the polysilicon thickness of deposit is
preferably, in described step 3, the germanium and silicon epitaxial thickness of deposit is
the doping content of germanium and silicon epitaxial is 1x10
18~ 1x10
19cM
-3.
Preferably, in described step 7, the source and drain implantation concentration of PMOS and NMOS is 1x10
20~ 1x10
21cM
-3.
A kind of germanium policrystalline silicon Si-gate BiCMOS device of the present invention, its cmos device jointly forms grid by gate oxide, polysilicon and germanium silicon, described manufacture method has manufactured the grid of CMOS while utilizing and forming germanium silicium HBT base, eliminate CMOS polysilicon gate process in traditional handicraft, decrease the use of one deck mask plate, reduce process complexity, reduction manufacturing cost, can be used for the CMOS of more than 5V.
Accompanying drawing explanation
Fig. 1 is that present invention process step 1 completes schematic diagram;
Fig. 2 is that present invention process step 2 completes schematic diagram;
Fig. 3 is that present invention process step 3 completes schematic diagram;
Fig. 4 is that present invention process step 4 completes schematic diagram;
Fig. 5 is that present invention process step 5 completes schematic diagram;
Fig. 6 is that present invention process step 6 completes schematic diagram;
Fig. 7 is that present invention process step 7 completes schematic diagram;
Fig. 8 is present invention process steps flow chart schematic diagram.
Description of reference numerals
1 is P type substrate, and 2 is shallow groove isolation structures, and 3 is the counterfeit buried regions of N-type, and 4 is the counterfeit buried regions of P type, 5 is collector regions, and 6 is N-type trap, and 7 is P type traps, and 8 is gate oxides, 9 is polysilicons, and 10 is germanium silicon, and 11 is oxide layers, and 12 is nitration cases, 13 is emitter region polysilicons, and 14 is photoresists, and 15 is oxide side walls, 16 is PMOS light dope source and drain, and 17 is NMOS light dope source and drain, and 18 is that PMOS source is leaked, 19 is NMOS source and drain, and 20 is inter-level dielectrics, and 21 is contact holes.
Embodiment
Germanium policrystalline silicon Si-gate BiCMOS device of the present invention, as shown in Figure 7, in P-type silicon substrate, 1 has HBT and CMOS to its structure.
Described HBT, there is the collector region 5 between two shallow groove isolation structures 2 in silicon substrate 1, collector region has the counterfeit buried regions 3 of N-type for 5 times, silicon substrate 1 surface coverage on collector region 5 has germanium silicon 10, described germanium silicon 10 covers whole collector region 5, and two ends extend on shallow groove isolation structure 2, between germanium silicon 10 and shallow groove isolation structure 2, there are oxide layer 8 and polysilicon 9 in interval, connect with shallow groove isolation structure 2 germanium silicon 10 upper surface of overlying regions of collector region 5 is made to have step, step place is coated with oxide-film 11 and nitride film 12, region between step and step has emitter region polysilicon 13, the two ends of described emitter region polysilicon 13 and germanium silicon 10 all have oxide side wall 15.
Described CMOS, comprise PMOS and NMOS, described PMOS device is near HBT, there is N-type trap 6 between two shallow groove isolation structures 2, there is bottom N-type trap 6 the counterfeit buried regions 3 of N-type, in N-type trap 6, both sides have lightly-doped source drain region 16 near silicon 1 surface of shallow groove isolation structure 2, source-drain area 18 is included respectively in lightly-doped source drain region 16, silicon 1 between lightly-doped source drain region 16 covering gate oxide layer 8, polysilicon 9 and germanium silicon 10 successively on the surface, form the grid structure of PMOS, the raceway groove two ends of described grid structure all have oxide side wall 15.
Described NMOS, there is P type trap 7 between two shallow groove isolation structures 2, there is bottom P type trap 7 the counterfeit buried regions 4 of P type, in P type trap 7, both sides have lightly-doped source drain region 17 near silicon 1 surface of shallow groove isolation structure 2, source-drain area 19 is included respectively in lightly-doped source drain region 17, silicon 1 between lightly-doped source drain region 17 covering gate oxide layer 8, polysilicon 9 and germanium silicon 10 successively on the surface, form the grid structure of NMOS, the raceway groove two ends of described grid structure have oxide side wall 15.
On whole silicon 1 surface, there is inter-level dielectric 20, the emitter of HBT and base stage, the grid of PMOS and NMOS, source electrode, drain electrode are drawn by multiple contact hole 21 respectively break-through inter-level dielectric 20, and the P type trap of the collector electrode of HBT and PMOS and NMOS and N-type trap are drawn by multiple dark contact hole 21 more break-through inter-level dielectric 20 and shallow groove isolation structure 2.
The manufacture method of germanium policrystalline silicon Si-gate BiCMOS device of the present invention, comprises following processing step:
Step 1: as shown in Figure 1, deposit layer of silicon dioxide and silicon nitride barrier in lightly doped P-type silicon substrate 1, shallow grooved-isolation technique is utilized to etch multiple groove 2 to isolate HBT and CMOS district, carry out the counterfeit buried regions 3 of N-type to HBT district and PMOS district to inject, carry out the counterfeit buried regions 4 of P type to nmos area to inject, after filling silicon dioxide in shallow-trench isolation groove 2, N-type trap 6 is carried out to PMOS district and injects, nmos area is carried out P type trap 7 and is injected, and removes the barrier layer on whole substrate 1 surface after completing.
Step 2: on whole silicon substrate 1 surface successively deposit gate oxide 8 and polysilicon 9, polysilicon 9 thickness of deposit is
photoetching is opened HBT regional window and is carried out collector region 5 and inject, and completes as shown in Figure 2.
Step 3: whole silicon substrate 1 surface deposition germanium and silicon epitaxial 10, deposited oxide layer 11 and nitration case 12 successively again on germanium and silicon epitaxial 10, germanium and silicon epitaxial 10 thickness of deposit is
the doping content of germanium and silicon epitaxial 10 is 1x10
18~ 1x10
19cM
-3.The oxide layer 11 in HBT region and the emitter window of nitration case 12 is opened, as shown in Figure 3 by photoetching.
Step 4: deposit emitter region polysilicon 13 also adulterates to emitter-polysilicon 13, makes 14 to define region, emitter region with photoresist, etches away the polysilicon 13 beyond region, emitter region, nitration case 12 and oxide layer 11.As shown in Figure 4.
Step 5: remove photoresist 14, then the photoetching formation SiGe base of HBT and the germanium policrystalline silicon Si-gate of CMOS are carried out to germanium and silicon epitaxial 10, as shown in Figure 5.
Step 6: after carrying out light dope source and drain 16 and 17 injection respectively to CMOS, HBT and CMOS grows simultaneously and form oxide side wall 15, as shown in Figure 6.
Step 7: carry out P type source and drain 18 to PMOS and inject and carry out N-type source and drain 19 to NMOS and inject, the source and drain implantation concentration of CMOS is 1x10
20~ 1x10
21cM
-3.Device surface deposit inter-level dielectric 20, and make contact hole 21 and draw each grid of the emitter of HBT, base stage and PMOS and NMOS, source electrode, drain electrode, dark contact hole 21 break-through inter-level dielectric 20 and shallow groove isolation structure 2 is more had the n type buried layer 3 of HBT to be drawn the collector electrode forming HBT, and the P type trap buried regions 4 of the N-type trap buried regions 3 of PMOS and NMOS is drawn, and finally completes figure as shown in Figure 7.
The above manufacture method, is formed the base of germanium silicium HBT and has synchronously manufactured with the grid of CMOS, simplify manufacturing process, reduce use one deck mask plate, reduce manufacturing cost.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. a germanium policrystalline silicon Si-gate BiCMOS device, includes HBT and CMOS, it is characterized in that:
Described HBT, there is collector region between two shallow groove isolation structures in a silicon substrate, there is under collector region the counterfeit buried regions of N-type, surface of silicon on collector region is coated with germanium silicon, described germanium silicon covers whole collector region, and two ends extend on shallow groove isolation structure, between germanium silicon and shallow groove isolation structure, there are oxide layer and polysilicon in interval, connect with the shallow groove isolation structure germanium silicon upper surface of overlying regions of collector region is made to have step, step place is coated with oxide-film and nitride film, germanium silicon face on step and between step has polysilicon, the two ends of described polysilicon and germanium silicon all have oxide side wall,
Described CMOS, comprise PMOS and NMOS, described PMOS device is near HBT, there is N-type trap between two shallow groove isolation structures, there is bottom N-type trap the counterfeit buried regions of N-type, in N-type trap, both sides have lightly-doped source drain region near the silicon face place of shallow groove isolation structure, lightly-doped source includes source-drain area in drain region respectively, covering gate oxide layer, polysilicon and germanium silicon successively on silicon face between lightly-doped source drain region, form the grid structure of PMOS, the raceway groove two ends of described grid structure all have oxide side wall;
Described NMOS, there is P type trap between two shallow groove isolation structures, there is bottom P type trap the counterfeit buried regions of P type, in P type trap, both sides have lightly-doped source drain region near the silicon face place of shallow groove isolation structure, lightly-doped source includes source-drain area in drain region respectively, covering gate oxide layer, polysilicon and germanium silicon successively on silicon face between lightly-doped source drain region, form the grid structure of NMOS, the raceway groove two ends of described grid structure all have oxide side wall;
At whole silicon face, there is inter-level dielectric, the emitter of HBT and base stage, the grid of PMOS and NMOS, source electrode, drain electrode are drawn by multiple contact hole respectively break-through inter-level dielectric, multiple deep hole contact more break-through inter-level dielectric and shallow groove isolation structure by the collector electrode of HBT, and the N-type trap of PMOS and NMOS P type trap draw.
2. the manufacture method of a kind of germanium policrystalline silicon Si-gate BiCMOS device as claimed in claim 1, is characterized in that: comprise following processing step:
Step 1: deposit layer of silicon dioxide and silicon nitride barrier in lightly doped P-type silicon substrate, shallow grooved-isolation technique is utilized to etch multiple groove to isolate HBT and CMOS district, carry out the counterfeit buried regions of N-type to HBT district and PMOS district to inject, carry out the counterfeit buried regions of P type to nmos area to inject, after filling silicon dioxide in shallow-trench isolation groove, carry out N-type trap injection to PMOS district, nmos area is carried out P type trap and is injected, and removes the barrier layer of whole substrate surface after completing;
Step 2: in whole surface of silicon successively deposit gate oxide and polysilicon, photoetching is opened HBT regional window and is carried out collector region injection;
Step 3: whole surface of silicon deposit germanium and silicon epitaxial, deposited oxide layer and nitration case successively again on germanium and silicon epitaxial, open oxide layer and the nitration case emitter window in HBT region by photoetching;
Step 4: deposit emitter region polysilicon also to emitter-polysilicon doping, makes to define region, emitter region with photoresist, etches away the polysilicon beyond region, emitter region, nitration case and oxide layer;
Step 5: remove photoresist, then the photoetching formation SiGe base of HBT and the germanium policrystalline silicon Si-gate of CMOS are carried out to germanium and silicon epitaxial;
Step 6: after carrying out the injection of light dope source and drain and the injection of PMOS light dope source and drain to NMOS, HBT and NMOS and PMOS grows formation oxide side wall simultaneously;
Step 7: P type source and drain is carried out to PMOS and injects and the injection of N-type source and drain carried out to NMOS, device surface deposit inter-level dielectric, and make contact hole and draw each electrode of HBT and CMOS and the N-type trap of CMOS and P type trap.
3. the manufacture method of a kind of germanium policrystalline silicon Si-gate BiCMOS device as claimed in claim 2, is characterized in that: the polysilicon thickness of deposit in described step 2 is
4. the manufacture method of a kind of germanium policrystalline silicon Si-gate BiCMOS device as claimed in claim 2, is characterized in that: the germanium and silicon epitaxial thickness of deposit in described step 3 is
the doping content of germanium and silicon epitaxial is 1x10
18~ 1x10
19cM
-3.
5. the manufacture method of a kind of germanium policrystalline silicon Si-gate BiCMOS device as claimed in claim 2, is characterized in that: in described step 7, the source and drain implantation concentration of PMOS and N MOS is 1x10
20~ 1x10
21cM
-3.
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| US6429085B1 (en) * | 1999-06-25 | 2002-08-06 | Applied Micro Circuits Corporation | Self-aligned non-selective thin-epi-base silicon germaniun (SiGe) heterojunction bipolar transistor BiCMOS process using silicon dioxide etchback |
| CN102104062A (en) * | 2009-12-21 | 2011-06-22 | 上海华虹Nec电子有限公司 | Bipolar transistor |
| CN102117749A (en) * | 2009-12-31 | 2011-07-06 | 上海华虹Nec电子有限公司 | Manufacturing technology for collector region and collector region buried layer of bipolar transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6429085B1 (en) * | 1999-06-25 | 2002-08-06 | Applied Micro Circuits Corporation | Self-aligned non-selective thin-epi-base silicon germaniun (SiGe) heterojunction bipolar transistor BiCMOS process using silicon dioxide etchback |
| CN102104062A (en) * | 2009-12-21 | 2011-06-22 | 上海华虹Nec电子有限公司 | Bipolar transistor |
| CN102117749A (en) * | 2009-12-31 | 2011-07-06 | 上海华虹Nec电子有限公司 | Manufacturing technology for collector region and collector region buried layer of bipolar transistor |
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