CN101452847B

CN101452847B - Manufacturing method for ESD gate grounding NMOS transistor

Info

Publication number: CN101452847B
Application number: CN200710094376A
Authority: CN
Inventors: 钱文生
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-12-06
Filing date: 2007-12-06
Publication date: 2010-05-26
Anticipated expiration: 2027-12-06
Also published as: CN101452847A

Abstract

The invention discloses a method for manufacturing an ESD gate grounded NMOS transistor. An ESD region does not adopt an ion injection method; a silicon substrate of a region of an ESD junction is subjected to dry-method etching to thin the depth of the ESD junction and reduce breakdown voltage of the ESD junction, thereby reducing trigger voltage of ESD; as the method carries out no any extra impurity adulteration on the ESD junction, an impurity distribution region and an exhaustion region of the ESD junction have no change so as not to cause increase of capacitance of the ESD junction and increase of delay of the transistor.

Description

ESD gate grounding NMOS transistor manufacture method

Technical field

The present invention relates to transistor and make the field, relate in particular to a kind of ESD gate grounding NMOS transistor manufacture method.

Background technology

Electrostatic protection (ESD) gate grounding NMOS (GGNMOS) transistor is the junction breakdown by drain terminal, makes Lou/raceway groove/source parasitic bipolar transistor conducting, obtains the effect of bleed off static.In order to make ESD have the better protect effect; need suitably to reduce the trigger voltage (triggervoltage) of its drain terminal; therefore often utilize the ESD ion to inject in the ESD technology, promptly inject N type or p type impurity, to reduce the puncture voltage of drain terminal knot in the position of transistorized drain terminal ESD knot.Though in common process, the ESD ion injects and only carries out in the part drain region, but can significantly increase the parasitic junction capacitance of drain terminal, and then increase transistorized delay.In addition, inject the method for regulating junction breakdown voltage by the ESD ion and also can cause the ESD trigger voltage too responsive to technology, process window is less.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of ESD gate grounding NMOS transistor manufacture method, can effectively reduce transistorized trigger voltage, can not increase the parasitic junction capacitance of drain terminal simultaneously.

For solving the problems of the technologies described above, the invention provides a kind of ESD gate grounding NMOS transistor manufacture method, comprise: after forming raceway groove, grid oxygen, polysilicon gate, silicon nitride side wall, lightly-doped source leakage and source leakage, make the position of selecting the ESD knot that is positioned at the drain terminal regional area on the silicon chip with photoresist, silicon chip is carried out dry etching form the ESD knot, then remove photoresist again.

The present invention is owing to adopted technique scheme, has such beneficial effect, not the method that adopts ion to inject promptly for the ESD zone, but come attenuate ESD junction depth by silicon substrate being carried out dry etching in the zone of ESD knot, and reduce the puncture voltage of ESD knot, therefore reduced the trigger voltage of ESD; The method of the invention so the Impurity Distribution and the depletion region of ESD knot all do not change, does not therefore cause the increase of ESD knot parasitic capacitance, so can not increase transistorized delay owing to the ESD knot is not carried out any extra doping impurity yet.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the schematic flow sheet of ESD gate grounding NMOS transistor constructed in accordance;

Fig. 2 a-2b is for making the sectional structure chart in the ESD gate grounding NMOS transistor process according to Fig. 1;

Fig. 3 is the vertical view according to the ESD gate grounding NMOS transistor of the method for the invention manufacturing.

Embodiment

As shown in Figure 1, the schematic flow sheet for ESD gate grounding NMOS transistor constructed in accordance may further comprise the steps:

At first, according to common process, the raceway groove, grid oxygen, polysilicon gate, silicon nitride side wall, lightly-doped source leakage and the source leakage that form the ESD gate grounding NMOS transistor (for what persons skilled in the art were familiar with are, the ion implantation dosage that lightly-doped source leaks should be the source leak that ion injects 1/100 to 1/10), since these operations for one of ordinary skill in the art all right and wrong Changshu know, therefore be not described in detail herein.

Second step; make the position of selecting the ESD knot that is positioned at the drain terminal regional area on the silicon chip with photoresist; the position of described ESD knot is determined by design rule apart from the gap length at grid edge; promptly depend on the electrostatic protection effect that will reach and the restriction of device size size, this should be to be familiar with for those skilled in the art.At this moment the cross-section structure of device is shown in Fig. 2 a;

The 3rd step, silicon chip is carried out dry etching form the ESD knot, the thickness of its etching depends on required ESD trigger voltage, generally in 500～1000 dust scopes,, can obtain different ESD trigger voltages easily by in this scope, choosing different silicon etching thickness, general in the time need obtaining higher trigger voltage, should select less etch thicknesses, and when increasing etch thicknesses gradually, trigger voltage can be successively decreased gradually then.

The 4th step, remove photoresist, at this moment the cross-section structure of ESD device is shown in Fig. 2 b, and its vertical view is then as shown in Figure 3.

Subsequently, can continue the step of follow-up manufacturing ESD gate grounding NMOS transistor again according to common process.

From said method as can be known, the method for the invention so the Impurity Distribution and the depletion region of ESD knot all do not change, therefore can't cause the increase of ESD knot parasitic capacitance owing to the ESD knot is not carried out any extra doping impurity.

Claims

1. ESD gate grounding NMOS transistor manufacture method, it is characterized in that, comprise: after forming raceway groove, grid oxygen, polysilicon gate, silicon nitride side wall, lightly-doped source leakage and source leakage, make the position of selecting the ESD knot that is positioned at the drain terminal regional area on the silicon chip with photoresist, silicon chip is carried out dry etching form the ESD knot, then remove photoresist again.

2. according to the described ESD gate grounding NMOS transistor of claim 1 manufacture method, it is characterized in that the etch thicknesses of silicon chip being carried out dry etching formation ESD knot depends on required ESD trigger voltage.

3. according to the described ESD gate grounding NMOS transistor of claim 2 manufacture method, it is characterized in that the etch thicknesses of silicon chip being carried out dry etching formation ESD knot is 500～1000 dusts.