TWI567937B - Active device and semiconductor device with the same - Google Patents

Description

Active component and semiconductor component using the same

The present invention relates to an active component and a semiconductor component thereof, and more particularly to a self-isolated active component and a shallow trench isolation semiconductor component using the active component.

In the Very-large-scale integration (VLSI) technology, shallow-trench isolation (STI) isolation active elements (such as complementary metal oxide semiconductor transistors) are usually defined. Channel width. However, researchers have found that STI edges can cause many serious problems for application components.

Figure 1 illustrates a conventional layout of a semiconductor component. The semiconductor component includes a plurality of active components 10 disposed on a substrate at a distance from one another and both located in a first well 12 having a first conductivity state, such as a P-well of an NMOS component. Furthermore, a light doping region has a second conductive state (eg, N-) and is located in the P-well and surrounds all active components 10 and P-well contacts. Adjacent active components 10 are electrically isolated by STI. Each active component 10 includes a diffusion region DIF having a first conductive state, a first contact region 111 (eg, A drain region) and a second contact region 113 (eg, a source region) are respectively located in the diffusion region DIF, and a polysilicon gate PG (having a gate contact 115 thereon) is formed in the first contact region 111 And the second contact area 113. For conventional semiconductor components, STIs that exist between adjacent active components 10 can cause undesirable STI edge issues.

2 is a schematic cross-sectional view showing a polysilicon gate of a conventional semiconductor device and insulators on both sides. A polysilicon gate PG is formed in a gate oxide layer GOX, and a channel 135 is located under the polysilicon gate PG and between the insulators STI. Figure 3A is an I _D -V _G characteristic curve of a typical low voltage (LV) NMOS transistor in which the gate oxide layer GOX has a thickness of 70 Å, W/Lg = 0.6 μm / 0.4 μm, and the curves are in a The pole bias (V _D ) is measured at 0.1V. Figure 3B is an I _D -V _G characteristic curve of a typical high voltage (HV) NMOS transistor, wherein the gate oxide layer GOX has a thickness of 370 Å, W/Lg = 10 μm / 1.6 μm, and the curves are in a bungee The bias voltage (V _D ) was measured at 0.1 V. Please refer to Figures 1 to 3B. The STI edge is usually the "weakness" of the semiconductor component (as circled in Figure 2), causing an abnormal subthreshold leakage current and an undesired double hump subcritical I _D- V _G characteristic curve (as shown by curve Process-1 in Figures 3A and 3B). In Figs. 3A and 3B, the curve Process-1 represents the I _D -V _G characteristic curve of a typical NMOS transistor having a bimodal leakage current, and the curve Process-2 represents the I _D of a typical NMOS transistor having an improved STI. The V _G characteristic curve, curve Process-3, represents the I _D -V _G characteristic curve of a typical NMOS transistor with improved STI and STI sidewall STI pocket implants.

In general, STI edges usually produce several non-ideal conditions, such as: (1) Boron segregation on the STI side wall leads to P-well dosage loss; (2) STI induced stress affects the stability of the threshold voltage (Vt); and (3) some interface traps or misalignments increase the leakage current. These conditions can cause undesirable subcritical properties and higher leakage current problems. Although it is often the case that a STI pocket implant is often applied to the "weakness" of the structure (as circled in Figure 2) to improve local well doping at the STI sidewall To suppress double-hump leakage (curve Process-3), the structure still has shortcomings, including: (1) it will reduce the junction breakdown of the high-voltage NMOS because of the junction (lightly doped NM) More P-well doping will be seen at the STI edge, and (2) a narrow narrow channel width effect will result when the channel width is reduced. Therefore, STI sidewall pocket doping still affects channel doping and threshold voltage control.

Moreover, due to the conventional configuration of the active device 10, as shown in FIG. 1, the manner of extension between the overlapping polysilicon gate PG and the diffusion region DIF limits the spacing of adjacent active devices 10, in particular It is the arrangement of the active elements 10 in the x-direction in Fig. 1. Therefore, since the design principle of the diffusion region DIF must be taken into consideration, this imposes a limitation on a tight-pitch layout design rule of the conventional configuration active element.

The present invention relates to an active component and a semiconductor component using the same. The active components of the embodiments are self-isolated using a conductive barrier structure, and the semiconductor components of the embodiments including the shallow trench isolation (STI-free) active devices can successfully solve the STI edge effects encountered by conventional semiconductor components (STI Edge issues).

According to an embodiment, a semiconductor device includes a substrate, a first well having a first conductive state and extending downward from a surface of the substrate, and a diffusion region of the impurity doped with the first conductive state. And extending downward from the surface of the first well, and a plurality of active components are formed in the diffusion region. Wherein, the active components are disposed apart from each other and electrically insulated from each other by the diffusion region.

According to an embodiment, an active device is formed in a diffusion region having a first conductive state at a substrate. The active component includes a conductive guarding structure, a first contact region, and a second contact region. The conductive barrier structure includes a middle portion, a first guarding portion, and a second guarding portion. The first guard portion is coupled to one side of the intermediate portion to define a first region located in one of the diffusion regions, wherein the first region is surrounded by the first guard portion and the intermediate portion. A second guard portion is opposite to the first guard portion and connects to the other side of the intermediate portion to define a second region located in one of the diffusion regions, wherein the second region is surrounded by the second guard portion and the intermediate portion. The first contact area has a second The conductive state is formed in the first region of the conductive barrier structure, and the first contact region is spaced from the first guard portion and the intermediate portion. The second contact region has a second conductive state and is formed in the second region of the conductive barrier structure, and the second contact region is spaced from the second guard portion and the intermediate portion.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.

10, 20‧‧‧ active components

12. PW‧‧‧ first well

111‧‧‧First contact area

113‧‧‧Second contact area

115‧‧‧gate contacts

135‧‧‧ channel

22‧‧‧Lightly doped areas

24‧‧‧ spacers

201‧‧‧ Conductive guardrail structure

201m‧‧‧ middle part

2011‧‧‧First Department

2012‧‧‧Second Ministry

201a‧‧‧First area

201b‧‧‧Second area

211‧‧‧First contact area

213‧‧‧Second contact area

215‧‧‧ Third contact area

251‧‧‧ first joint

253‧‧‧second junction

255‧‧‧gate contacts

S‧‧‧Substrate

DIF‧‧‧Diffusion area

PG‧‧‧ polysilicon gate

STI‧‧‧Insulators

GOX‧‧‧ gate oxide layer

S1‧‧‧first isolation distance

S2‧‧‧Second isolation distance

W’‧‧‧ effective channel width

W‧‧‧Width of the first and second regions

W2‧‧‧Width of the first and second guards

Dp‧‧‧ active component spacing

Lg‧‧‧ channel length

d _offset ‧‧‧Minimum distance from the contact area to the first guard/second guard

Figure 1 illustrates a conventional layout of a semiconductor component.

2 is a schematic cross-sectional view showing a polysilicon gate of a conventional semiconductor device and insulators on both sides.

Figure 3A is an I _D -V _G characteristic curve of a typical low voltage (LV) NMOS transistor in which the gate oxide layer GOX has a thickness of 70 Å, W/Lg = 0.6 μm / 0.4 μm, and the curves are in a The pole bias (V _D ) is measured at 0.1V.

Figure 3B is an I _D -V _G characteristic curve of a typical high voltage (HV) NMOS transistor, wherein the gate oxide layer GOX has a thickness of 370 Å, W/Lg = 10 μm / 1.6 μm, and the curves are in a bungee The bias voltage (V _D ) was measured at 0.1 V.

Figure 4 is a layout of a semiconductor device of one embodiment of the present disclosure.

FIG. 5A is a schematic view showing an active element of one of the semiconductor elements of the disclosed embodiment.

Figure 5B is an exploded view of the conductive barrier structure of one of the active components of Figure 5A.

Figure 6 is a schematic view showing two adjacent active elements in the semiconductor device of Figure 4.

FIG. 7 is a schematic diagram showing two adjacent active elements in FIG. 4 of the disclosed embodiment, and a drain current between the source and the drain of the active device.

Figure 8 clearly shows that there is no bimodal leakage current generation, and the experimental values are ideally coincident with the simulation curves of the theoretical model.

Figure 9 is a page buffer circuit design of a NAND flash memory with a clamped line element (BL Clamp Devices).

Figure 10 is a diagram showing the layout of a high voltage semiconductor device in an embodiment.

FIG. 11 is a diagram showing a layout of a CMOS including a plurality of active elements, which is applicable to an embodiment of the present disclosure.

12A-12D are respectively a perspective view of the STI-free transistor according to an embodiment of the TCAD simulation experiment, and a cross-sectional view along the YZ-plane, the XZ-plane, and the XY-plane.

Figure 13A is a graph showing the I _D -V _G characteristic of the STI-free transistor of the embodiment in the TCAD simulation experiment, in which the voltages Vg1 and Vg2 are applied to the STI-free transistor "Gate 1" and "Gate 2" components of the embodiment. .

Figure 13B is a schematic diagram showing the simulation of the current density of Vg1 = 0.5V, Vg2 = 3.8V, and Vds = 0.1V in the "Gate 1" and "Gate 2" elements.

Fig. 14A is a graph showing the I _D -V _G characteristic of the STI-free transistor of the embodiment in the TCAD simulation experiment, wherein the system has different widths W2 of 0.1 μm, 0.15 μm and 0.2 μm.

Fig. 14B is a graph showing the I _D -V _G characteristic of the STI-free transistor of the embodiment in the TCAD simulation experiment, wherein the system changes the channel length Lg to 0.25 μm, 0.3 μm and 0.4 μm.

Figure 15A is a cross-sectional view of the STI-free transistor of the embodiment along the XY-plane in a TCAD simulation experiment.

15B-15E is a graph showing the I _D -V _G characteristic of the STI-free transistor of the embodiment in the TCAD simulation experiment, wherein Vg2=0V and Vd1=0.1V in Fig. 15B, Vg2=0V and Vd1 in Fig. 15C = 3.8 V, Vg2 = 3.8 V and Vd1 = 0.1 V in Fig. 15D, and Vg2 = 3.8 V and Vd1 = 3.8 V in Fig. 15E.

Figure 16 is a graph showing the IV _d1 characteristic curve in the STI-free transistor of the embodiment in the TCAD simulation experiment.

In an embodiment of the present disclosure, an active component and one of the semiconductor components are applied. The active component of the embodiment is self-isolated with a conductive guarding structure, such as a polysilicon barrier structure also acting as a gate for the active component. The semiconductor component without the STI active device of the application embodiment can successfully solve the STI edge problem existing in the conventional semiconductor device. The embodiments of the present disclosure are applicable to many different aspects of low voltage (LV) semiconductor components and high voltage (HV) semiconductor components, and the disclosure is not limited to a certain application. The following is an embodiment, which is described in detail with the illustration. A new layout of one of the active components and a semiconductor component proposed is disclosed. However, the disclosure is not limited to this. The descriptions of the embodiments, such as the details of the details, the dimensions of the elements and the choice of materials, etc., are for illustrative purposes only and are not intended to limit the scope of the disclosure.

Furthermore, the disclosure does not show all possible embodiments. The structure and process may be modified and modified to meet the needs of the actual application without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

Figure 4 is a layout of a semiconductor device of one embodiment of the present disclosure. FIG. 5A is a schematic view showing an active element of one of the semiconductor elements of the disclosed embodiment. Figure 5B is an exploded view of the conductive barrier structure of one of the active components of Figure 5A. Figure 6 is a schematic view showing two adjacent active elements in the semiconductor device of Figure 4. Please refer to Figure 4 - Figure 6.

In one embodiment, a semiconductor device includes a substrate S having a first well PW of a first conductive state (eg, P-type), a diffusion region DIF, and a plurality of active devices 20 formed in the diffusion region DIF (fourth Figure and Figure 6). The first well PW extends downward from one surface of the substrate S, and the diffusion region DIF having the first conductive state (e.g., P-type) extends downward from one surface of the first well PW (Fig. 6). As shown in FIG. 4, the active elements 20 are disposed at a distance from each other, and all the active elements 20 are formed in a continuous diffusion region DIF, wherein the active device 20 is They are electrically insulated from each other by the diffusion region DIF. No shallow trench isolation (STI) exists between two adjacent active elements 20. In one embodiment, the diffusion region DIF is heavily doped with impurities in a first conductivity state, such as P+, to provide field isolation.

Furthermore, each active component 20 includes a conductive guarding structure 201 formed on the diffusion region DIF, and a light doping region 22 having a second conductive state (eg, N-), and The lightly doped region 22 extends downwardly from one surface of the diffusion region DIF and is correspondingly located within the conductive barrier structure 201. According to an embodiment, an isolating region (e.g., an area labeled with an isolation distance S1 or S2) between adjacent active elements 20 is defined by conductive barrier structure 201 of adjacent active elements 20. As shown in FIG. 4, adjacent active elements 20 arranged along the first direction, such as the x-direction, are isolated by an isolation region having a first isolation distance S1, and phases arranged along a second direction, such as the y-direction. The adjacent active element 20 is isolated by an isolation region having a second isolation distance S2. The first isolation distance S1 and the second isolation distance S2 may not be equal or equal. In one embodiment, the first isolation distance S1 is equal to the second isolation distance S2. According to an embodiment, the space (S1/S2) between adjacent active elements 20 is free of shallow trench isolation (STI), so the embodiment is designed to completely eliminate the semiconductor components from any STI edge effects (eg, bimodal Critical leakage current, breakdown voltage drop, difference in different STI layouts, etc.).

In one embodiment, the conductive barrier structure 201 includes a middle portion 201m, a first guarding portion 2011, and A second guarding portion 2012, as shown in Figures 5A and 5B. The first guard portion 2011 is connected to one side of the intermediate portion 201m to define a first region 201a located in one of the diffusion regions DIF. The second guard portion 2012 is opposite to the first guard portion 2011 and is connected to the other side of the intermediate portion 201m to define a second region 201b located in one of the diffusion regions DIF. Therefore, the first region 201a is surrounded by the first guard portion 2011 and the intermediate portion 201m, and the second region 201b is surrounded by the second guard portion 2012 and the intermediate portion 201.

As shown in FIG. 4, the first region 201a and the second region 201b of the active device 20 are located within the lightly doped region 22. The lightly doped region 22 surrounds the first region 201a and the second region 201b but is spaced apart therefrom. In one embodiment, the lightly doped region 22 is located at the corresponding first guard portion 2011 and the second guard portion 2012. For example, the boundary of the lightly doped region 22 (ie, indicated by the broken line in the active element 20 in FIGS. 4 and 5A) substantially corresponds to the middle of the first guard portion 2011 and the second guard portion 2012, as in the first Figure 4 and Figure 5A show.

Furthermore, each active component 20 further includes a first contact region 211 having a second conductive state (eg, N+) and formed in the first region 201a of the conductive barrier structure 201, and having a second conductive state ( For example, N+) is formed in a second contact region 213 in the second region 201b of the conductive barrier structure 201. The first contact region 211 is spaced apart from the first guard portion 2011 and the intermediate portion 201m, and the second contact region 213 is spaced apart from the second guard portion 2012 and the intermediate portion 201m. In an embodiment, the first contact region 211 and the second contact region 213 can be used as a drain region of the active device 20, respectively. And a source region.

As shown in FIG. 6, each active component 20 further includes a first contact 251 (for example, as a drain) formed in the first contact region 211, and a second contact 253. (for example, as a source) is formed in the second contact region 213. Furthermore, a gate contact 255 is in contact with the conductive barrier structure 201. In one embodiment, the gate contact 255 can be formed on the third contact region 215 of the intermediate portion 201m of the conductive barrier structure 201, wherein the gate contact 255 is correspondingly located within the lightly doped region 22. However, the gate contact 255 is not limited to the position shown in the drawing, and may be formed at other positions as long as the gate contact 255 can be electrically connected to the conductive barrier structure 201.

In the manufacturing process, the openings of the conductive barrier structure 201 (corresponding to the first region 201a and the second region 201b) are formed under the conductive barrier structure 201 by doping a small amount of second conductive state (such as N-) impurities. Lightly doped region 22, as shown in Figure 6. Thereafter, appropriately sized spacers (such as oxides) 24 are formed at the openings to define the first contact regions 211 and the second contact regions 213. Since the areas of the first contact region 211 and the second contact region 213 are very small (especially corresponding to semiconductor components for small electronic products), the first contact 251, the second contact 253, and the gate contact 255 may be formed first. Then, a high concentration of the second conductive state impurity (such as N+) is doped under the contacts by a plug implant. However, the disclosure is not limited to this manufacturing method. The steps as described above are for illustrative purposes only and may be appropriately adjusted or varied as needed for the actual application conditions.

According to an embodiment, the material of the conductive guardrail structure 201 may be more The wafer, and the intermediate portion 201m of the conductive barrier structure 201 can serve as a gate of the active device 20 (i.e., a polysilicon gate). FIG. 7 is a schematic diagram showing two adjacent active elements in FIG. 4 of the disclosed embodiment, and a drain current between the source and the drain of the active device. Please refer to both Figure 4 and Figure 7. The intermediate portion 201m of the conductive barrier structure 201 as the gate of the active component 20 has an effective channel width W' along the first direction (eg, the x-direction), along the second The direction (such as the y-direction) has a channel length Lg.

In one embodiment, the first direction (eg, the x-direction) is perpendicular to the second direction (eg, the y-direction). As shown in Figs. 4 and 7, the first region 201a and the second region 201b are separated by a channel length Lg. Furthermore, the first guard portion 2011 and the second guard portion 2012 each have a width W2 along the first direction (eg, the x-direction), and the first region 201a and the second region 201b each have a width W along the first direction. . The first contact 251 formed on the first contact region 211 and the second contact 253 formed on the second contact region 213 may serve as a drain and a source, respectively. As shown in Figure 7, the drain current between the source and the drain includes: the current flowing in the shortest path between the source and the drain (ie, the vertical line segment), and the side of the flow path that is longer than the shortest path. Sidewall current (the curve on both sides). Thus, the effective channel width W' of one of the active elements 20 in the embodiment is approximately equal to the sum of the width W and the double width W2 (denoted as W + 2 x W2). The side current has a longer effective channel length, ie greater than Lg, without the problem of bimodal leakage current. In one embodiment, when the diffusion region DIF includes a high concentration of the first conductive state dopant such as P+, and outside the lightly doped region 22, a P+ surrounding gate is formed to achieve field isolation. According to an embodiment, the parasitic leakage of two adjacent transistors can be effectively suppressed by the diffusion region DIF, and the suppression can be sufficient due to the space (S1/S2) between the two active devices (such as NMOS). The concentration of P-type doping (P+) is achieved. FIG. 8 is an I _D -V _G characteristic curve of a MOSFET transistor layout according to an embodiment of the present disclosure. Figure 8 clearly shows that there is no bimodal leakage current generation, and the experimental values are ideally coincident with the simulation curves of the theoretical model. Furthermore, only a very low leakage current value was observed when Vg was lower than 0.7V.

According to the above, the semiconductor element to which the active element of the embodiment is applied has several characteristics, such as: (1) a diffusion region DIF having no separation (no STI exists in the active region of the element); (2) using a conductive barrier structure (eg The polysilicon gate 201 itself defines the channel length and the channel width; (3) the lightly doped region 22 (eg, N-) and the doped region 22 (eg, N+) (ie, the first contact region 211, the second contact region 213, and The gate contact regions 215) are isolated in each gate region; and (4) the isolation distance between the conductive barrier structures 201 can be achieved with P+ impurities to achieve good field insulation. The semiconductor element layout of the embodiment (as shown in Fig. 4) has many advantages over the conventional layout of the semiconductor element as shown in Fig. 1. For example, the space between adjacent active elements 20 (S1/S2) is present because there is no shallow trench isolation (STI), so the embodiment is designed to completely eliminate the semiconductor components from any STI edge effects (eg, bimodal sub-critical leakage). Current, breakdown voltage drop, difference in different STI layouts, etc.). Moreover, due to the special configuration of the active element 20 of the embodiment, there is no overlap and extension between the conventional diffusion region DIF and the polysilicon gate, so the distance between the active elements 20 can be further reduced.

The active component of the embodiment can be applied to a high voltage (HV) semiconductor component Or low voltage (LV) semiconductor components. The following describes one of the design rules that can be implemented in a high voltage semiconductor element or a low voltage semiconductor element. However, the relevant parameter values set forth below are for illustrative purposes only and are not intended to limit the scope of the disclosure.

Referring to Figure 4, there may be shown a layout of a low voltage semiconductor component in an embodiment. For a NAND flash memory device operating at 3V, the maximum bias voltage is about 3.8V. The following is a description of a set of related parameters for operating a low voltage semiconductor component at 3V. In one embodiment, for a low voltage semiconductor device operating at 3V, the channel length Lg can be from about 0.3 [mu]m to about 0.4 [mu]m to support a maximum bias voltage of 3.8V. The minimum width W of the first region 201a and the second region 201b is about 0.2 μm, and one of the first contact region 211 and the second contact region 213 (ie, each drain/source) has about 0.1 μm×0.1 μm. area. The minimum width W2 of the first guard portion 2011 and the second guard portion 2012 is about 0.1 μm to about 0.15 μm. The space of adjacent active elements 20 (assuming S1 = S2 = S) is, for example, a distance of about 0.18 μm to about 0.28 μm. Furthermore, the active element 20 has a pitch DP of about 0.68 μm. Since the active device pitch DP of the embodiment reaches about 0.68 μm, it conforms to the page buffer circuit design of the NAND flash memory.

Figure 9 is a page buffer circuit design of a NAND flash memory with a clamped line element (BL Clamp Devices). In NAND flash memory page buffer designs, the BLC, BLK, and BLC_I components (and the components of the three circled regions) are important. These components require a tight threshold voltage (Vt) distribution to accurately control the bit line bias during sensing. Furthermore, due to many page buffer circuits There is a need for a layout rule that tightly configurable components. While the elements of the embodiments are particularly suitable for this purpose, they have at least the following advantages: including (1) the layout of the embodiment can achieve a tighter arrangement spacing than the conventional layout since there is no need to consider the diffusion area rule; and (2) the tight threshold voltage (Vt) distribution and problems and variations caused by the absence of STI edges.

Figure 10 is a diagram showing the layout of a high voltage semiconductor device in an embodiment. Please refer to the description of the relevant components of the active components of the above embodiments. The same elements in the drawings of FIG. 10 and FIG. 4 are given the same reference numerals to clearly illustrate the embodiments. Details thereof (for example, the lightly doped region 22 (N-) in the polysilicon gate, the first contact region 211 / the second contact region 213 in the first region 201a / the second region 201b) have been described as before This will not be repeated here. The main difference between the design of the low voltage and high voltage semiconductor components is that the distance between the first contact region 211 and the second contact region 213 of the high voltage semiconductor component to the first guard portion 2011 and the second guard portion 2012 must be increased to support the high voltage operation. Since the N+ of the contact region (211/213/215) is performed after the contact etching, the heavily doped contact region (211/213/215) is confined to a small-area contact region.

The following is a description of one of the design rules for a high voltage component of a NAND flash memory operating at 30V. However, the relevant parameter values set forth below are for illustrative purposes only and are not intended to limit the scope of protection. As shown in Fig. 10, in a high voltage semiconductor device of an embodiment, the channel length Lg may be about 1.2 μm to about 2 μm to support a maximum operating voltage of 30V. In one embodiment, the minimum distance from the contact regions (ie, N+, first contact region 211 and second contact region 213) to the polysilicon gate (ie, the first guard portion 2011 and the second guard portion 2012) is denoted by d _offset The distance d _offset is about 0.5 μm to about 1 μm to provide a sufficient N+drain offset, thus reducing the collapse caused by GEDL (gate induced drain leakage). In one embodiment, the distance d _offset is about 0.8 μm. Moreover, in one embodiment, one of the first contact regions 211 and/or the second contact regions 213 (ie, each drain/source) has an area of about 0.1 μm×0.1 μm. In one embodiment, the minimum width W2 of the first guard portion 2011 and the second guard portion 2012 is about 0.2 μm. Therefore, for the high voltage semiconductor device of an embodiment, the relationship of the distance d _offset (about 0.5 μm to 1 μm) and the width W2 (about 0.2 μm) can be expressed as 2.5 × W 2 . d _offset 5 × W2. In one embodiment, the minimum channel width W' is about 2.1 [mu]m. Furthermore, the space of adjacent active elements 20 (with P-type doping to achieve field insulation) (assuming S1 = S2 = S) has a minimum distance of about 1 [mu]m.

Although the first well has a P-type conductive state and the lightly doped region 22 has an N-conductive state in the above embodiment, the disclosure is not limited thereto. For a PMOS process, the present disclosure can also be applied as long as the doped conductive state of the well and the junction is reversed. For example, the P-well of the NMOS device and the N-type lightly doped region 22 are replaced by an N-well and a P-type lightly doped region in the PMOS device. Therefore, a CMOS may include a plurality of NMOS devices sharing a P-type well, and a plurality of PMOS devices sharing an N-type well. FIG. 11 is a diagram showing a layout of a CMOS including a plurality of active elements, which is applicable to an embodiment of the present disclosure. A CMOS layout design for large components separates multiple NMOS components sharing a P-well from multiple PMOS components sharing an N-well, as shown in Figure 11.

Furthermore, the active component of the embodiment can also be easily formed on a thin body On silicon-on-insulation (SOI) wafers.

DIF isolation can be fabricated during polysilicon etch (self-aligned etch) to form the conductive barrier structure 201, and thus the space (S1/S2) can be further reduced. Since there is no well isolation considerations, it is possible to design N/P MOSFETs in adjacent areas to optimize the layout. Furthermore, it is a floating-body MOSFET due to the lack of body contact.

<Related experiments, simulations and results>

Many related experiments and simulations (such as Computer Aided Design, "TCAD") are used to observe the results of the layout design of the embodiment. The following is a summary of the layout design of several of the proven embodiments (eg Good field insulation between active components, no traces of silicon current in STI transistors, etc.). 12A-12D are respectively a perspective view of the STI-free transistor according to an embodiment of the TCAD simulation experiment, and a cross-sectional view along the YZ-plane, the XZ-plane, and the XY-plane. Please also refer to Figure 4 and the description of the relevant parameters. In the TCAD simulation experiment, "Gate 1" and "Gate 2" represent two adjacent active components, and related parameters include: GOX (gate oxide) = 7 nm, SPR = 60 nm, Lg (channel length) = 0.4 μm , W1=0.2 μm, W2=0.1 μm, diffusion contact (ie, N+, first contact region 211 and second contact region 213)=0.1 μm×0.1 μm, distance of P-type 主动 to active region (AA)=0.5 Μm, heavy doping concentration (HDD) = 1 × 10 ²⁰ cm ^-3 , light doping concentration (LDD) = 5 × 10 ¹⁸ cm ^-3 , N + gate doping concentration = 1 × 10 ²⁰ cm ^-3 , P The erbium doping concentration = 6 × 10 ¹⁷ cm ^-3 , and the active element pitch (pitch) = 0.68 μm.

Fig. 13A is a graph showing the I _D -V _G characteristic curve of the STI-free transistor of the embodiment in the TCAD simulation experiment. Among them, the voltages Vg1 and Vg2 are applied to the STI-free transistor "Gate 1" and "Gate 2" elements of the embodiment. In Fig. 13A, the two TI _D - V _G characteristic curves are obtained by applying a voltage of Vg1 of 0V and Vg2 of 3.8V, respectively. According to the result of Fig. 13A, the variation of the bias applied to the element labeled "Gate 2" does not change the I _D - V _G characteristic of the element labeled "Gate 1", thus demonstrating that the embodiment provides a good field insulation. Figure 13B is a schematic diagram showing the simulation of the current density of Vg1 = 0.5V, Vg2 = 3.8V, and Vds = 0.1V in the "Gate 1" and "Gate 2" elements. From the current density simulation of Fig. 13B, it is known that most of the drain current flows along the path of the shortest distance, so the effective channel width can also be regarded as equal to W1.

Fig. 14A is a graph showing the I _D -V _G characteristic of the STI-free transistor of the embodiment in the TCAD simulation experiment, wherein the system has different widths W2 of 0.1 μm, 0.15 μm and 0.2 μm. In Fig. 14A, the relevant parameters of the STI-free transistor include: Vds = 0.1 V, Vg2 = 3.8 V, W1 = 0.2 μm, Lg = 0.4 μm, and P-type erbium doping concentration = 6 × 10 ¹⁷ cm ^-3 . Fig. 14B is a graph showing the I _D -V _G characteristic of the STI-free transistor of the embodiment in the TCAD simulation experiment, wherein the system changes the channel length Lg to 0.25 μm, 0.3 μm and 0.4 μm. In Fig. 14B, the relevant parameters of the STI-free transistor include Vds = 0.1 V, Vg2 = 3.8 V, W1 = 0.2 μm, W2 = 0.1 μm, and P-type erbium doping concentration = 6 × 10 ¹⁷ cm ^-3 . The results of Figures 14A and 14B indicate that the narrow-width effect and the short-channel effect are mirrored. Furthermore, when W2 = 0.2 um, the spatial distance between the active elements can be reduced to only 0.08 μm, and no increase in the leakage current that causes attention is observed.

Figure 15A is a cross-sectional view of the STI-free transistor of the embodiment along the XY-plane in a TCAD simulation experiment in which the applied voltage is indicated on the contact area of the active device. 15B-15D are diagrams showing the I _D -V _G characteristic curve of the STI-free transistor of the embodiment in the TCAD simulation experiment, wherein Vg2=0V and Vd1=0.1V in Fig. 15B, Vg2=0V and Vd1 in Fig. 15C = 3.8 V, Vg2 = 3.8 V and Vd1 = 0.1 V in Fig. 15D, and Vg2 = 3.8 V and Vd1 = 3.8 V in Fig. 15E. According to the simulation results of Fig. 15B-15D, the transistor "Gate-2" maintains a very small drain current regardless of the bias condition, indicating excellent field insulation effect.

Figure 16 is a graph showing the IV _d1 characteristic curve in the STI-free transistor of the embodiment in the TCAD simulation experiment, wherein Vg2 = 3.8V and Vg1 = 3.8V, and the Id1 curve represents the drain current of the transistor "Gate-1". The Id2 curve represents the drain current of the transistor "Gate-2" and the Ip-well curve represents the current of the P-well. According to the simulation experiment shown in Fig. 16, when the Vd1 is increased, the P-type well current also rises. But even when Vd1 is increased to 8V, the gate current Id2 of the transistor "Gate-2" remains infinitely small.

In summary, in the semiconductor device of the active device of the embodiment, each active device uses a conductive barrier structure (such as a polysilicon gate) to define the channel length and width. The semiconductor component of an embodiment may include NMOS, PMOS, or CMOS. For NMOS, the N+ junction is surrounded by a conductive barrier structure (such as a polysilicon gate), thus allowing the active component (without STI) to be self-isolated by a conductive barrier structure (such as a polysilicon gate). Furthermore, the area outside the conductive barrier structure (ie, diffusion) The region DIF) can be doped with P-type impurities to achieve field insulation. The semiconductor layout design of the embodiment can completely eliminate the semiconductor components from any STI edge effects, such as bimodal sub-critical leakage current, breakdown voltage drop, difference in different STI layouts, etc., and can successfully solve the traditional semiconductor components encounter STI The problem of edge effects. Moreover, since the active elements of the embodiment do not overlap and extend as in the conventional diffusion region DIF and the polysilicon gate, the pitch of the active elements is further reduced. In addition, the results of the simulation experiments also demonstrate that the semiconductor component of the embodiment can achieve good field insulation and an increase in leakage current that cannot be noticed.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20‧‧‧Active components

PW‧‧‧First Well

22‧‧‧Lightly doped areas

201‧‧‧ Conductive guardrail structure

201m‧‧‧ middle part

2011‧‧‧First Department

2012‧‧‧Second Ministry

201a‧‧‧First area

201b‧‧‧Second area

211‧‧‧First contact area

213‧‧‧Second contact area

215‧‧‧ Third contact area

S1‧‧‧first isolation distance

S2‧‧‧Second isolation distance

Dp‧‧‧ active component spacing

Lg‧‧‧ channel length

W2‧‧‧Width of the first and second guards

W‧‧‧Width of the first and second regions

Claims (10)

A semiconductor device comprising: a substrate; a first well having a first conductive state and extending downward from a surface of the substrate; a diffusion region doping the impurity of the first conductive state and from the first One of the wells extends downwardly; a plurality of active components are formed in the diffusion region, and the active components are disposed apart from each other, wherein the active components are electrically insulated from each other by the diffusion region. The semiconductor component of claim 1, wherein one of the active components comprises: a conductive guarding structure formed on the diffusion region; and a light doping region a second conductive state, wherein the lightly doped region extends downward from a surface of the diffusion region and is correspondingly located within the conductive barrier structure, wherein the adjacent active components each comprise the conductive barrier structure An isolating region between the adjacent active components is defined by the conductive barrier structures of the adjacent active components. The semiconductor device of claim 2, wherein the conductive barrier structure comprises: a middle portion, wherein the intermediate portion serves as a gate of the active device, and the intermediate portion is along a first One direction has a channel width (channel Width, W') and having a channel length (Lg) along a second direction; a first guarding portion connecting one side of the intermediate portion to define one of the diffusion regions a first region, wherein the first region is surrounded by the first guard portion and the intermediate portion; and a second guarding portion opposite to the first guard portion and connected to the middle portion The other side of the portion is defined as a second region of the diffusion region, wherein the second region is surrounded by the second guard portion and the intermediate portion, wherein the first region and the second region The region is located within the lightly doped region, and the first region and the second region are separated by a distance from the length of the channel. The semiconductor device of claim 3, wherein one of the active elements further comprises: a first contact region having the second conductive state and formed on the conductive barrier structure In the first region, the first contact region is spaced apart from the first guard portion and the intermediate portion; a second contact region has the second conductive state and is formed in the conductive fence structure In the two regions, the second contact region is spaced apart from the second guard portion and the intermediate portion; and a first contact is formed in the first contact region, and a second contact (second contact) ) formed in the second contact region. The semiconductor device of claim 1, wherein when the semiconductor device is a low voltage (LV) device, a space between adjacent ones of the active devices The space (S) is in the range of 0.18 μm to 0.28 μm; when the semiconductor component is a high voltage (HV) component, a space (S) between adjacent active components is 0.8. Within the range of μm to 1.2μm. The semiconductor device according to claim 1, wherein a space (S) between adjacent ones of the active elements is not shallow trench isolation (STI). An active component is formed in a diffusion region of a substrate having a first conductive state, the active component comprising: a conductive guarding structure, including: a middle portion; a first a first guarding portion, connected to one side of the intermediate portion to define a first region located in the diffusion region, wherein the first region is surrounded by the first guard portion and the intermediate portion And a second guarding portion opposite to the first guard and connected to the other side of the intermediate portion to define a second region of the diffusion region, wherein the second region Formed by the second guard portion and the intermediate portion; a first contact region has a second conductive state and is formed in the first region of the conductive fence structure, and the first contact The region is spaced apart from the first guard and the intermediate portion; and a second contact region has the second conductive state and Formed in the second region of the conductive barrier structure, and the second contact region is spaced from the second guard portion and the intermediate portion. The active component of claim 7, wherein the intermediate portion serves as a gate of the active component, and the intermediate portion has a channel width (W') and along a first direction. The second direction has a channel length (Lg), and the first area and the second area are separated by a distance of the length of the channel; and the active component further comprises: a lightly doped area (light The doping region has the second conductive state, and the lightly doped region extends downward from a surface of the diffusion region and is located within the corresponding conductive barrier structure, wherein the first region and the second region are located in the light a doped region; a first contact is formed in the first contact region, and a second contact is formed in the second contact region, wherein a peripheral region of the active component is surrounded ( The peripheral region is a heavily doped diffusion region of the first conductive state and has no shallow trench isolation (STI). The active element of claim 7, wherein the first area and the second area each have a width W along a first direction, and the first guard and the second guard follow the The first direction has a width W2, and one of the active elements has an effective channel width of W+2×W2. The active component as described in claim 7 is a high voltage (HV) component, wherein the first guard portion and the second guard portion each have a width W2, the first contact region and the second contact The area is separated from the first guard part and the second guard part by a distance d _offset , wherein 2.5×W2 d _offset 5 × W2.