CN111490100A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN111490100A CN111490100A CN202010301464.1A CN202010301464A CN111490100A CN 111490100 A CN111490100 A CN 111490100A CN 202010301464 A CN202010301464 A CN 202010301464A CN 111490100 A CN111490100 A CN 111490100A
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- semiconductor device
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Abstract
一种半导体装置及其制造方法。所述半导体装置包括衬底、通道层、势垒层、一栅极结构,其包含:第一经掺杂III‑V族半导体、III‑V族半导体及导体。通道层设置于所述衬底上。势垒层设置于所述通道层上。第一经掺杂III‑V族半导体设置于所述势垒层上。III‑V族半导体设置于所述经掺杂III‑V族半导体上。导体设置于所述III‑V族半导体上,其中所述第一经掺杂III‑V族半导体之宽度大于所述导体之宽度。
Description
技术领域
本公开系关于一半导体装置及其制造方法,特别系关于具有III-V族半导体之一半导体装置及其制造方法。
背景技术
包括直接能隙(direct bandgap)半导体之组件,例如包括三五族材料或III-V族化合物(Category:III-V compounds)之半导体组件,由于其特性而可在多种条件或环境(例如不同电压、频率)下操作或运作。
上述半导体组件可包括异质接面双极晶体管(heterojunction bipolartransistor,HBT)、异质接面场效晶体管(heterojunction field effect transistor,HFET)、高电子迁移率晶体管(high-electron-mobility transistor,HEMT),或调变掺杂场效晶体管(modulation-doped FET,MODFET)等。
发明内容
本公开的一些实施例提供一种半导体装置,其包括衬底、通道层、势垒层、一栅极结构,其包含:第一经掺杂III-V族半导体、III-V族半导体及导体。通道层设置于所述衬底上。势垒层设置于所述通道层上。第一经掺杂III-V族半导体设置于所述势垒层上。III-V族半导体设置于所述经掺杂III-V族半导体上。导体设置于所述III-V族半导体上,其中所述第一经掺杂III-V族半导体之宽度大于所述导体之宽度。
本公开的一些实施例提供一种制造半导体装置的方法,其包括提供一衬底;形成一通道层于所述衬底上;形成一势垒层于所述通道层上;形成一栅极结构于所述势垒层上,其中形成所述栅极结构包含:形成一第一经掺杂III-V族半导体于所述势垒层上;形成一III-V族半导体于所述第一经掺杂III-V族半导体上;形成一导体于所述III-V族半导体上,其中所述第一经掺杂III-V族半导体之宽度大于所述导体之宽度。
附图说明
当结合附图阅读时,从以下具体实施方式容易理解本公开的各方面。应注意,各个特征可以不按比例绘制。实际上,为了论述清晰起见,可任意增大或减小各种特征的尺寸。
图1所示为根据本案之某些实施例之一半导体装置之截面图;
图2所示为根据本案之某些实施例之一半导体装置之截面图;
图3A、图3B、图3C、图3D、图3E、图3F、图3G及图3H所示为制造根据本案之某些实施例的一半导体装置之若干操作;
图4A为根据本案之某些实施例之半导体装置的电容电压特性图。
图4B为半导体装置的缺陷密度能带图。
图5所示为根据本案之某些实施例之一半导体装置之截面图;
图6所示为根据本案之某些实施例之一半导体装置之截面图;
图7所示为根据本案之某些实施例之一半导体装置之截面图;
图8所示为根据本案之某些实施例之一半导体装置之截面图;
图9所示为根据本案之某些实施例之一半导体装置之截面图。
具体实施方式
以下公开内容提供用于实施所提供的标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例。当然,这些只是实例且并不意欲为限制性的。在本公开中,在以下描述中对第一特征形成在第二特征上或上方的叙述可包含第一特征与第二特征直接接触形成的实施例,并且还可包含额外特征可形成于第一特征与第二特征之间从而使得第一特征与第二特征可不直接接触的实施例。另外,本公开可以在各种实例中重复参考标号和/或字母。此重复是出于简化和清楚的目的,且本身并不规定所论述的各种实施例和/或配置之间的关系。
下文详细论述本公开的实施例。然而,应了解,本公开提供的许多适用概念可实施在多种具体环境中。所论述的具体实施例仅仅是说明性的且并不限制本公开的范围。
III-V族半导体例如氮化镓(GaN)将成为下一代功率半导体。由于III-V族半导体具有更高的击穿强度,更快的开关速度,更高的导热率和更低的导通电阻(on-resistance(Ron)),基于这种宽带隙III-V族半导体材料的功率装置可以大大优于传统的基于硅(Si)的功率芯片。因此,基于GaN的功率装置将在电池充电器、智能手机、计算器、服务器、汽车、照明系统和光伏发电等功率转换市场中发挥关键作用。
图1所示为根据本案之某些实施例之一半导体装置1。
如图1所示,半导体装置1可包括其包括衬底10、晶种层(seed layer)20、缓冲层(buffer layer)30、超晶格电子阻挡层(blocking layer)40、通道层(channel layer)50、势垒层(barrier layer)60、钝化层70、钝化层80、一栅极结构、源极接触92、漏极接触90和导体结构94。栅极结构包含经掺杂III-V族半导体901、III-V族半导体902、经掺杂III-V族半导体903、导体904。
衬底10可包括,例如但不限于,硅(Si)、经掺杂硅(doped Si)、碳化硅(SiC)、硅化锗(SiGe)、砷化镓(GaAs)、或其它半导体材料。衬底10可包括,例如但不限于,蓝宝石(sapphire)、绝缘层上覆硅(silicon on insulator,SOI)或其它适合之材料。
晶种层20设置于衬底10上。在一些实施例中,晶种层20可包括,例如但不限于,金属化合物组成氮化物或氧化物或氮氧化物等,例如氮化钽(TaN)、氮化钛(TiN)、碳化钨(WC)、氮化铝(Al2O3)、氮氧化铝(AlON)等
在一些实施例中,半导体装置1还可包括设置于晶种层20上的缓冲层30。缓冲层30可设置于衬底10和通道层50之间。在一些实施例中,缓冲层30可用以促进衬底10、晶种层20与超晶格电子阻挡层40之间的晶格匹配(lattice match)。在一些实施例中,缓冲层30可包括(但不限于)氮化物(nitrides),例如氮化铝(AlN)、氮化铝镓(AlGaN)等。
半导体装置1还可包括设置于缓冲层30上的超晶格电子阻挡层40。超晶格电子阻挡层40可位于通道层(channel layer)50与衬底10之间。通道层50可包含单一层结构(single-layer structure)。
超晶格电子阻挡层40可包含单一层结构(single-layer structure)。超晶格电子阻挡层40可包括多层结构(multi-layer structure)或复数层堆迭(multi-layer stack),例如AlN/GaN对的复数迭层。在一些实施例中,超晶格电子阻挡层40可降低半导体装置1的张应力(tensile stress)。在一些实施例中,超晶格电子阻挡层40可捕获从衬底10衬底扩散至通道层50的电子,进而提升装置效能与可靠性。
在一些实施例中,超晶格电子阻挡层40可减少电子捕获(electron trap)。在一些实施例中,超晶格电子阻挡层40可提高崩溃电压(breakdown voltage)
由于超晶格电子阻挡层40可阻挡在相对高电压环境中(例如大于200伏(V))所产生晶体缺陷(crystallographic defect)(例如差排(dislocation))的扩散,所以会在半导体装置1设置超晶格电子阻挡层40。
在一些实施例中,半导体装置1还可包括设置于超晶格电子阻挡层40上的通道层50。在一些实施例中,通道层50可包括III-V族层,例如但不限于,III-V族氮化物,例如化合物GaN,GaN可具有约3.4V的能带间隙。信道层50可具有电子通道区域。在一些实施例中,通道层50可包含单一层结构(single-layer structure)。通道层50可包括多层结构(multi-layer structure)。通道层50可包括异质结构。
在一些实施例中,半导体装置1还可包括设置于通道层50上的势垒层60。势垒层60可包括III-V族层。势垒层60可包括,例如但不限于,III族氮化物,例如化合物氮化铝镓(AlxGa1-xN),其中X=0.05~0.3。在一些实施例中,势垒层60可包括其他磊晶成长(epitaxial growth)的氮化物,例如但不限于,氮化铟铝镓(InAlGaN)或氮化铟铝(InAlN)合金。势垒层60可具有较通道层50相对较大之能带间隙(bandgap)。势垒层60的厚度介于,但不限于,约5~50纳米(nm)。
在一些实施例中,半导体装置1还可包括设置于势垒层60上的栅极结构。栅极结构可包含经掺杂III-V族半导体901、III-V族半导体902、经掺杂III-V族半导体903、导体904。经掺杂III-V族半导体901。在一些实施例中,经掺杂III-V族半导体901可包括,例如但不限于,p型掺杂物(dopant)或其他掺杂物。在一些实施例中,经掺杂III-V族半导体901可为P型掺杂氮化镓(GaN)、经掺杂氮化铝镓(doped AlGaN)、经掺杂氮化铟镓(doped InGaN)、及其他经掺杂的III-V族化合物。经掺杂III-V族半导体901可为镁(Mg)掺杂或其他合适掺杂所形成之p型掺杂III-V族半导体。在一些实施例中,经掺杂III-V族半导体901之厚度为约3~80nm。
在一些实施例中,半导体装置1还可包括设置于经掺杂III-V族半导体901上之III-V族半导体902。在一些实施例中,III-V族半导体902之横向宽度与所述第一经掺杂III-V族半导体901之横向宽度大体上相同。在一些实施例中,III-V族半导体902可为氮化铝镓(AlxGa1-xN),其中X=0~1。在一些实施例中,III-V族半导体902之厚度为约1~30nm。
在一些实施例中,半导体装置1还可包括设置于III-V族半导体902上的经掺杂III-V族半导体903。在一些实施例中,经掺杂III-V族半导体903可包括,例如但不限于,p型掺杂物(dopant)或其他掺杂物。在一些实施例中,经掺杂III-V族半导体903可为P型掺杂氮化镓(GaN)、经掺杂氮化铝镓(doped AlGaN)、经掺杂氮化铟镓(doped InGaN)、及其他经掺杂的III-V族化合物。经掺杂III-V族半导体903可为镁掺杂或其他合适掺杂所形成之p型掺杂III-V族半导体。在一些实施例中,经掺杂III-V族半导体903之厚度为约3~80nm。
在一些实施例中,半导体装置1还可包括设置于经掺杂III-V族半导体903上之导体904。在一些实施例中,导体904可包括,例如但不限于,钛(Ti)、钽(Ta)、钨(W)、铝(Al)、钴(Co)、铜(Cu)、镍(Ni)、铂(Pt)、铅(Pb)、钼(Mo)及其化合物(例如但不限于,氮化钛(TiN)、氮化钽(TaN)、其他传导性氮化物(conductive nitrides)、或传导性氧化物(conductiveoxides))、金属合金(例如铝铜合金(Al-Cu))、或其他适当的材料。
在一些实施例中,经掺杂III-V族半导体901之横向宽度大于导体904之横向宽度。在一些实施例中,经掺杂III-V族半导体903设置于III-V族半导体902与导体904之间。在一些实施例中,经掺杂III-V族半导体903之横向宽度与导体904的横向宽度大体上相同。在一些实施例中,经掺杂III-V族半导体901之横向宽度与III-V族半导体902的横向宽度大体上相同。在一些实施例中,经掺杂III-V族半导体901及III-V族半导体902之横向宽度大于经掺杂III-V族半导体903及导体904之横向宽度。
在III-V族半导体装置中,实现低栅极漏电流仍然是一个很大的挑战,降低漏电流可以提高装置的可靠度及改良装置的电性。由于p-GaN及其与钝化层之间的界面品质/质量较差,栅极漏电流路径主要受p-GaN侧壁(例如:III-V族半导体903及901的顶部和相邻部分)的支配。因此,降低栅极漏电流的关键可通过表面清洁或钝化沉积工艺来提高界面质量。
由于III-V族半导体902(例如:氮化铝镓(AlxGa1-xN))与钝化层70的钝化界面更好。因此,在一些实施例中,使用经掺杂III-V族半导体901、III-V族半导体902及III-V族半导体903的迭层可降低栅极漏电流,因为使用III-V族半导体902之结构可以使经掺杂III-V族半导体901及经掺杂III-V族半导体903与钝化层70之间的接触面积变小,进而使半导体装置1的漏电流降低。在一些实施例中,经掺杂III-V族半导体901、经掺杂III-V族半导体903及III-V族半导体902亦可使用其他适合的III-V族半导体替换。
在一些实施例中,半导体装置1还可包括源极(source)接触92、漏极(drain)接触90和导体结构94。源极接触92和漏极接触90设置于通道层50上,并且分别地设置在导体904和导体结构94的两侧,但源极接触92与漏极接触90可因设计需求而在本案其它实施例中有不同的配置。导体结构94设置于导体904上。
在一些实施例中,源极接触92、漏极接触90和导体结构94可包括,例如但不限于,导体材料。导体材料可包括,例如但不限于,金属、合金、经掺杂半导体材料(例如经掺杂多晶硅(doped crystalline silicon))或其它合适的导体材料。
在一些实施例中,半导体装置1还可包括设置于势垒层60上的钝化层70。钝化层70可覆盖(cover)势垒层60。在一些实施例中,钝化层70覆盖经掺杂III-V族半导体901、III-V族半导体902、经掺杂III-V族半导体903、导体904及导体结构94。在一些实施例中,钝化层70可围绕(surround)源极接触92、漏极接触90和导体结构94的一部分。
在一些实施例中,钝化层70可包括,例如但不限于,氧化物(oxides)或氮化物(nitrides),例如氮化硅(Si3N4)、氧化硅(SiO2)等。钝化层70可包括,例如但不限于,氧化物及氮化物之复合层,例如Al2O3/SiN、Al2O3/SiO2、AlN/SiN、AlN/SiO2等。
在一些实施例中,半导体装置1还可包括设置于钝化层70上的钝化层80。在一些实施例中,钝化层80可覆盖钝化层70。在一些实施例中,钝化层80可覆盖源极接触92、漏极接触90和导体结构94的一部分。在一些实施例中,钝化层80可围绕源极接触92、漏极接触90和导体结构94的一部分。在一些实施例中,钝化层80可包括,例如但不限于,氧化物(oxides)或氮化物(nitrides),例如氮化硅(Si3N4)、氧化硅(SiO2)等。钝化层80可包括,例如但不限于,氧化物及氮化物之复合层,例如Al2O3/SiN、Al2O3/SiO2、AlN/SiN、AlN/SiO2等。
图2所示为根据本案之某些实施例之一半导体装置2。
图2所示的半导体装置2可与图1所示的半导体装置1相同或相似,其中之一的不同在于:半导体装置2的经掺杂III-V族半导体903'设置于势垒层60上且导体904及设置于经掺杂III-V族半导体903'上。
如图2所示,经掺杂III-V族半导体903'之横向宽度大于导体904之横向宽度。在一些实施例中,半导体装置2不包括经掺杂III-V族半导体901及III-V族半导体902。钝化层70可覆盖经掺杂III-V族半导体903'及导体904。
图2所示的半导体装置2相较于图1所示的半导体装置1具有较高的漏电流。如图2中箭头所示,栅极的漏电流会从导体904的边缘流经经掺杂III-V族半导体903'与钝化层70的接口,最后抵达势垒层60。
漏电流现象是由较差的界面质量所造成,亦是因为经掺杂III-V族半导体903具有更高的GaO/GaN比。使用氮化铝镓(AlxGa1-xN)代替部分经掺杂III-V族半导体903(例如:P型掺杂氮化镓(GaN))可以相对减少Ga-O的形成。使用氮化铝镓(AlxGa1-xN)将具有更多的Al-O,而Al-O可以更好地化学键合到界面性质,进而减少界面的漏电流。
相较之下,如图1所示的半导体装置1的III-V族半导体902(例如:氮化铝镓(AlxGa1-xN))的钝化界面具有较少的缺陷。因此,在经掺杂III-V族半导体901和903中间加入一层III-V族半导体902将可有效降低栅极的漏电流。
图3A、图3B、图3C、图3D、图3E、图3F、图3G及图3H所示为制造根据本案之某些实施例的一半导体装置之若干操作。虽然图3A至3H系描绘制造半导体装置1之若干操作,但相似的操作亦可用于制造半导体装置2或半导体装置5~9。
参照图3A,提供衬底10。在一些实施例中,在衬底10上形成晶种层20。在一些实施例中,在晶种层20上形成缓冲层30。晶种层20及缓冲层30可透过以下方式形成:有机金属化学气相沉积(metal organic chemical vapor deposition,MOCVD)磊晶成长(epitaxialgrowth)。在一些实施例中,超晶格电子阻挡层40形成于缓冲层30上。在一些实施例中,经由磊晶成长(epitaxial growth)在超晶格电子阻挡层40上设置通道层50。在势垒层60设置通道层50上。势垒层60例如可透过有机金属化学气相沉积(metal organic chemical vapordeposition,MOCVD)磊晶成长(epitaxial growth)或其他适当的沉积步骤形成。
在经掺杂III-V族半导体901a上形成势垒层60上。在半导体层902a上形成经掺杂III-V族半导体901a上。在经掺杂III-V族半导体903a上形成半导体层902a上。在一些实施例中,经掺杂III-V族半导体901a、半导体层902a及经掺杂III-V族半导体903a可透过以下方式形成:有机金属化学气相沉积(metal organic chemical vapor deposition,MOCVD)磊晶成长(epitaxial growth),并将掺杂物掺杂其中。
参照图3B,导体层904a及硬掩模(hard mask)41形成于经掺杂III-V族半导体903a上。导体层904a可透过物理气相沉积(physical vapor deposition,PVD)、化学气相沉积(chemical vapor deposition,CVD)、原子层沉积(atomic layer deposition,ALD)、电镀(plating)、及/或其他适当的沉积步骤形成。在一些实施例中,硬掩模41可包括,但不限于,氮化硅(Si3N4)、氮氧化硅(SiON)、碳化硅(SiC)等。硬掩模41用于透过黄光微影(photolithography)、蚀刻(etching)等制程而图案化经掺杂III-V族半导体903a及导体层904a。在一些实施例中,可使用干式蚀刻(dry etching)、湿式蚀刻(wet etching)、或干式与湿式蚀刻的组合进行蚀刻步骤。
参照图3C,在半导体层902a上方可透过如黄光微影的方式移除部分经掺杂III-V族半导体903a及导体层904a之后,形成经掺杂III-V族半导体903及导体904。
参照图3D,在硬掩模41、经掺杂III-V族半导体903a及导体层904a两侧形成图案化光阻42遮盖半导体层902a。移除部分经掺杂III-V族半导体901a及半导体层902a之后,形成经掺杂III-V族半导体901及III-V族半导体902。由于图案化光阻42的缘故,经掺杂III-V族半导体901及III-V族半导体902的宽度较经掺杂III-V族半导体903a及导体层904a要宽。
参照图3E,移除硬掩模41及图案化光阻42之后,形成钝化层70覆盖经掺杂III-V族半导体901、III-V族半导体902、经掺杂III-V族半导体903及导体904。
参照图3F,在钝化层70及势垒层60中形成源极接触孔洞与漏极接触孔洞,并填入材料,形成源极接触92与漏极接触90。在一些实施例中,这涉及复数步骤,包括黄光微影(photolithography)、蚀刻(etching)、及沉积(deposition)等步骤。在一些实施例中,源极接触92与漏极接触90可透过物理气相沉积(physical vapor deposition,PVD)、化学气相沉积(chemical vapor deposition,CVD)、原子层沉积(atomic layer deposition,ALD)、电镀(plating)、及/或其他适当的沉积步骤形成。
参照图3G,形成钝化层80覆盖经掺杂III-V族半导体901、III-V族半导体902、经掺杂III-V族半导体903及导体904。在一些实施例中,钝化层80可透过以下方式沉积:CVD、高密度电浆(high density plasma,HDP)CVD、旋转涂布(spin-on)、喷溅(sputtering)等。接着以化学机械平坦化(Chemical-Mechanical Planarization,CMP)处理钝化层80表面
参照图3H,在钝化层80及70中形成源极接触孔洞与漏极接触孔洞,并填入材料,形成源极接触92、漏极接触90及导体结构94。在一些实施例中,源极接触92、漏极接触90及导体结构94可具有相同的材料。在一些实施例中,这涉及复数步骤,包括黄光微影(photolithography)、蚀刻(etching)、及沉积(deposition)等步骤。源极接触92、漏极接触90及导体结构94形成之后,完成半导体装置1之制程。
在形成钝化层70之前,可以对势垒层60的上表面、经掺杂III-V族半导体901、III-V族半导体902的侧壁及部分上表面、及经掺杂III-V族半导体903的侧壁实施预处理(pretreatment)。
表一
样本 | 预处理 | V<sub>TH</sub>(V) | ΔV<sub>1</sub>(V) | ΔV<sub>2</sub>(V) | Ga-O(N)/Ga-N(%) |
A | 天然氧化物 | -10.5 | 0 | 0.13 | 8.7 |
B | 氧退火 | -7.2 | 0.08 | 0.67 | 48.7 |
C | N2等离子体 | -8.7 | 0.7 | 0.2 | 8.7 |
D | FG等离子体 | -8.1 | 0.5 | 0.18 | 5.3 |
表一为实施不同预处理(pretreatment)后的电性表现。在一些实施例中,预处理包括氧退火(annealed)预处理或N2、FG等离子体(电浆)(plasma)预处理。由表一可知,经过不同预处理后,样本的表面缺陷密度也会有不同,其中样本D经预处理方式过后在接口形成最少的Ga-O,因此接口缺陷也最少。在某些实施例中,预处理可在图3C或图3D中之操作时实施。
图4A为根据本案之某些实施例之半导体装置的电容电压特性图。详细来说,图4A为对应表一中实施预处理后半导体装置的电容电压特性图。图4A中所示之样本A特性图为针对势垒层60上表面、经掺杂III-V族半导体901/III-V族半导体902的侧壁、及经掺杂III-V族半导体903的侧壁仅使用天然氧化物处理的电容电压特性图。图4A中所示之样本B特性图为针对势垒层60上表面、经掺杂III-V族半导体901/III-V族半导体902的侧壁、及经掺杂III-V族半导体903的侧壁实施氧退火预处理。图4A中所示之样本C特性图为针对势垒层60上表面、经掺杂III-V族半导体901/III-V族半导体902的侧壁、及经掺杂III-V族半导体903的侧壁实施N2等离子体预处理。图4A中所示之样本D特性图为针对势垒层60上表面、经掺杂III-V族半导体901/III-V族半导体902的侧壁、及经掺杂III-V族半导体903的侧壁实施FG等离子体预处理。
由图4A中各样本特性图可看出,在不同频率时,VTH在电压为0以上时,当频率不同时是否有较大的分散或差异(dispersion)。图4A之样本D特性图可看出,频率从50kHz到400kHz的范围内使用FG等离子体预处理的半导体装置具有较小的分散(dispersion),表示使用FG等离子体预处理的半导体装置的势垒层60上表面、经掺杂III-V族半导体901/III-V族半导体902的侧壁、及经掺杂III-V族半导体903的侧壁具有较少的缺陷。Ga-O的键结相对Al-O的键结较不稳定(Ga2O3相对Al2O3自由能高所以比较不稳定)。因此,具有Al-O的界面相对具有G-O的的界面,缺陷比较少,因此,半导体装置中G-O的量越少,其电性越好。在一些实施例中,Ga-O(N)/Ga-N之比率(及Ga-O)在上述势垒层60、经掺杂III-V族半导体901/III-V族半导体902及经掺杂III-V族半导体903各界面的量越少,表示各界面中的缺陷越少。
图4B为半导体装置的缺陷密度(Dit)能带图。在一些实施例中,图4B为对应图4A中半导体装置的缺陷密度。图4B是依据图4A的电容电压结果所计算出来对应于GaN bandenergy里缺陷的密度。不同的样本中的缺陷密度(Dit)不同,缺陷密度数值越低,则半导体装置的电性表现越好。同样地,由图4B显示样本D的缺陷密度最低
图5所示为根据本案之某些实施例之一半导体装置5。
图5所示的半导体装置5可与图1所示的半导体装置1相似,其中之一的不同在于:半导体装置5的导体904'、经掺杂III-V族半导体903"、III-V族半导体902和经掺杂III-V族半导体901的横向宽度大体上相同。
图6所示为根据本案之某些实施例之一半导体装置6。
图6所示的半导体装置6可与图1所示的半导体装置1相似,其中之一的不同在于:经掺杂III-V族半导体903'"之横向宽度大于导体904之横向宽度。
图7所示为根据本案之某些实施例之一半导体装置7。
图7所示的半导体装置7可与图1所示的半导体装置1相同或相似,其中之一的不同在于:半导体装置7的导体941的形状和图1不同,且III-V族半导体903之横向宽度大于导体941底部的宽度。此外,钝化层70围绕导体941之一部分且钝化层80围绕导体941之一部分。导体941之一部分设置在钝化层80的上表面上。
图8所示为根据本案之某些实施例之一半导体装置8。
图8所示的半导体装置8可与图1所示的半导体装置1相似,其中之一的不同在于:经掺杂III-V族半导体903"之横向宽度与III-V族半导体902之横向宽度大体上相同,且经掺杂III-V族半导体903"之横向宽度大于导体904之横向宽度。
图9所示为根据本案之某些实施例之一半导体装置9。
图9所示的半导体装置9可与图1所示的半导体装置1相同或相似,其中之一的不同在于:半导体装置9不包括经掺杂III-V族半导体903。导体904直接设置在III-V族半导体902上。
图1、2及6-9的实施例中,III-V族半导体、经掺杂III-V族半导体、以及导体具有相同或不同的横向宽度,由于III-V族半导体、经掺杂III-V族半导体、以及导体的边缘并非完全对齐,这使得栅极漏电流路径被延长,进而减少漏电流的状况。此外,由于III-V族半导体的表面缺陷较经掺杂III-V族半导体要少,藉由在漏电流路径上安排较多的III-V族半导体的表面,可减少整体漏电流路径的表面缺陷,并且进一步改善漏电流的状况。
如本文中所使用,为易于描述可在本文中使用空间相对术语例如“下面”、“下方”、“下部”、“上方”、“上部”、“下部”、“左侧”、“右侧”等描述如图中所说明的一个组件或特征与另一组件或特征的关系。除图中所描绘的定向之外,空间相对术语意图涵盖在使用或操作中的装置的不同定向。设备可以其它方式定向(旋转90度或处于其它定向),且本文中所使用的空间相对描述词同样可相应地进行解释。应理解,当一组件被称为“连接到”或“耦合到”另一组件时,其可直接连接或耦合到所述另一组件,或可存在中间组件。
如本文中所使用,术语“大约”、“基本上”、“大体”以及“约”用以描述和考虑小的变化。当与事件或情形结合使用时,所述术语可以指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。如在本文中相对于给定值或范围所使用,术语“约”通常意指在给定值或范围的±10%、±5%、±1%或±0.5%内。范围可在本文中表示为从一个端点到另一端点或在两个端点之间。除非另外指定,否则本文中所公开的所有范围包括端点。术语“基本上共面”可指在数微米(μm)内沿同一平面定位,例如在10μm内、5μm内、1μm内或0.5μm内沿着同一平面的的的两个表面。当参考“基本上”相同的数值或特征时,术语可指处于所述值的平均值的±10%、±5%、±1%或±0.5%内的值。
前文概述本公开的若干实施例和细节方面的特征。本公开中描述的实施例可容易地用作用于设计或修改其它过程的基础以及用于执行相同或相似目的和/或获得引入本文中的实施例的相同或相似优点的结构。这些等效构造不脱离本公开的精神和范围并且可在不脱离本公开的精神和范围的情况下作出不同变化、替代和改变。
Claims (23)
1.一种半导体装置,包含:
一衬底;
一通道层,设置于所述衬底上;
一势垒层,设置于所述通道层上;
一栅极结构,其包含:
一第一经掺杂III-V族半导体,设置于所述势垒层上;
一III-V族半导体,设置于所述第一经掺杂III-V族半导体上;
一导体,设置于所述III-V族半导体上,其中所述第一经掺杂III-V族半导体之宽度大于所述导体之宽度。
2.根据权利要求1所述的半导体装置,其中所述栅极结构另包含:
一第二经掺杂III-V族半导体,设置于所述III-V族半导体与所述导体之间。
3.根据权利要求2所述的半导体装置,其中所述所述第二经掺杂III-V族半导体之宽度与所述导体的宽度大体上相同。
4.根据权利要求2所述的半导体装置,其中所述第二经掺杂III-V族半导体之宽度与所述第一经掺杂III-V族半导体的宽度大体上相同。
5.根据权利要求1所述的半导体装置,其中所述III-V族半导体之宽度与所述导体之宽度大体上相同。
6.根据权利要求1所述的半导体装置,其中所述III-V族半导体之宽度与所述第一经掺杂III-V族半导体之宽度大体上相同。
7.根据权利要求1-6中任一项所述的半导体装置,其中所述势垒层是氮化铝镓(AlxGa1- xN),其中X=0.05~0.3。
8.根据权利要求1-6中任一项所述的半导体装置,其中所述势垒层之厚度为约5~50纳米(nm)。
9.根据权利要求1-6中任一项所述的半导体装置,其中所述第一经掺杂III-V族半导体之厚度为约3~80nm。
10.根据权利要求2-6中任一项所述的半导体装置,其中所述第二经掺杂III-V族半导体之厚度为约3~80nm。
11.根据权利要求1-6中任一项所述的半导体装置,其中所述III-V族半导体是氮化铝镓(AlxGa1-xN),其中X=0~1。
12.根据权利要求1-6中任一项所述的半导体装置,其中所述III-V族半导体之厚度为约1~30nm。
13.根据权利要求1-6中任一项所述的半导体装置,其中所述第一经掺杂III-V族半导体为P型掺杂氮化镓(GaN)。
14.根据权利要求2-6中任一项所述的半导体装置,其中所述第二经掺杂III-V族半导体为P型掺杂氮化镓。
15.根据权利要求1-6中任一项所述的半导体装置,更包括一源极接触和一汲极接触,设置于所述通道层上。
16.根据权利要求1-6中任一项所述的半导体装置,更包括一电子阻挡层,设置于所述衬底和所述通道层之间。
17.根据权利要求1-6中任一项所述的半导体装置,更包括一缓冲层,设置于所述衬底和所述通道层之间。
18.根据权利要求1-6中任一项所述的半导体装置,更包括一钝化层,设置于所述势垒层上,并且覆盖所述第一经掺杂III-V族半导体、所述III-V族半导体及所述导体。
19.一种制造一半导体装置的方法,包含:
提供一衬底;
形成一通道层于所述衬底上;
形成一势垒层于所述通道层上;
形成一栅极结构于所述势垒层上,其中形成所述栅极结构包含:
形成一第一经掺杂III-V族半导体于所述势垒层上;形成一III-V族半导体于所述第一经掺杂III-V族半导体上;
形成一导体于所述III-V族半导体上,其中所述第一经掺杂III-V族半导体之宽度大于所述导体之宽度。
20.根据权利要求19所述的方法,其中形成所述栅极结构另包含:
形成一第二经掺杂III-V族半导体于所述III-V族半导体与所述导体之间。
21.根据权利要求19-20中任一项所述的方法,其另包含:
形成一电子阻挡层于所述衬底和所述通道层之间。
22.根据权利要求19-20中任一项所述的方法,其另包含:
形成一缓冲层于所述衬底和所述通道层之间。
23.根据权利要求19-20中任一项所述的方法,其另包含:
形成一钝化层于所述势垒层上,并且覆盖所述第一经掺杂III-V族半导体、所述III-V族半导体及所述导体。
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CN112740418A (zh) * | 2020-12-14 | 2021-04-30 | 英诺赛科(苏州)科技有限公司 | 半导体装置和其制造方法 |
CN113871479A (zh) * | 2021-09-07 | 2021-12-31 | 南方科技大学 | 晶体管结构及其制备方法 |
CN114616679A (zh) * | 2021-04-12 | 2022-06-10 | 英诺赛科(苏州)科技有限公司 | 半导体器件及其制造方法 |
WO2023066439A1 (en) * | 2021-10-18 | 2023-04-27 | Huawei Technologies Co., Ltd. | Transistor devices, power devices, and method of manufacturing thereof |
TWI804035B (zh) * | 2021-05-28 | 2023-06-01 | 韓商艾維工程股份有限公司 | Iii-n半導體結構及其製造方法 |
TWI832491B (zh) * | 2022-10-14 | 2024-02-11 | 力晶積成電子製造股份有限公司 | 半導體結構及其形成方法 |
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US20210327850A1 (en) | 2021-10-21 |
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