CN111490023A - 具有结合焊盘的半导体器件 - Google Patents
具有结合焊盘的半导体器件 Download PDFInfo
- Publication number
- CN111490023A CN111490023A CN201910948277.XA CN201910948277A CN111490023A CN 111490023 A CN111490023 A CN 111490023A CN 201910948277 A CN201910948277 A CN 201910948277A CN 111490023 A CN111490023 A CN 111490023A
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- Prior art keywords
- bonding
- layer
- interconnect
- pad
- semiconductor device
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Abstract
一种半导体器件,包括:第一半导体芯片,所述第一半导体芯片具有第一结合层;以及第二半导体芯片,所述第二半导体芯片堆叠在所述第一半导体芯片上,并且具有第二结合层。所述第一结合层包括第一结合焊盘、多个第一内部通路以及连接所述第一结合焊盘和所述多个第一内部通路的第一互连。所述第二结合层包括结合到所述第一结合焊盘的第二结合焊盘。所述第一互连的上表面和所述第一结合焊盘的上表面与所述第一结合层的上表面共面。所述第一互连通过所述多个第一内部通路电连接到多条不同的第一内部线。
Description
相关申请的交叉引用
本申请要求2019年1月28日提交的韩国专利申请No.10-2019-0010373的优先权,该韩国申请的全部公开内容以引用的方式合并于本申请中。
技术领域
本文描述的实施例涉及具有结合焊盘的半导体器件。
背景技术
在半导体加工过程中,可以将晶片彼此结合以获得高度集成的半导体器件。当晶片彼此结合时,形成在晶片上的结合焊盘连接到晶片的互连,因此可以使用再分布层来连接结合焊盘和互连。
发明内容
本发明构思的示例实施例涉及提供在结合层的结合界面处具有结合焊盘和互连的半导体器件。
根据示例实施例,一种半导体器件包括:第一半导体芯片,所述第一半导体芯片包括第一衬底、在所述第一衬底上并且包括多条第一内部线的第一电路层以及在所述第一电路层上的第一结合层;以及第二半导体芯片,所述第二半导体芯片堆叠在所述第一半导体芯片上,并且包括第二衬底、在所述第二衬底下方的第二电路层以及在所述第二电路层下方的第二结合层,其中所述第一结合层包括第一结合焊盘、多个第一内部通路以及电连接所述第一结合焊盘和所述多个第一内部通路的第一互连,所述第二结合层包括结合到所述第一结合焊盘的第二结合焊盘,所述第一互连的上表面和所述第一结合焊盘的上表面与所述第一结合层的上表面共面,并且所述第一互连通过所述多个第一内部通路电连接到所述多条不同的第一内部线。
根据示例实施例,一种半导体器件包括:第一半导体芯片,所述第一半导体芯片包括第一衬底、在所述第一衬底上的第一电路层以及在所述第一电路层上的第一结合层;以及第二半导体芯片,所述第二半导体芯片堆叠在所述第一半导体芯片上,并且包括第二衬底、在所述第二衬底下方并且包括多条第二内部线的第二电路层以及在所述第二电路层下方的第二结合层,其中所述第一结合层包括多个第一结合焊盘以及连接所述多个第一结合焊盘的第一互连,所述第二结合层包括多个第二结合焊盘以及连接所述多个第二结合焊盘和多个第二内部通路的第二互连,其中所述第二结合焊盘结合到所述多个第一结合焊盘,所述第二互连的下表面与所述第二结合焊盘的相应下表面共面,并且所述多个第二结合焊盘通过所述多个第二内部通路连接到所述多条不同的第二内部线。
根据示例实施例,一种半导体器件包括:第一半导体芯片,所述第一半导体芯片包括第一衬底、多条第一内部线以及在所述多条第一内部线上的第一结合层;以及第二半导体芯片,所述第二半导体芯片堆叠在所述第一半导体芯片上,并且包括第二衬底以及在所述第二衬底下方的第二结合层,其中所述第一结合层包括第一结合焊盘、至少一个非结合焊盘以及连接所述第一结合焊盘和所述至少一个非结合焊盘的第一互连,所述第二结合层包括结合到所述第一结合焊盘的第二结合焊盘,所述第一互连的上表面和所述第一结合焊盘的上表面与所述第一结合层的上表面共面,在平面图中,所述至少一个非结合焊盘的宽度大于所述第一互连的宽度,并且小于所述第一结合焊盘的宽度,并且所述第一互连通过所述至少一个非结合焊盘连接到所述多条第一内部线。
附图说明
图1是根据示例实施例的半导体器件的横截面视图。
图2是图1中所例示的半导体器件的局部放大横截面视图。
图3例示了图1中所例示的半导体器件的第一结合层和第二结合层的平面图。
图4例示了根据示例实施例的半导体器件的第一结合层和第二结合层的平面图。
图5和图6是根据示例实施例的半导体器件的横截面视图。
图7是根据示例实施例的半导体器件的横截面视图。
图8是图7中所例示的半导体器件的局部放大横截面视图。
图9例示了图7中所例示的半导体器件的第一结合层和第二结合层的平面图。
图10至图16是根据示例实施例的半导体器件的第一结合层和第二结合层的平面图。
图17和图18是根据示例实施例的半导体器件的横截面视图。
具体实施方式
图1是根据示例实施例的半导体器件的横截面视图。图2是图1中所例示的半导体器件的局部放大横截面视图。图3例示了图1中所例示的半导体器件的第一结合层和第二结合层的平面图。具体而言,图3例示了图1中所例示的第一结合层的俯视图和图1中所例示的第二结合层的仰视图。本文使用的术语第一、第二、第三等仅仅是为了将一个元件与另一个元件区分或区别开。
参照图1和图2,半导体器件可以包括第一半导体芯片100和第二半导体芯片200。第二半导体芯片200堆叠在第一半导体芯片100上,并且可以物理地电连接到第一半导体芯片100。
第一半导体芯片100可以包括第一衬底102、第一电路层110和第一结合层140。第一衬底102可以包括硅、硅锗、碳化硅、氧化硅或其组合。
第一电路层110可以包括第一元件层120和第一互连层130。第一元件层120可以包括内部线121、层间绝缘层125、接触C1和栅极结构TR1。内部线121可以设置在第一元件层120中以电连接到第一互连层130。栅极结构TR1可以设置在第一衬底102的上表面上。第一衬底102可以在其上表面上包括杂质区。杂质区可以设置在栅极结构TR1的两侧。内部线121可以通过接触C1电连接到杂质区。层间绝缘层125可以在内部线121、接触C1和栅极结构TR1上延伸,或者覆盖内部线121、接触C1和栅极结构TR1。如本文所用,覆盖另一元件或表面的元件可以部分地或完全地覆盖该另一元件或表面。内部线121和接触C1可以包括钨、钴、铜或铝。虽然未示出,但是第一元件层120还可以包括覆盖内部线121和接触C1的阻挡膜。层间绝缘层125可以包括氧化硅、氮化硅、氮氧化硅或其组合。
第一互连层130可以包括多个层。例如,第一互连层130的每个层可以具有堆叠有内部线131和132以及层间绝缘层135的结构。第一互连层130可以包括通路137,位于不同层的内部线通过通路137电连接。第一互连层130的内部线131可以电连接到第一元件层120的内部线121。内部线131和132以及通路137可以包括钨、铜、钴、钌、钼或铝。第一互连层130还可以包括覆盖内部线131和132以及通路137的阻挡膜。层间绝缘层135可以包括氧化硅、氮化硅、氮氧化硅、低K介电材料或其组合。
第二半导体芯片200可以包括第二衬底202、第二电路层210和第二结合层240。第二电路层210可以包括第二元件层220和第二互连层230。第二元件层220可以包括内部线221、层间绝缘层225、接触C2和栅极结构TR2。第二互连层230可以包括内部线211和层间绝缘层235。
第一半导体芯片100和第二半导体芯片200可以是不同类型的半导体芯片,即,第一半导体芯片100和第二半导体芯片200可以是包括不同结构和配置的半导体芯片。在一些实施例中,第一半导体芯片100可以是逻辑芯片,第二半导体芯片200可以是包括逻辑芯片100中不存在的存储结构(例如,位线、字线等)的存储芯片。在一些实施例中,第一半导体芯片100可以是逻辑芯片,第二半导体芯片200可以是包括逻辑芯片100中不存在的像素结构(例如,光电转换区域)的像素阵列芯片。在一些实施例中,第一半导体芯片100和第二半导体芯片200可以是相同类型的半导体芯片。
参照图2和图3,第一结合层140和第二结合层240可以沿着结合界面或表面S彼此结合。第一结合层140可以包括第一界面绝缘层142、层间绝缘层144和结合结构150。第一结合层140还可以包括阻挡膜146和内部通路V1、V2和V3。
第一界面绝缘层142可以设置在第一结合层140的上表面上,并且可以部分地覆盖结合结构150的侧表面。例如,第一界面绝缘层142可以设置在层间绝缘层144的上表面上,并且第一界面绝缘层142可以在层间绝缘层144上延伸。第一界面绝缘层142的上表面和结合结构150的上表面可以彼此共面。例如,第一界面绝缘层142的上表面和结合结构150的上表面可以位于与结合表面S相同的高度水平。
层间绝缘层144可以位于第一界面绝缘层142的下方,并且可以覆盖结合结构150和内部通路V1、V2和V3。层间绝缘层144可以保护结合结构150和内部通路V1、V2和V3并使他们电绝缘。阻挡膜146可以覆盖结合结构150的侧表面和下表面。阻挡膜146也可以设置在内部通路V1、V2和V3以及内部线131和132的侧表面上。
第一界面绝缘层142可以包括SiO2、SiCN、SiC、SiON或其组合。层间绝缘层144可以包括SiO2、SiN、低K介电材料或其组合。例如,设置在包括SiO2或SiN的层间绝缘层144上的第一界面绝缘层142可以包括SiO2、SiCN、SiC、SiON或者包括SiO2、SiCN、SiC和SiON的多层结构。
结合结构150可以包括结合焊盘BP和互连L1。结合焊盘BP被例示为具有圆形形状,但不限于此,并且可以具有多边形或四边形形状、具有圆角的多边形或四边形形状等。互连L1可以连接结合焊盘BP和内部通路V1、V2和V3。在一些实施例中,互连L1可以形成为当从上方观察时穿过结合焊盘BP。在一些实施例中,互连L1可以连接到结合焊盘BP的一侧。结合焊盘BP和互连L1可以通过镶嵌工艺形成。在一些实施例中,在形成内部通路V1、V2和V3之后,可以通过单镶嵌工艺形成结合焊盘BP和互连L1。阻挡膜146也可以设置在互连L1与内部通路V1、V2和V3之间。在一些实施例中,结合焊盘BP、互连L1和内部通路V1、V2和V3可以通过双镶嵌工艺形成。
在一些实施例中,内部通路V1、V2和V3可以在横向方向上与结合焊盘BP间隔开,并且可以设置在互连L1的下方。在一些实施例中,内部通路V1、V2和V3可以设置在结合焊盘BP的下方。图3例示了互连L1连接到多个内部通路V1、V2和V3,但是在一些实施例中,互连L1可以连接到更少的内部通路或一个内部通路。在平面图中,互连L1的宽度W1可以小于结合焊盘BP的宽度W2。结合焊盘BP的宽度W2可以在约0.2μm至约2.5μm的范围内。
结合焊盘BP、互连L1和内部通路V1、V2和V3可以包括金属。在一些实施例中,结合焊盘BP、互连L1和内部通路V1、V2和V3可以包括Cu、Al、Co或其组合。阻挡膜146可以包括TaN、Ta、Ti、TiN、Mn、MnN或其组合。可以在结合焊盘BP和互连L1上设置包括Mn、Co、Ru、Sn、CoWP、Au、Pt、Ni或其组合的膜。
第二结合层240可以包括第二界面绝缘层242、层间绝缘层244和结合焊盘BP'。第二结合层240还可以包括阻挡膜246。第二界面绝缘层242可以包括与第一界面绝缘层142相同的材料,并且层间绝缘层244可以包括与层间绝缘层144相同的材料。结合焊盘BP'可以包括与结合焊盘BP相同的材料。第一界面绝缘层142和第二界面绝缘层242可以设置在结合表面S上,以增加第一半导体芯片100与第二半导体芯片200之间的附着。例如,第二界面绝缘层242可以设置在第二结合层240的下表面上,并且第二界面绝缘层242可以在层间绝缘层244上延伸。另外,第二界面绝缘层242可以防止不与结合焊盘BP'接触的互连L1的金属材料扩散到层间绝缘层244中。
结合焊盘BP可以结合到结合焊盘BP'。互连L1可以设置在第一结合层140的上表面上以执行布线(routing)。例如,结合到结合焊盘BP'的结合焊盘BP可以通过互连L1电连接到一个或更多个内部通路。结合焊盘BP可以通过互连L1电连接到内部通路V1、V2和V3。因此,结合焊盘BP可以电连接到不同的内部线131和132。图3例示了结合结构150包括在第一结合层140中,但是实施例不限于此。在一些实施例中,类似地,可以在第二结合层240的下表面上设置包括互连的结合结构。
如图1至图3所例示,结合焊盘BP和互连L1设置在第一半导体芯片100的第一结合层140的结合表面S上,因此可以在结合表面S上执行结合功能和互连功能。即使当结合焊盘BP和结合焊盘BP'未对准(例如,沿着结合表面S偏离期望的重叠)而彼此结合时,可以通过互连L1确保接触区域,从而降低结合风险。由于结合焊盘BP和结合焊盘BP'未被配置为用于一对一结合,所以第一半导体芯片100和第二半导体芯片200可以以结合焊盘BP和互连L1的各种图案彼此结合。
图4例示了根据示例实施例的半导体器件的第一结合层和第二结合层的平面图。
参照图4,第一结合层140a可以包括结合结构150a。在平面图中,互连L1可以具有突出部分。在一些实施例中,在平面图中,突出部分的宽度W3可以大于互连L1的宽度W1。突出部分不连接到结合焊盘BP',并且可以被称为非结合焊盘NBP1、NBP2和NBP3。非结合焊盘NBP1、NBP2和NBP3可以通过双镶嵌工艺与结合焊盘BP和互连L1一起形成。在一些实施例中,在平面图中,非结合焊盘NBP的宽度W3可以小于结合焊盘BP的宽度W2。
第二结合层240a可以包括结合焊盘BP'。结合焊盘BP'可以连接到结合焊盘BP。在平面图中,结合焊盘BP'的宽度W4可以不同于结合焊盘BP的宽度W2。在一些实施例中,结合焊盘BP'的宽度W4可以大于结合焊盘BP的宽度W2。在一些实施例中,结合焊盘BP'的宽度W4可以小于结合焊盘BP的宽度W2。
图5和图6是根据示例实施例的半导体器件的横截面视图。
参照图5,半导体器件可以包括第一半导体芯片100和第二半导体芯片200b。在一些实施例中,第二半导体芯片200b可以是背部光接收图像传感器。第二半导体芯片200b可以包括光电转换部或区域PD、钝化层250、色彩滤光片252和微透镜254。光电转换部PD可以设置在第二衬底202的内部。钝化层250可以设置在第二衬底202上。色彩滤光片252和微透镜254可以设置在钝化层250上。
光电转换部PD可以包括包含诸如磷(P)或砷(As)的n型杂质离子的n型区域以及包含诸如硼(B)的p型杂质离子的p型区域。光电转换部PD可以包括光电二极管、光电晶体管、光电门、钉扎光电二极管或其组合。
钝化层250可以包括氧化硅、氮化硅、氮氧化硅或其他绝缘材料。色彩滤光片252和微透镜254可以包括聚合材料。在一些实施例中,钝化层250可以包括抗反射层。
多个色彩滤光片252可以以包括针对每个单位像素的红色滤光片R、绿色滤光片G或蓝色滤光片B的拜耳图案来实现。可见区域的波长中的红色区域的波长可以穿过红色滤光片R。可见区域的波长中的绿色区域的波长可以穿过绿色滤光片G。可见区域的波长中的蓝色区域的波长可以穿过蓝色滤光片B。在一些实施例中,多个色彩滤光片252可以包括青色滤光片、品红色滤光片或黄色滤光片。多个色彩滤光片252还可以包括白色滤光片。
参照图6,半导体器件可以包括第一半导体芯片100和第二半导体芯片200c。第二半导体芯片200c可以包括第二衬底202、第二电路层210和第二结合层240。第二电路层210可以包括第二元件层220和第二互连层230。第二元件层220可以包括内部线221和222。第二半导体芯片200c还可以包括穿硅通路(through silicon via)TSV1。穿硅通路TSV1可以形成为从第二衬底202的上表面开始部分地穿过第二衬底202和第二元件层220。顶焊盘TP可以设置在穿硅通路TSV1的上表面上。穿硅通路TSV1的下表面可以连接到内部线222。钝化层250可以设置在第二衬底202的表面上并且可以覆盖顶焊盘TP的一部分。
尽管未示出,但是第二半导体芯片200c还可以包括覆盖穿硅通路TSV1的阻挡膜。顶焊盘TP和穿硅通路TSV1和TSV2可以包括Cu、CuSn、CuMg、CuNi、CuZn、CuPd、CuAu、CuRe、CuW、W或其组合。覆盖穿硅通路TSV1的阻挡膜可以包括选自W、WN、WC、Ti、TiN、Ta、TaN、Ru、Co、Mn、WN、Ni或NiB中的至少一种材料。阻挡膜可以是单个膜或多个膜。
在一些实施例中,第二半导体芯片200c还可以包括穿硅通路TSV2。穿硅通路TSV2可以形成为从第二衬底202的上表面开始穿过第二衬底202、第二元件层220、第二互连层230、第二结合层240和第一结合层140。穿硅通路TSV2的下表面可以连接到内部线133。
图7是根据示例实施例的半导体器件的横截面视图。图8是图7中所例示的半导体器件的局部放大横截面视图。图9例示了图7中所例示的半导体器件的第一结合层和第二结合层的平面图。
参照图7和图8,半导体器件可以包括第一半导体芯片100和第二半导体芯片200d。第一半导体芯片100可以包括第一电路层110和第一结合层140d。第一电路层110可以包括第一元件层120和第一互连层130。第一互连层130可以包括多个层,每个层具有多条内部线。例如,第一互连层130可以包括内部线131d、132d、133d和134d。第一结合层140d可以包括第一界面绝缘层142、层间绝缘层144和结合焊盘BP1'、BP2'、BP3'和BP4'。结合焊盘BP1'、BP2'、BP3'和BP4'可以分别连接到内部线131d、132d、133d和134d。
第二半导体芯片200d可以包括第二结合层240d、存储层210d和第二衬底202。第一结合层140d和第二结合层240d可以沿着结合表面S彼此结合。在一些实施例中,第二半导体芯片200d可以是存储芯片,例如,垂直NAND(VNAND)存储芯片。
存储层210d可以包括:内部线211d、212d、213d和214d;栅电极221d、222d、223d和224d;以及层间绝缘层235d。内部线211d、212d、213d和214d可以分别连接到栅电极221d、222d、223d和224d。内部线211d、212d、213d和214d可以对应于位线。栅电极221d、222d、223d和224d可以对应于字线并且可以以堆叠结构布置,并且绝缘层可以布置在栅电极221d、222d、223d和224d之间。层间绝缘层235d可以覆盖内部线211d、212d、213d和214d以及栅电极221d、222d、223d和224d。
栅电极221d、222d、223d和224d可以包括金属或金属氮化物。例如,栅电极221d、222d、223d和224d可以包括钨、氮化钨、钛、氮化钛、钽、氮化钽、铂、金属氮化物或其组合。设置在栅电极221d、222d、223d和224d之间的绝缘层可以包括氧化物基材料,例如氧化硅、碳氧化硅或氟氧化硅。
参照图9,第二结合层240d可以包括:结合焊盘BP1、BP2、BP3和BP4;结合结构252d、253d和254d;以及内部通路V1、V2、V3和V4。结合结构252d可以包括结合焊盘BP2和互连L2。结合结构253d可以包括结合焊盘BP3和互连L3。结合结构254d可以包括结合焊盘BP4和互连L4。结合焊盘BP1、BP2、BP3和BP4之间的距离可以在约0.5μm至约5μm的范围内。
第二结合层240d的结合焊盘BP1、BP2、BP3和BP4可以分别结合到第一结合层140d的结合焊盘BP1'、BP2'、BP3'和BP4'。结合焊盘BP1、BP2、BP3和BP4的下表面和互连L2、L3和L4的下表面可以彼此共面。内部通路V1、V2、V3和V4可以设置在结合焊盘BP1上。内部通路V1、V2、V3和V4可以设置在互连L2、L3和L4上。
图10至图16是根据示例实施例的半导体器件的第一结合层和第二结合层的平面图。
图10和图11是类似于图9或对应于图9的第一结合层和第二结合层的平面图。参照图10,第一结合层140e可以包括多个结合焊盘BP1'、BP2'和BP3'。第二结合层240e可以包括多个结合结构250e。每个结合结构250e可以包括彼此连接的结合焊盘BP1、BP2和BP3。第二结合层240e还可以包括结合焊盘BP4。多个内部通路V1、V2、V3和V4可以设置在结合结构250e上。第二结合层240e的结合结构250e可以具有结合功能和互连功能。例如,第一结合层140e的结合焊盘BP1'可以连接到第二结合层240e的结合焊盘BP1,因此可以通过内部通路V1和V2连接到不同的内部线。
参照图11,第一结合层140f可以包括多个结合结构150f和结合焊盘BP1'、BP5'和BP6'。第二结合层240f可以包括多个结合结构250f和结合焊盘BP1、BP5和BP6。第二结合层240f可以具有与图10的第二结合层240e相同的结构。结合结构150f的结合焊盘BP1'、BP5'和BP6'可以彼此连接。当从上方观察时,结合结构150f和结合结构250f可以在不同方向上延伸。在一些实施例中,结合结构150f的互连可以结合到多个结合结构250f以与多个结合结构250f相交。第一结合层140f的结合结构150f可以具有结合功能和互连功能。例如,第二结合层240f的结合焊盘BP1可以连接到第一结合层140f的结合焊盘BP1',因此可以通过多个内部通路连接到不同的内部线。
图12和图13是根据示例实施例的半导体器件的第一结合层和第二结合层的平面图。
参照图12,第一结合层140g可以包括结合结构150g。第二结合层240g可以包括结合焊盘BP'。结合结构150g可以包括结合焊盘BP和互连L1。互连L1可以连接结合焊盘BP和内部通路V1、V2和V3。互连L1可以具有各种形状以连接内部通路V1、V2和V3。例如,互连L1可以根据要连接的内部通路V1、V2和V3的位置而具有各种形状。在一些实施例中,互连L1可以具有折线形状。在一些实施例中,互连L1可以是沿对角线方向延伸或弯曲的线的形式。
参照图13,第一结合层140h可以包括结合结构150h。第二结合层240h可以包括结合结构250h。结合结构150h可以包括结合焊盘BP和互连L1。互连L1可以连接到内部通路V1、V2和V3。结合结构250h可以包括结合焊盘BP'和互连L1'。互连L1'可以连接到内部通路V4和V5。结合焊盘BP'可以结合到结合焊盘BP。如图13所例示,第一结合层140h和第二结合层240h分别包括具有互连功能的互连L1和L1',因此可以减少用于互连的层的数量。
参照图14,第一结合层140i可以包括多个结合结构150i。每个结合结构150i可以包括结合焊盘BP、非结合焊盘NBP和互连L。第二结合层240i可以包括多个结合焊盘BP'。每个结合焊盘BP可以通过互连L连接到非结合焊盘NBP中的一个非结合焊盘。非结合焊盘NBP可以电连接到第一结合层140i下方的内部线。
参照图15,第一结合层140j可以包括互连L1。第二结合层240j可以包括结合焊盘BP1和BP2。内部通路V1、V2和V3可以结合到结合焊盘BP1和BP2。内部通路V1、V2和V3可以电连接到第一结合层140j下方的内部线。第一结合层140j和第二结合层240j可以以各种图案彼此结合。在一些实施例中,互连L1可以连接到内部通路V1、V2和V3。在一些实施例中,互连L1可以连接到多个内部通路中的一个或更多个内部通路,例如一个内部通路V1或两个内部通路V1和V2。结合焊盘BP1可以连接到一个内部通路V1,并且结合焊盘BP2可以连接到两个内部通路V2和V3。如图15所例示,第一结合层140j包括具有互连功能的互连L1,因此可以应用各种结合图案。
参照图16,第一结合层140k可以包括互连L1。第二结合层240k可以包括互连L1'。内部通路V1、V2和V3可以电连接到第一结合层140k下方的内部线。内部通路V4和V5可以电连接到第二结合层240k上的内部线。在平面图中,互连L1和互连L1'可以延伸成彼此相交,即,相交。在一些实施例中,互连L1和互连L1'可以在对角线方向或相同方向上延伸。如图16所例示,第一结合层140k和第二结合层240k通过互连L1和互连L1'连接,因此可以提高结合位置和图案的自由度。另外,即使当互连L1和互连L1'未对准(例如,沿着结合表面S)而彼此接触时,也可以保持他们之间一定的接触面积。
图17和图18是根据示例实施例的半导体器件的横截面视图。参照图17,第二结合层240l可以设置在第一结合层140l上。结合焊盘BP和结合焊盘BP'可以形成为在横向方向上具有相同的宽度,并且可以在横向方向上彼此对准和结合。第一结合层140l可以包括覆盖焊盘BP'的侧表面和下表面的阻挡膜146l。第二结合层240l可以包括覆盖焊盘BP的侧表面和上表面的阻挡膜246l。
第一结合层140l可以包括位于其上表面上的第一界面绝缘层142。第二结合层240l可以包括位于其下表面上的第二界面绝缘层242。半导体器件还可以包括位于第一界面绝缘层142与第二界面绝缘层242之间的界面氧化物层148。界面氧化物层148可以通过氧化第一界面绝缘层142和/或第二界面绝缘层242来形成。例如,可以通过对包括SiCN的第一界面绝缘层142或第二界面绝缘层242的表面执行O2等离子体处理、H2等离子体处理、N2等离子体处理或NH3等离子体处理来形成界面氧化物层148。界面氧化物层148可以增加第一半导体芯片100与第二半导体芯片200之间的附着。
在一些实施例中,可以通过化学机械抛光(CMP)部分地去除结合焊盘BP和BP'的表面的边缘,因此结合焊盘BP和BP'可以具有圆角。结合焊盘BP'上的阻挡膜146l的一部分可以不附着到结合焊盘BP,因此可以与结合焊盘BP'分离。类似地,阻挡膜246l的一部分可以与结合焊盘BP分离。
在一些实施例中,可以在结合焊盘BP与结合焊盘BP'之间形成金属氧化物。金属氧化物可以通过氧化结合焊盘BP和BP'形成,并且可以包括例如氧化铜(如CuO)。
参照图18,第一结合层140m可以包括覆盖结合焊盘BP'的侧表面和下表面的阻挡膜146m。第二结合层240m可以包括覆盖结合焊盘BP的侧表面和上表面的阻挡膜246m。结合焊盘BP和结合焊盘BP'可以彼此不对准。在一些实施例中,结合焊盘BP和结合焊盘BP'可以在沿着结合表面S的横向方向上未对准并彼此结合。结合焊盘BP'的一部分可以与界面氧化物层148或阻挡膜246m接触。
根据本发明构思的示例实施例,在半导体器件的结合层的结合界面处提供结合焊盘和互连,因此,可以减少用于互连的层的数量并且可以实施各种类型的结合结构。
尽管已经参照附图描述了本发明构思的实施例,但是本领域技术人员应当理解的是,在不脱离本发明构思的范围且不改变本发明构思的基本特征的情况下,可以进行各种修改。因此,上述实施例应当仅被认为是描述性的,而不是为了限制的目的,本发明构思的范围在所附权利要求中阐述。
Claims (20)
1.一种半导体器件,包括:
第一半导体芯片,所述第一半导体芯片包括第一衬底、在所述第一衬底上并且包括多条第一内部线的第一电路层以及在所述第一电路层上的第一结合层;以及
第二半导体芯片,所述第二半导体芯片堆叠在所述第一半导体芯片上,并且包括第二衬底、在所述第二衬底下方的第二电路层以及在所述第二电路层下方的第二结合层,
其中,所述第一结合层包括第一结合焊盘、多个第一内部通路以及电连接所述第一结合焊盘和所述多个第一内部通路的第一互连,
所述第二结合层包括结合到所述第一结合焊盘的第二结合焊盘,
所述第一互连的上表面和所述第一结合焊盘的上表面与所述第一结合层的上表面共面,并且
所述第一互连通过所述多个第一内部通路电连接到所述多条第一内部线。
2.根据权利要求1所述的半导体器件,其中,所述第一结合焊盘的下表面和所述第一互连的下表面共面。
3.根据权利要求1所述的半导体器件,其中,在平面图中,所述第一结合焊盘的宽度大于所述第一互连的宽度。
4.根据权利要求1所述的半导体器件,其中,所述多个第一内部通路中的至少一个第一内部通路在沿着所述第一结合层的上表面的横向方向上与所述第一结合焊盘间隔开,并且其中,所述第一互连在所述横向方向上延伸超过所述第一结合焊盘。
5.根据权利要求1所述的半导体器件,其中,所述第二结合层还包括:
多个第二内部通路;以及
第二互连,所述第二互连电连接所述第二焊盘和所述多个第二内部通路,
其中,所述第二互连的下表面和所述第二结合焊盘的下表面与所述第二结合层的下表面共面。
6.根据权利要求5所述的半导体器件,其中,在平面图中,所述第二结合焊盘的宽度大于所述第二互连的宽度。
7.根据权利要求1所述的半导体器件,其中,所述第一结合焊盘和所述第二结合焊盘在沿着所述第一结合层的上表面的横向方向上未对准而彼此结合,并且其中,所述第一结合焊盘与所述第二结合焊盘上的阻挡膜的一部分接触和/或与所述第一结合层与所述第二结合层之间的界面氧化物层的一部分接触。
8.根据权利要求1所述的半导体器件,其中,所述第一结合层包括:
第一层间绝缘层,所述第一层间绝缘层与所述第一结合焊盘、所述多个第一内部通路和所述第一互连接触;以及
第一界面绝缘层,所述第一界面绝缘层在所述第一层间绝缘层的上表面上,并且在所述第一层间绝缘层上延伸;并且
其中,所述第二结合层包括:
第二层间绝缘层,所述第二层间绝缘层与所述第二结合焊盘接触;以及
第二界面绝缘层,所述第二界面绝缘层在所述第二结合层的下表面上,并且在所述第二层间绝缘层上延伸。
9.根据权利要求8所述的半导体器件,还包括界面氧化物层,所述界面氧化物层在所述第一界面绝缘层与所述第二界面绝缘层之间。
10.根据权利要求1所述的半导体器件,还包括穿硅通路,所述穿硅通路穿过所述第二衬底、所述第二结合层和所述第一结合层,并且连接到所述多条第一内部线中的至少一条第一内部线。
11.根据权利要求1所述的半导体器件,其中,所述第一半导体芯片是逻辑芯片,并且所述第二半导体芯片是像素阵列芯片,所述像素阵列芯片中包括一个或更多个光电转换区域。
12.根据权利要求1所述的半导体器件,其中,所述第一半导体芯片是逻辑芯片,并且所述第二半导体芯片是存储芯片,所述存储芯片中包括字线和位线。
13.根据权利要求1所述的半导体器件,其中,所述第一结合焊盘和所述第二结合焊盘具有不同的宽度。
14.一种半导体器件,包括:
第一半导体芯片,所述第一半导体芯片包括第一衬底、在所述第一衬底上的第一电路层以及在所述第一电路层上的第一结合层;以及
第二半导体芯片,所述第二半导体芯片堆叠在所述第一半导体芯片上,并且包括第二衬底、在所述第二衬底下方并且包括多条第二内部线的第二电路层以及在所述第二电路层下方的第二结合层,
其中,所述第一结合层包括多个第一结合焊盘以及连接所述多个第一结合焊盘的第一互连,并且
所述第二结合层包括多个第二结合焊盘以及连接所述多个第二结合焊盘和多个第二内部通路的第二互连,所述多个第二结合焊盘结合到所述多个第一结合焊盘,并且
其中,所述第二互连的下表面与所述多个第二结合焊盘的各个下表面共面,并且
所述多个第二结合焊盘通过所述多个第二内部通路连接到所述多条第二内部线。
15.根据权利要求14所述的半导体器件,其中,所述第一互连在平行于所述第一衬底的顶表面的第一方向上延伸超过所述第一结合焊盘,并且其中,所述第二互连在平行于所述第二衬底的底表面的第二方向上延伸超过所述第二结合焊盘。
16.根据权利要求15所述的半导体器件,其中,所述第一互连和所述第二互连在所述第一互连和所述第二互连彼此相交的区域中彼此结合。
17.根据权利要求14所述的半导体器件,还包括穿硅通路,所述穿硅通路穿过所述第二衬底、所述第二结合层和所述第一结合层,并且连接到所述多条第一内部线中的至少一条第一内部线。
18.一种半导体器件,包括:
第一半导体芯片,所述第一半导体芯片包括第一衬底、多条第一内部线以及在所述多条第一内部线上的第一结合层;以及
第二半导体芯片,所述第二半导体芯片堆叠在所述第一半导体芯片上,并且包括第二衬底以及在所述第二衬底下方的第二结合层,
其中,所述第一结合层包括第一结合焊盘、至少一个非结合焊盘以及连接所述第一结合焊盘和所述至少一个非结合焊盘的第一互连,
所述第二结合层包括结合到所述第一结合焊盘的第二结合焊盘,
所述第一互连的上表面和所述第一结合焊盘的上表面与所述第一结合层的上表面共面,
在平面图中,所述至少一个非结合焊盘的宽度大于所述第一互连的宽度,并且小于所述第一结合焊盘的宽度,并且
所述第一互连通过所述至少一个非结合焊盘连接到所述多条第一内部线。
19.根据权利要求18所述的半导体器件,其中,所述第一结合焊盘的下表面和所述第一互连的下表面共面。
20.根据权利要求18所述的半导体器件,其中,所述至少一个非结合焊盘和所述第二结合焊盘在沿着所述第一结合层的上表面的横向方向上未对准而彼此结合。
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