CN111478863B - Switch system and network port time synchronization method thereof - Google Patents
Switch system and network port time synchronization method thereof Download PDFInfo
- Publication number
- CN111478863B CN111478863B CN202010289927.7A CN202010289927A CN111478863B CN 111478863 B CN111478863 B CN 111478863B CN 202010289927 A CN202010289927 A CN 202010289927A CN 111478863 B CN111478863 B CN 111478863B
- Authority
- CN
- China
- Prior art keywords
- board
- clock
- time information
- opposite
- local
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Electric Clocks (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a switch system and a network port time synchronization method thereof, which carry out the separated design of a main control switch board, a clock board and a service board, transmit messages with time stamps through each communication interface and different communication protocols thereof, give play to the serial operation of a CPU, easily realize the advantages of IEEE1588v2 protocol, give play to the parallel operation of an FPGA, quickly and timely, calculate time deviation by the CPU, correct the deviation by the FPGA, and finally synchronize the clock to a switch chip on each service board through a 1PPS + ToD interface.
Description
Technical Field
The invention relates to the field of communication, in particular to a switch system and a network port time synchronization method thereof.
Background
In a communication system, in order to achieve a certain order of magnitude of data exchange capacity, multiple network ports are generally used in addition to increasing the bandwidth of a single network port of a switch. Meanwhile, in order to realize the interconnection with different interfaces of the opposite-end switch, a plurality of or a plurality of network ports are also needed on the switch.
With the development of the internet, more and more applications such as voice, video call, automatic driving, internet of things and the like have requirements on network time synchronization, and also have requirements on network port synchronization of a multi-network-port switch, namely the time synchronization of all network ports of the whole machine is required.
Due to the limitation of the existing switch system, the method for synchronizing the switch network port time is also extremely limited, and a pure hardware mode is generally adopted: and the clock recovered from the received data is sent to a counter, the running time is calculated according to the value of the counter, the calculated running time is compared with the RTC clock of the network port, the deviation value of the running time and the RTC clock of the network port is calculated, the RTC clock is calibrated according to the deviation value so as to realize clock synchronization of the master network port and the slave network port, and the synchronized RTC clock of the network port is synchronized with other network ports on the board or other board card RTC clocks. This approach can only synchronize clock frequencies, not time information.
Disclosure of Invention
Aiming at the defects in the prior art, the switch system and the network port time synchronization method thereof provided by the invention solve the problem that the prior switch network port time synchronization technology can only synchronize clock frequency and cannot synchronize time information.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a switch system, comprising: the system comprises a switchboard back plate, a master control switchboard, a clock plate and N service plates, wherein N is an integer greater than 1; the master control exchange board, the clock board and the N service boards are all fixedly connected with the switchboard back board; the master control exchange board is in communication connection with the clock board and is in communication connection with the N service boards; and the clock board is respectively in communication connection with the N service boards.
Furthermore, the core processing chip of the master control exchange board comprises an exchange chip, a CPU and an FPGA; the core processing chip of the clock board is an FPGA; the core processing chips of the N service boards are all switching chips; each service board comprises M network ports, and M is an integer greater than 1.
Furthermore, the switching chip of the master control switching board is in communication connection with the CPU of the master control switching board through a PCIE interface; the CPU of the main control exchange board is in communication connection with the FPGA of the main control exchange board through a management interface; the exchange chip of the master control exchange board is in communication connection with the exchange chips of the N service boards through data interfaces; the FPGA of the main control exchange board is in communication connection with the FPGA of the clock board through a management interface; the FPGA of the clock board is in communication connection with the switching chips of the N service boards through a 1PPS + ToD interface; and the respective exchange chip of each service board is in communication connection with the M network ports.
Further, the communication protocol of the management interface comprises an SPI serial peripheral interface protocol and a UART serial communication protocol.
A network port time synchronization method of a switch system comprises the following steps:
s1, presetting local default time information through a clock board;
s2, obtaining a PTP message with a local timestamp and an opposite terminal host timestamp through N service boards according to the default time information;
s3, inputting the PTP message with the local timestamp and the opposite-end host timestamp into the CPU of the main control exchange board, and calculating the deviation value of the local default time information and the opposite-end host time information through the CPU of the main control exchange board;
s4, writing the deviation value between the local default time information and the time information of the opposite-end host into a register of the FPGA of the main control exchange board through a management interface, and presenting the deviation value between the local default time information and the time information of the opposite-end host to the FPGA of the clock board through the FPGA of the main control exchange board and the management interface;
s5, calibrating local time through a clock board according to the deviation value of the local default time information and the opposite-end host time information to obtain preliminarily calibrated time;
s6, synchronizing the time after the preliminary calibration to the N service boards through the 1PPS + ToD interface;
s7, the CPU performs PTP communication with the opposite end host according to the set frequency, the clock board continuously calibrates the local time according to the deviation value, and synchronizes the calibrated time to the N service boards through the 1PPS + ToD interface, so as to achieve the purpose of time synchronization of each network port.
Further, the step S2 includes the following sub-steps:
s21, synchronizing the default time information of the clock board to the N service boards through the 1PPS + ToD interface;
s22, selecting the best clock synchronization network port from the network ports of the N service boards which are communicating with the host of the opposite end on the respective network by the CPU of the main control exchange board and adopting the best master clock algorithm;
s23, receiving a PTP time synchronization message broadcasted by an opposite terminal host on the network through the optimal clock synchronization network port, wherein the synchronization message comprises a timestamp marked by the opposite terminal host, and when the PTP message enters an exchange chip of a service board communicated with the PTP message, carrying out timestamp marking operation on the PTP message through the exchange chip according to default time information to obtain the PTP message with a local timestamp and a timestamp of the opposite terminal host.
Further, the step S3 includes the following steps:
s31, presenting the PTP message with the local timestamp and the opposite-end host timestamp to a switching chip of the main control switching board through a data interface, and then presenting the PTP message to a CPU of the main control switching board through a PCIE interface;
s32, calculating the deviation value of the local default time information and the opposite-end host time information according to the local time stamp and the opposite-end host time stamp in the PTP message.
The invention has the beneficial effects that: the invention carries out the separated design of the main control exchange board, the clock board and the service board, transmits messages with time stamps through each communication interface and different communication protocols thereof, gives play to the serial operation of the CPU, is easy to realize the advantages of IEEE1588v2 protocol, simultaneously gives play to the parallel operation of the FPGA, has the advantages of rapidness and timeliness, calculates the time deviation by the CPU, corrects the deviation by the FPGA, and finally synchronizes the clock to the exchange chip on each service board through the 1PPS + ToD interface.
Drawings
FIG. 1 is a system block diagram of a switch;
fig. 2 is a schematic flow chart of a method for synchronizing network port time in a switch system.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 1, in one embodiment of the present invention, a switch system includes: the system comprises a switchboard back plate, a master control switchboard, a clock plate and N service plates, wherein N is an integer greater than 1; the master control exchange board, the clock board and the N service boards are all fixedly connected with the switchboard back board; the master control exchange board is in communication connection with the clock board and is in communication connection with the N service boards; and the clock board is respectively in communication connection with the N service boards.
The core processing chip of the master control exchange board comprises an exchange chip, a CPU and an FPGA; the core processing chip of the clock board is an FPGA; the core processing chips of the N service boards are all switching chips; each service board comprises M network ports, and M is an integer greater than 1.
The switching chip of the master control switching board is in communication connection with the CPU of the master control switching board through a PCIE interface; the CPU of the main control exchange board is in communication connection with the FPGA of the main control exchange board through a management interface; the exchange chip of the master control exchange board is in communication connection with the exchange chips of the N service boards through data interfaces; the FPGA of the main control exchange board is in communication connection with the FPGA of the clock board through a management interface; the FPGA of the clock board is in communication connection with the switching chips of the N service boards through a 1PPS + ToD interface; and the respective exchange chip of each service board is in communication connection with the M network ports.
The communication protocol of the management interface comprises an SPI serial peripheral interface protocol and a UART serial communication protocol.
As shown in fig. 2, a method for synchronizing network port time of a switch system includes the following steps:
s1, presetting local default time information through a clock board;
s2, obtaining a PTP message with a local timestamp and an opposite terminal host timestamp through N service boards according to the default time information;
the step S2 includes the following sub-steps:
s21, synchronizing the default time information of the clock board to the N service boards through the 1PPS + ToD interface;
s22, selecting the best clock synchronization network port from the network ports of the N service boards which are communicating with the host of the opposite end on the respective network by the CPU of the main control exchange board and adopting the best master clock algorithm;
s23, receiving a PTP time synchronization message broadcasted by an opposite terminal host on the network through the optimal clock synchronization network port, wherein the synchronization message comprises a timestamp marked by the opposite terminal host, and when the PTP message enters an exchange chip of a service board communicated with the PTP message, carrying out timestamp marking operation on the PTP message through the exchange chip according to default time information to obtain the PTP message with a local timestamp and a timestamp of the opposite terminal host.
S3, inputting the PTP message with the local timestamp and the opposite-end host timestamp into the CPU of the main control exchange board, and calculating the deviation value of the local default time information and the opposite-end host time information through the CPU of the main control exchange board;
the step S3 includes the steps of:
s31, presenting the PTP message with the local timestamp and the opposite-end host timestamp to a switching chip of the main control switching board through a data interface, and then presenting the PTP message to a CPU of the main control switching board through a PCIE interface;
s32, calculating the deviation value of the local default time information and the opposite-end host time information according to the local time stamp and the opposite-end host time stamp in the PTP message.
S4, writing the deviation value between the local default time information and the time information of the opposite-end host into a register of the FPGA of the main control exchange board through a management interface, and presenting the deviation value between the local default time information and the time information of the opposite-end host to the FPGA of the clock board through the FPGA of the main control exchange board and the management interface;
s5, calibrating local time through a clock board according to the deviation value of the local default time information and the opposite-end host time information to obtain preliminarily calibrated time;
s6, synchronizing the time after the preliminary calibration to the N service boards through the 1PPS + ToD interface;
s7, the CPU performs PTP communication with the opposite end host according to the set frequency, the clock board continuously calibrates the local time according to the deviation value, and synchronizes the calibrated time to the N service boards through the 1PPS + ToD interface, so as to achieve the purpose of time synchronization of each network port.
The invention has carried on the separate design of the main control exchange board, clock board, business board, transmit the message with time stamp through every communication interface and its different communication protocol, give play to CPU serial operation, easy to realize the advantage of IEEE1588v2 agreement, give play to FPGA parallel operation at the same time, advantage fast and timely, calculate the time deviation with CPU, correct the deviation with FPGA, send the clock synchronization to the switching chip on every business board through 1PPS + ToD interface finally, the invention is with the design of the unique hardware and supporting method flow, compare with the traditional technology that can only synchronize the clock frequency, can realize the synchronization of the time information.
Claims (3)
1. A network port time synchronization method of a switch system, wherein the switch system comprises: the system comprises a switchboard back plate, a master control switchboard, a clock plate and N service plates, wherein N is an integer greater than 1; the master control exchange board, the clock board and the N service boards are all fixedly connected with the switchboard back board; the master control exchange board is in communication connection with the clock board and is in communication connection with the N service boards; the clock board is respectively in communication connection with the N service boards;
the method is characterized by comprising the following steps:
s1, presetting local default time information through a clock board;
s2, obtaining a PTP message with a local timestamp and an opposite terminal host timestamp through N service boards according to the default time information;
s3, inputting the PTP message with the local timestamp and the opposite-end host timestamp into the CPU of the main control exchange board, and calculating the deviation value of the local default time information and the opposite-end host time information through the CPU of the main control exchange board;
s4, writing the deviation value between the local default time information and the time information of the opposite-end host into a register of the FPGA of the main control exchange board through a management interface, and presenting the deviation value between the local default time information and the time information of the opposite-end host to the FPGA of the clock board through the FPGA of the main control exchange board and the management interface;
s5, calibrating local time through a clock board according to the deviation value of the local default time information and the opposite-end host time information to obtain preliminarily calibrated time;
s6, synchronizing the time after the preliminary calibration to the N service boards through the 1PPS + ToD interface;
s7, the CPU performs PTP communication with the opposite end host according to the set frequency, the clock board continuously calibrates the local time according to the deviation value, and synchronizes the calibrated time to the N service boards through the 1PPS + ToD interface, so as to achieve the purpose of time synchronization of each network port.
2. The method for time synchronization of network ports of a switch system according to claim 1, wherein said step S2 comprises the following substeps:
s21, synchronizing the default time information of the clock board to the N service boards through the 1PPS + ToD interface;
s22, selecting the best clock synchronization network port from the network ports of the N service boards which are communicating with the host of the opposite end on the respective network by the CPU of the main control exchange board and adopting the best master clock algorithm;
s23, receiving a PTP time synchronization message broadcasted by an opposite terminal host on the network through the optimal clock synchronization network port, wherein the synchronization message comprises a timestamp marked by the opposite terminal host, and when the PTP message enters an exchange chip of a service board communicated with the PTP message, carrying out timestamp marking operation on the PTP message through the exchange chip according to default time information to obtain the PTP message with a local timestamp and a timestamp of the opposite terminal host.
3. The portal time synchronization method of the switch system according to claim 1, wherein the step S3 comprises the steps of:
s31, presenting the PTP message with the local timestamp and the opposite-end host timestamp to a switching chip of the main control switching board through a data interface, and then presenting the PTP message to a CPU of the main control switching board through a PCIE interface;
s32, calculating the deviation value of the local default time information and the opposite-end host time information according to the local time stamp and the opposite-end host time stamp in the PTP message.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010289927.7A CN111478863B (en) | 2020-04-14 | 2020-04-14 | Switch system and network port time synchronization method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010289927.7A CN111478863B (en) | 2020-04-14 | 2020-04-14 | Switch system and network port time synchronization method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111478863A CN111478863A (en) | 2020-07-31 |
| CN111478863B true CN111478863B (en) | 2022-02-11 |
Family
ID=71751855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010289927.7A Active CN111478863B (en) | 2020-04-14 | 2020-04-14 | Switch system and network port time synchronization method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111478863B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112769785B (en) * | 2020-12-29 | 2023-06-27 | 深圳市风云实业有限公司 | Network integrated depth detection device and method based on rack switch equipment |
| CN113766697B (en) * | 2021-09-24 | 2024-05-03 | 华源智信半导体(深圳)有限公司 | LED backlight system, driving chip thereof and processing method of main control chip |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2922300Y (en) * | 2006-06-26 | 2007-07-11 | 华为技术有限公司 | Clock synchronizing system and service plate |
| CN101114896A (en) * | 2007-05-15 | 2008-01-30 | 北京东土科技股份有限公司 | Method for implementing precise synchronization clock |
| CN101625568B (en) * | 2009-08-14 | 2012-08-08 | 江西联创通信有限公司 | Synchronous data controller based hot standby system of main control unit and method thereof |
| CN102263629B (en) * | 2010-05-24 | 2013-11-06 | 华为技术有限公司 | Method for time synchronization among boards, clock board and NE (network element) device |
| CN101986594B (en) * | 2010-11-18 | 2015-06-03 | 中兴通讯股份有限公司 | Method and device for realizing communication between single boards |
| CN102045124B (en) * | 2010-12-06 | 2014-12-17 | 神州数码网络(北京)有限公司 | Rack-mount synchronous Ethernet architecture and clock synchronization control method |
| CN103067112B (en) * | 2012-12-17 | 2016-01-27 | 福建星网锐捷网络有限公司 | Clock synchronizing method, device and the network equipment |
| FR3019337B1 (en) * | 2014-04-01 | 2016-03-18 | Snecma | SYNCHRONIZATION OF DATA LINKS IN THE ENTRY OF A COMPUTER |
| CN107579795B (en) * | 2017-10-23 | 2019-01-22 | 广州供电局有限公司 | The method for synchronizing time of distributed multi bri device and distributed multiport system |
| CN108023839B (en) * | 2017-12-13 | 2023-12-08 | 天津光电通信技术有限公司 | Signal switching equipment applied to Tb/s-level optical network and control system thereof |
| CN209120199U (en) * | 2018-09-29 | 2019-07-16 | 南京泰通科技股份有限公司 | High reliability real-time synchronization data processing equipment |
| CN109981205B (en) * | 2019-02-22 | 2020-07-28 | 烽火通信科技股份有限公司 | Method and system for transmitting 1PPS + TOD signals |
| CN110572234A (en) * | 2019-10-22 | 2019-12-13 | 深圳震有科技股份有限公司 | Method for realizing clock synchronization based on serial port, intelligent terminal and storage medium |
-
2020
- 2020-04-14 CN CN202010289927.7A patent/CN111478863B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111478863A (en) | 2020-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8259749B2 (en) | System, method and apparatus of time information synchronization | |
| CN101594673B (en) | Method and system for processing 1588 time stamp in distribution mode | |
| CN102394715B (en) | Clock synchronizing method and device | |
| CN101547083B (en) | Time synchronizer, time synchronization system and time synchronization method | |
| CN111478863B (en) | Switch system and network port time synchronization method thereof | |
| CN101582733A (en) | Method and system for realizing high precision time synchronization among SDH equipment | |
| CN103378993A (en) | Slave clock monitoring method based on PTP | |
| CN103188066A (en) | Reference clock signal processing method and device | |
| CN101247169A (en) | Method, system and equipment for implementing time synchronization in communication network | |
| CN102404105A (en) | Device and method for realizing time synchronization on Ethernet switch | |
| CN102208958A (en) | Clock synchronization method for synchronous Ethernets, as well as synchronous information sending/receiving method, device and apparatus | |
| CN102916758B (en) | Ethernet time synchronism apparatus and the network equipment | |
| CN102263629A (en) | Method for time synchronization among boards, clock board and NE (network element) device | |
| CN104660360A (en) | Ethernet data and multi-channel E1 data processing method and system | |
| CN201789508U (en) | 1588V2 protocol processing system | |
| CN101296070B (en) | Clock synchronization method and system of multiport synchronization Ethernet equipment | |
| CN102342051B (en) | For coming the method for synchronised clock and relevant system and module by separating transmission first and second data via at least one time distribution protocol | |
| CN103378916A (en) | Clock transmission method, boundary clock and transparent clock | |
| CN111083776B (en) | TTE time synchronization method based on 1588 and AS6802 protocol | |
| CN102571253B (en) | Method and equipment for implementing precise time synchronization | |
| CN109842456A (en) | A kind of clock synchronizing method based on AFDX network | |
| CN113573403B (en) | Slave clock synchronization system and method for 5G RRU | |
| CN112615694B (en) | Method and device for realizing network time synchronization | |
| CN117439691B (en) | Time information synchronization system, processor chip and electronic device | |
| CN102340396A (en) | Time synchronization method for Ethernet passive optical network (EPON) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |