CN111477140A - Novel power-saving display screen architecture and driving method - Google Patents
Novel power-saving display screen architecture and driving method Download PDFInfo
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- CN111477140A CN111477140A CN202010270351.XA CN202010270351A CN111477140A CN 111477140 A CN111477140 A CN 111477140A CN 202010270351 A CN202010270351 A CN 202010270351A CN 111477140 A CN111477140 A CN 111477140A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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Abstract
The invention discloses a new display screen architecture for saving power consumption, which comprises: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, eight data lines and four source lines. The pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into eight rows of sub-pixel pairs, and each row of sub-pixel pairs comprises two rows of sub-pixels. A data line is arranged in the middle of each column of sub-pixel pairs, each data line is connected with a TFT switch, eight TFT switches are formed in total, and all the TFT switches are divided into two groups. Each row of sub-pixels comprises an upper gate line and a lower gate line. Above-mentioned technical scheme will reduce the quantity of source line by a wide margin, has reduced the length of Y axle, has also practiced thrift the cost of manufacture this moment, has reduced the consumption when showing simultaneously, promotes the display quality of display screen.
Description
Technical Field
The invention relates to the field of display screens, in particular to a novel display screen framework capable of saving power consumption and a driving method.
Background
The design of the display screen with the narrow frame and the full screen is mainstream, with the wide popularization of the display screen, from the aspect of screen occupation ratio, the initial generation iPhone screen occupation ratio in 2007 is only about 50%, in the following years, the mobile phone screen occupation ratio is continuously improved, but the improvement range is not large.
Disclosure of Invention
Therefore, it is desirable to provide a new display screen architecture and a driving method for saving power consumption, which solve the problem of small screen occupation ratio and reduce the power consumption of the display screen.
To achieve the above object, the inventor provides a new display screen architecture for saving power consumption, comprising: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, eight data lines and four source lines;
the pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into eight rows of sub-pixel pairs, each row of sub-pixel pair comprises two rows of sub-pixels, and each row of sub-pixels comprises an upper gate line and a lower gate line;
a data line is arranged in the middle of each column of sub-pixel pairs, each data line is connected with a TFT switch, eight TFT switches in total are arranged, and the output end of each TFT switch is connected with the data line; all the TFT switches are divided into two groups, and are divided into one group at the positions of the first to the fourth columns and divided into another group at the positions of the fourth to the eight columns according to the column sequence;
one Demux line is connected with the grid electrode of the TFT switch of one group of each pixel unit, and the other Demux line is connected with the grid electrode of the TFT switch of the other group of each pixel unit; the input ends of the four TFT switches of each group are respectively connected with the four source lines one by one;
each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row.
Further, one data line connects one sub-pixel in the sub-pixel pair, and also connects one sub-pixel in the other sub-pixel pair.
Further, one data line connects two sub-pixels in the sub-pixel pair.
Further, still include: a driving unit connected to the plurality of source lines.
Further, the plurality of sub-pixels are arranged in an array in sequence in the manner of R, G, B.
The inventor provides a driving method of a new power consumption saving display screen architecture, which is applied to the new power consumption saving display screen architecture in any one of the above embodiments, and is characterized by comprising the following steps:
opening a gate line of a row of sub-pixels;
sequentially opening two Demux lines during the opening period of one gate line;
during the opening period of the Demux line of the first strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the first to fourth column positions through the source lines, and during the opening period of the Demux line of the second strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the fourth to eighth column positions through the source lines;
the other gate line of a row of sub-pixels is turned on,
sequentially turning on two Demux lines during the turning on of the other gate line;
during the opening period of the Demux line of the first strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the first to fourth column positions through the source lines, and during the opening period of the Demux line of the second strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the fourth to eighth column positions through the source lines;
and driving the sub-pixels of each row by circulating the steps.
Different from the prior art, the technical scheme greatly reduces the number of source lines, reduces the length of a Y axis, greatly saves the manufacturing cost at the moment, reduces the power consumption during display, reduces the picture temperature, and improves the display quality of the display screen.
Drawings
FIG. 1 is a structural diagram of a new power saving display screen;
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1, in the present embodiment, a new display screen architecture for saving power consumption is provided, including: the pixel structure comprises a plurality of pixel units and two Demux lines (SW1, SW2), wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines (G1, G2, G3 … …), eight data lines (D1, D2, D3, D4, D5, D6, D7, D8) and four source lines (S1, S2, S3, S4). The pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into eight rows of sub-pixel pairs, each row of sub-pixel pair comprises two rows of sub-pixels, and each row of sub-pixels comprises an upper gate line and a lower gate line. A data line is arranged in the middle of each column of sub-pixel pairs, each data line is connected with a TFT switch, eight TFT switches in total are arranged, and the output end of each TFT switch is connected with the data line; all the TFT switches are divided into two groups, and are divided into one group at the first to fourth column positions and another group at the fourth to eighth column positions in the column order. One Demux line is connected with the grid electrode of the TFT switch of one group of each pixel unit, and the other Demux line is connected with the grid electrode of the TFT switch of the other group of each pixel unit; the input ends of the four TFT switches of each group are respectively connected with the four source lines one by one. Each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row. Meanwhile, one data line is connected with one sub-pixel in the sub-pixel pair and is also connected with one sub-pixel in the other sub-pixel pair. One data line connects two subpixels in the subpixel pair.
Of course, in some embodiments, the pixel driving method is as follows:
opening a gate line of a row of sub-pixels;
sequentially opening two Demux lines during the opening period of one gate line;
during the opening period of the Demux line of the first strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the first to fourth column positions through the source lines, and during the opening period of the Demux line of the second strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the fourth to eighth column positions through the source lines;
the other gate line of a row of sub-pixels is turned on,
sequentially turning on two Demux lines during the turning on of the other gate line;
during the opening period of the Demux line of the first strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the first to fourth column positions through the source lines, and during the opening period of the Demux line of the second strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the fourth to eighth column positions through the source lines;
and driving the sub-pixels of each row by circulating the steps.
Specifically, referring to fig. 1, a pixel unit, S1-S4 source lines, TFT switches, and SW, wherein the leftmost and rightmost display is column inversion, and the rest is Dot display effect, the pixel unit will repeatedly appear on the display screen for a plurality of times, and the number of times of appearance will be different according to the resolution of the display screen. D1-D8 are data lines in the display screen, S1-S4 are source lines from the IC, and SW1 and SW2 are provided with TFT switches to control whether the data is transmitted to the display screen. S1 is connected to D1 in the plane through the TFT switch and SW1, and connected to D5 in the plane through the TFT switch and SW 2; s2 is connected to D2 in the plane through the TFT switch and SW1, and connected to D6 in the plane through the TFT switch and SW 2; s3 is connected to D3 in the plane through the TFT switch and SW1, and connected to D7 in the plane through the TFT switch and SW 2; s4 is connected to D4 in the plane through the TFT switch and SW1, and connected to D8 in the plane through the TFT switch and SW 2;
taking the sub-pixels on S1 as an example, the data transmission process of the third embodiment of the patent is described, wherein when G1 is turned on and SW1 is turned on, S1 transmits B sub-pixel ① to D1 in the plane, SW1 is turned off, SW2 is turned on, S1 transmits B sub-pixel ② to D5 in the plane, when G2 is turned on and SW2 is turned on, S2 transmits R sub-pixel 2 to D2 in the plane, SW2 is turned off, SW2 is turned on, S2 transmits G sub-pixel 2 to D2 in the plane, when G2 is turned on and SW2 is turned on, S2 transmits the D sub-pixel 2 in the plane to D2 in the plane, SW2 is turned off, SW2 is turned on, S2 transmits the D sub-pixel 2 in the plane to D2 in the plane, when the S2 is turned on, S2 transmits the S sub-pixel 2 to the D2 in the plane, and the S2 transmits the S2 to the S2 in-plane, the S2 and the S2 transmits the S2 and the S2 to the S2, the S2 and S2 transmits the S2.
Referring to fig. 1, it can be seen that the source lines in the present embodiment are column inversion driven, but after special sub-pixel arrangement, Dot display can be shown on the display screen. Generally, Dot display is only performed by Dot driving, and although the display effect is good, the power consumption of the display screen is high due to the fact that the positive and negative inversion frequency of the voltage on the source line is high in one frame during Dot driving. By adopting the Column Inversion driving method, the positive and negative Inversion frequency of the voltage on the source line in one frame can be reduced, thereby reducing the power consumption without influencing the display effect. Different from the prior art, the technical scheme greatly reduces the number of source lines, reduces the length of a Y axis, greatly saves the manufacturing cost at the moment, reduces the power consumption during display, reduces the picture temperature, and improves the display quality of the display screen.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (6)
1. A new power saving display screen architecture, comprising: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, eight data lines and four source lines;
the pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into eight rows of sub-pixel pairs, each row of sub-pixel pair comprises two rows of sub-pixels, and each row of sub-pixels comprises an upper gate line and a lower gate line;
a data line is arranged in the middle of each column of sub-pixel pairs, each data line is connected with a TFT switch, eight TFT switches in total are arranged, and the output end of each TFT switch is connected with the data line; all the TFT switches are divided into two groups, and are divided into one group at the positions of the first to the fourth columns and divided into another group at the positions of the fourth to the eight columns according to the column sequence;
one Demux line is connected with the grid electrode of the TFT switch of one group of each pixel unit, and the other Demux line is connected with the grid electrode of the TFT switch of the other group of each pixel unit; the input ends of the four TFT switches of each group are respectively connected with the four source lines one by one;
each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row.
2. The new power saving display screen architecture of claim 1, wherein one data line connects one subpixel of the subpixel pair and one subpixel of the other subpixel pair.
3. The new power saving display screen structure of claim 1 or 2, wherein one data line connects two sub-pixels in the sub-pixel pair.
4. The new power saving display screen architecture of claim 1, further comprising: a driving unit connected to the plurality of source lines.
5. The new power saving display screen structure of claim 1, wherein the plurality of sub-pixels are sequentially arranged in an array of R, G, B.
6. A driving method for a new power saving display screen structure, applied to the new power saving display screen structure of any one of claims 1 to 6, comprising the following steps:
opening a gate line of a row of sub-pixels;
sequentially opening two Demux lines during the opening period of one gate line;
during the opening period of the Demux line of the first strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the first to fourth column positions through the source lines, and during the opening period of the Demux line of the second strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the fourth to eighth column positions through the source lines;
the other gate line of a row of sub-pixels is turned on,
sequentially turning on two Demux lines during the turning on of the other gate line;
during the opening period of the Demux line of the first strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the first to fourth column positions through the source lines, and during the opening period of the Demux line of the second strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the fourth to eighth column positions through the source lines;
and driving the sub-pixels of each row by circulating the steps.
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| CN112086035A (en) * | 2020-09-21 | 2020-12-15 | 福建华佳彩有限公司 | Display screen structure and driving method |
| CN112309261A (en) * | 2020-11-09 | 2021-02-02 | 福建华佳彩有限公司 | Optimized structure of display screen and driving method thereof |
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| CN110058466A (en) * | 2019-04-22 | 2019-07-26 | 深圳市华星光电技术有限公司 | Display device and its driving method |
| CN110308599A (en) * | 2019-06-28 | 2019-10-08 | 武汉天马微电子有限公司 | A kind of array substrate and display panel |
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| CN202837748U (en) * | 2012-06-25 | 2013-03-27 | 北京京东方光电科技有限公司 | Array substrate and display device |
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| CN112309261A (en) * | 2020-11-09 | 2021-02-02 | 福建华佳彩有限公司 | Optimized structure of display screen and driving method thereof |
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