CN211980166U

CN211980166U - Display screen framework with new power consumption saving function

Info

Publication number: CN211980166U
Application number: CN202020502068.0U
Authority: CN
Inventors: 熊克; 谢建峰
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2020-04-08
Filing date: 2020-04-08
Publication date: 2020-11-20
Anticipated expiration: 2030-04-08

Abstract

The utility model discloses a display screen framework of new sparingly consumption, include: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, eight data lines and four source lines. The pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into eight rows of sub-pixel pairs, and each row of sub-pixel pairs comprises two rows of sub-pixels. A data line is arranged in the middle of each column of sub-pixel pairs, each data line is connected with a TFT switch, eight TFT switches are formed in total, and all the TFT switches are divided into two groups. Each row of sub-pixels comprises an upper gate line and a lower gate line. Above-mentioned technical scheme will reduce the quantity of source line by a wide margin, has reduced the length of Y axle, has also practiced thrift the cost of manufacture this moment, has reduced the consumption when showing simultaneously, promotes the display quality of display screen.

Description

Display screen framework with new power consumption saving function

Technical Field

The utility model relates to a display screen field especially relates to a display screen framework of new power saving consumption.

Background

The design of narrow-frame and full-screen display screens has become mainstream, with the wide popularization of display screens, the ratio of the initial generation iPhone screen in 2007 is only about 50% from the aspect of screen ratio, and in the following years, the ratio of the mobile phone screen is continuously improved, but the improvement range is not large. In the existing display screen, the Y-axis length of a driving unit is an important factor influencing the overall screen or the narrow-frame screen. The conventional display screen is that one Source Line (Source Line) of an IC corresponds to one Data Line (Data Line) in a plane, and one Data Line of the display screen controls one sub-pixel, so that the number of the Source lines is excessive, the Y axis of a driving unit cannot be reduced, the power consumption of the display screen is increased, and the manufacturing cost of the driving unit is increased.

SUMMERY OF THE UTILITY MODEL

Therefore, a new display screen architecture capable of saving power consumption is needed, the problem of small screen occupation ratio is solved, and the power consumption of the display screen is reduced.

To achieve the above object, the inventor provides a new display screen architecture for saving power consumption, comprising: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, eight data lines and four source lines;

the pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into eight rows of sub-pixel pairs, each row of sub-pixel pair comprises two rows of sub-pixels, and each row of sub-pixels comprises an upper gate line and a lower gate line;

a data line is arranged in the middle of each column of sub-pixel pairs, each data line is connected with a TFT switch, eight TFT switches in total are arranged, and the output end of each TFT switch is connected with the data line; all the TFT switches are divided into two groups, and are divided into one group at the positions of the first to the fourth columns and divided into another group at the positions of the fourth to the eight columns according to the column sequence;

one Demux line is connected with the grid electrode of the TFT switch of one group of each pixel unit, and the other Demux line is connected with the grid electrode of the TFT switch of the other group of each pixel unit; the input ends of the four TFT switches of each group are respectively connected with the four source lines one by one;

each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row.

Further, one data line connects one sub-pixel in the sub-pixel pair, and also connects one sub-pixel in the other sub-pixel pair.

Further, one data line connects two sub-pixels in the sub-pixel pair.

Further, still include: a driving unit connected to the plurality of source lines.

Further, the plurality of sub-pixels are arranged in an array in sequence in the manner of R, G, B.

Different from the prior art, the technical scheme greatly reduces the number of source lines, reduces the length of a Y axis, greatly saves the manufacturing cost at the moment, reduces the power consumption during display, reduces the picture temperature, and improves the display quality of the display screen.

Drawings

FIG. 1 is a structural diagram of a new power saving display screen;

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1, in the present embodiment, a new display screen architecture for saving power consumption is provided, including: the pixel structure comprises a plurality of pixel units and two Demux lines (SW1, SW2), wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines (G1, G2, G3 … …), eight data lines (D1, D2, D3, D4, D5, D6, D7, D8) and four source lines (S1, S2, S3, S4). The pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into eight rows of sub-pixel pairs, each row of sub-pixel pair comprises two rows of sub-pixels, and each row of sub-pixels comprises an upper gate line and a lower gate line. A data line is arranged in the middle of each column of sub-pixel pairs, each data line is connected with a TFT switch, eight TFT switches in total are arranged, and the output end of each TFT switch is connected with the data line; all the TFT switches are divided into two groups, and are divided into one group at the first to fourth column positions and another group at the fourth to eighth column positions in the column order. One Demux line is connected with the grid electrode of the TFT switch of one group of each pixel unit, and the other Demux line is connected with the grid electrode of the TFT switch of the other group of each pixel unit; the input ends of the four TFT switches of each group are respectively connected with the four source lines one by one. Each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row. Meanwhile, one data line is connected with one sub-pixel in the sub-pixel pair and is also connected with one sub-pixel in the other sub-pixel pair. One data line connects two subpixels in the subpixel pair.

Of course, in some embodiments, the pixel driving method is as follows:

opening a gate line of a row of sub-pixels;

sequentially opening two Demux lines during the opening period of one gate line;

during the opening period of the Demux line of the first strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the first to fourth column positions through the source lines, and during the opening period of the Demux line of the second strip, the driving unit transmits signals to the sub-pixels connected with the data lines positioned at the fourth to eighth column positions through the source lines;

the other gate line of a row of sub-pixels is turned on,

sequentially turning on two Demux lines during the turning on of the other gate line;

and driving the sub-pixels of each row by circulating the steps.

Specifically, referring to fig. 1, a pixel unit, S1-S4 source lines, TFT switches, and SW, wherein the leftmost and rightmost are Column Inversion displays, and the rest are Dot displays, the pixel unit will repeatedly appear on the display screen for a plurality of times, and the number of times of appearance will be different according to the resolution of the display screen. D1-D8 are data lines in the display screen, S1-S4 are source lines from the IC, and SW1 and SW2 are provided with TFT switches to control whether the data is transmitted to the display screen. S1 is connected to D1 in the plane through the TFT switch and SW1, and connected to D5 in the plane through the TFT switch and SW 2; s2 is connected to D2 in the plane through the TFT switch and SW1, and connected to D6 in the plane through the TFT switch and SW 2; s3 is connected to D3 in the plane through the TFT switch and SW1, and connected to D7 in the plane through the TFT switch and SW 2; s4 is connected to D4 in the plane through the TFT switch and SW1, and connected to D8 in the plane through the TFT switch and SW 2;

taking the sub-pixel at S1 as an example, the data transmission process of the third embodiment of this patent is described: when G1 is turned on and SW1 is turned on, S1 transmits B sub-pixel ① to in-plane D1, SW1 is turned off, and SW2 is turned on, S1 transmits B sub-pixel ② to in-plane D5; when G2 is turned on and SW1 is turned on, S1 transmits the R sub-pixel ③ to the in-plane D1, SW1 is turned off, and SW2 is turned on, S1 transmits the G sub-pixel ④ to the in-plane D5; when G3 is turned on and SW1 is turned on, S1 transfers the G subpixel ⑤ to the in-plane D1, SW1 is turned off, and when SW2 is turned on, S1 transfers the G subpixel ⑥ to the in-plane D5; when G4 is on and SW1 is on, S1 transfers R subpixel ⑦ to in-plane D1, SW1 is off, and SW2 is on, S1 transfers R subpixel ⑧ to in-plane D5; the data transmission of S2-S4 is the same as the principle of S1 transmission, except that the data to be transmitted is different. The Y axis of the IC is reduced, the manufacturing cost is lower than that of the common IC, and the lower frame of the display screen is also reduced.

Referring to fig. 1, it can be seen that the source lines in the present embodiment are Column Inversion driven, but after special sub-pixel arrangement, Dot display can be shown on the display screen. Generally, Dot display is only performed by Dot driving, and although the display effect is good, the power consumption of the display screen is high due to the fact that the positive and negative inversion frequency of the voltage on the source line is high in one frame during Dot driving. By adopting the ColumnInversion driving mode, the positive and negative inversion frequency of the voltage on the source line in one frame can be reduced, so that the power consumption is reduced, and the display effect is not influenced. Different from the prior art, the technical scheme greatly reduces the number of source lines, reduces the length of a Y axis, greatly saves the manufacturing cost at the moment, reduces the power consumption during display, reduces the picture temperature, and improves the display quality of the display screen.

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims

1. A new power saving display screen architecture, comprising: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, eight data lines and four source lines;

2. The new power saving display screen architecture of claim 1, wherein one data line connects one subpixel of the subpixel pair and one subpixel of the other subpixel pair.

3. The new power saving display screen structure of claim 1 or 2, wherein one data line connects two sub-pixels in the sub-pixel pair.

4. The new power saving display screen architecture of claim 1, further comprising: a driving unit connected to the plurality of source lines.

5. The new power saving display screen structure of claim 1, wherein the plurality of sub-pixels are sequentially arranged in an array of R, G, B.