CN202837748U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN202837748U CN202837748U CN 201220302746 CN201220302746U CN202837748U CN 202837748 U CN202837748 U CN 202837748U CN 201220302746 CN201220302746 CN 201220302746 CN 201220302746 U CN201220302746 U CN 201220302746U CN 202837748 U CN202837748 U CN 202837748U
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Abstract
The utility mode discloses an array substrate which comprises at least five data lines, at least eight gate lines and a pixel region comprising at least one pixel group. The at least five data lines comprise a first data line, a second data line, a third data line, a fourth data line and a fifth data line. The pixel group is formed by the five data lines and the eight gate lines in an intersecting mode and comprises a four-line six-column pixel. Data driving signals with the same polarity are output on the same frame by all data lines, and data driving signals with opposite polarity are respectively output by the adjacent data lines. Correspondingly, the utility model further discloses a display device. Compared with traditional dot inversion, line inversion and column inversion, power consumption of the display device is greatly reduced. Compared with traditional frame inversion, frame quality is largely improved.
Description
Technical field
The utility model relates to lcd technology, relates in particular to a kind of array base palte and display device.
Background technology
In present liquid crystal panel drive pattern, common are a counter-rotating (dot inversion), row counter-rotating, row counter-rotating, frame counter-rotating four kinds of inversion modes such as (face counter-rotatings).
Because the some counter-rotating is well a lot of on the picture quality that shows with respect to other drive pattern, therefore, on the liquid crystal display of personal computer, employed liquid crystal panel drive pattern major part all is a counter-rotating now.But, owing to putting under the inversion mode, the polarity of the data drive signal that data line is contained will be reversed once after every row gate drive signal is opened, therefore, compared to other inversion modes, will bring the much larger loss of power, and adopt other modes can be so that the picture quality that shows reduces, flicker (Flicker) phenomenon the most easily occurs when particularly adopting the frame counter-rotating.
The utility model content
In view of this, fundamental purpose of the present utility model is to provide a kind of array base palte and display device, can reduce the loss of power under the prerequisite that guarantees picture quality.
For achieving the above object, the technical solution of the utility model is achieved in that
The invention provides a kind of array base palte, described array base palte comprises: at least five data lines, at least eight gate lines and pixel region, and described pixel region comprises at least one pixel groups; Wherein, described at least five data lines comprise the first data line, the second data line, the 3rd data line, the 4th data line and the 5th data line;
Described pixel groups is staggered to form by five data lines and eight gate lines, comprises four lines six row pixels;
One-row pixels connects two gate lines;
For the first row pixel and the second row pixel: be positioned at the pixel of first row and be positioned at tertial pixel and all be connected on the second data line; Be positioned at the pixel of secondary series and be positioned at the 4th pixel that is listed as and all be connected on the 3rd data line; The pixel that is positioned at the 5th row is connected on the 4th data line, and the pixel that is positioned at the 6th row is connected on the 5th data line;
For the third line pixel and fourth line pixel: the pixel that is positioned at first row is connected on the first data line; The pixel that is positioned at secondary series is connected on the second data line; Be positioned at tertial pixel and be positioned at the 5th pixel that is listed as and all be connected on the 3rd data line; Be positioned at the pixel of the 4th row and be positioned at the 6th pixel that is listed as and all be connected on the 4th data line;
Described each data line is exported the data drive signal of same polarity in same frame picture, and the opposite data drive signal of adjacent data line output polarity.
In such scheme, the arranged outside of any one or two data line that is arranged in two data lines at described pixel region two ends has virtual (dummy) pixel, the zone that described dummy pixel is arranged in the outside of described data line, is staggered to form with each described gate line.
In such scheme, be arranged in all dummy pixels in a data line outside, the dummy pixel on per two row is a dummy pixel groups, has a dummy pixel groups to connect on the described data line in adjacent two dummy pixel groups.
In such scheme, described liquid crystal display comprises: five * N bar data lines, eight * N bar gate lines and the pixel region that both interlock and surround, and described pixel region comprises N pixel groups, N is not less than 1 integer.
The present invention also provides a kind of display device, and described display device comprises above-mentioned array base palte.
The liquid crystal display that the utility model provides, each data line only needs the data drive signal of the same polarity of output in same frame picture, and the opposite data drive signal of adjacent data line (Data line) output polarity can realize double-point inversion, compares power consumption and has substantial degradation with traditional some counter-rotating, row counter-rotating, row counter-rotating; To compare power consumption identical with the counter-rotating of traditional frame, but improve a lot aspect picture quality.
Description of drawings
Fig. 1 is the structural representation of the utility model embodiment array basal plate;
Fig. 2 is the structural representation of array base palte in the utility model example two;
Description of reference numerals:
101, gate driver circuit; 102, data drive circuit; 103, pixel region; D1～D5, data line; G1～G8, gate line; P11～P46, pixel.
Embodiment
Embodiment one
As shown in Figure 1, the array base palte in the utility model comprises gate driver circuit 101, data drive circuit 102 and pixel region 103; Described pixel region 103 can comprise one or more pixel groups, and each pixel groups is staggered to form by eight gate lines and five data lines, comprises 24 pixels, and 24 pixels list in four lines six respectively.
As shown in Figure 1, gate driver circuit 101 comprises eight gate lines G 1～G8, and gate driver circuit 101 sequentially produces gate drive signal SG1～SG8, and transmits via gate lines G 1～G8 respectively.Data drive circuit 102 comprises five data line D1～D5, and data drive circuit produces data drive signal SD1～SD5, and respectively via data line D1～D5 transmission.Each gate lines G 1～G8 is the straight line that is parallel to each other, each data line D1～D5 is the straight line for being parallel to each other also, in the interlaced area of gate line and data line, form pixel, as shown in Figure 1, pixel region 103 comprises a pixel groups, is staggered to form by gate lines G 1～G8 and data line D1～D5, has comprised four lines six row totally 24 pixels, wherein, two data line D1, the D5 at place, two ends all have a side for empty.
Particularly, be connected on two gate lines with delegation's pixel, as shown in Figure 1, the first row pixel is connected on gate lines G 1 and the gate lines G 2, the second row pixel is connected on gate lines G 3 and the gate lines G 4, the third line pixel is connected on gate lines G 5 and the gate lines G 6, and the fourth line pixel is connected on gate lines G 7 and the gate lines G 8.Wherein, neighbor is connected on the different gate lines in every delegation pixel, as: for the first row pixel among Fig. 1, be connected on gate lines G 1 and the gate lines G 2, wherein, pixel P11 is connected on the gate lines G 1, pixel P12 is connected to gate lines G 1, and P13 is connected on the gate lines G 1 ..., pixel P15 is connected on the gate lines G 2, and pixel P16 is connected on the gate lines G 1.
For the first row pixel and the second row pixel: be positioned at pixel P11 and the P21 of first row and be positioned at tertial pixel P13 and P23 all is connected on the data line D2; Be positioned at pixel P12 and the P22 of secondary series and be positioned at the 4th pixel P14 and the P24 that is listed as and all be connected on the data line D3; The pixel P15 and the P25 that are positioned at the 5th row are connected on the data line D4, and the pixel P16 and the P26 that are positioned at the 6th row are connected on the data line D5.
For the third line pixel and fourth line pixel: the pixel P31 and the P41 that are positioned at first row are connected on the data line D1; The pixel P32 and the P42 that are positioned at secondary series are connected on the data line D2; Be positioned at tertial pixel P33 and P43 and be positioned at the 5th pixel P35 and the P45 that is listed as and all be connected on the data line D3; Be positioned at pixel P34 and the P44 of the 4th row and be positioned at the 6th pixel P36 and the P46 that is listed as and all be connected on the data line D4.
For same frame picture, the data drive signal of every data line output remains unchanged, and only needs to guarantee that the data drive signal of data line D1, D3, D5 output is opposite with the data drive signal polarity of data line D2, D4 output.Every conversion one frame picture, the polarity of the data drive signal of exporting on each data line once, that is: for each bar data line, with the voltage transformation of its loading once, be transformed into and be lower than Vcom or be transformed into and be higher than Vcom from being lower than Vcom from being higher than common electric voltage (Vcom), that is to say, the positive polarity data drive signal of exporting on described each data line is reversed to negative polarity or the data drive signal of negative polarity is reversed to positive polarity.
Particularly, for current picture, data line D1, D3, D5 are in same voltage levvl, are higher than Vcom or are lower than Vcom, export the data drive signal of same polarity; Data line D2, D4 are in same voltage levvl always, are lower than Vcom or are higher than Vcom, export the data drive signal of same polarity; When then arriving the next frame picture, data line D1, D3, D5 are in the voltage that is higher than Vcom, the data drive signal of output cathode; Data line D2, D4 are in the voltage that is lower than Vcom, the data drive signal of output negative pole.Like this, from the present frame picture to the next frame picture, the data drive signal of each data line output only need to be changed once, can realize the double-point inversion of present frame picture and its next frame picture, and the mutual data drive signal of data line book need to be changed repeatedly in the existing some counter-rotating, therefore, above-mentioned double-point inversion will reduce power supply (source) driving power consumption of liquid crystal display greatly.
Embodiment two
In the practical application, can also be in arranged outside virtual (dummy) pixel of any one or two data line of two data lines that are arranged in described pixel region two ends, the zone that described dummy pixel is arranged in the outside of described data line, is staggered to form with each described gate line.Be arranged in all dummy pixels in a data line outside, the dummy pixel on per two row is a dummy pixel groups, has a dummy pixel groups to connect on the described data line in adjacent two dummy pixel groups.
In the present embodiment, the structure of array base palte is basic identical in the structure of array base palte and above-described embodiment one, difference is: data line D1 and the data line D5 outside at place, pixel region 103 two ends arrange respectively the dummy pixel, are used for the data line D1 at place, balance two ends and the load of D5.Particularly, in the zone that is staggered to form in the outside of data line D1 and D5, with gate lines G 1～G8 the dummy pixel is set, arranges altogether eight, like this, comprised 32 pixels that are positioned at four lines six row in the pixel groups, wherein, the two row pixels at place, two ends are the dummy pixel.Wherein, for the first row pixel and the second row pixel: the pixel that is positioned at first row is the dummy pixel, is connected on the data line D1; The pixel that is positioned at the 8th row is that the dummy pixel is that sky connects.For the third line pixel and fourth line pixel: the pixel that is positioned at first row is that the dummy pixel is that sky connects, and the pixel that is positioned at the 8th row is the dummy pixel, is connected on the data line D5.So, by dummy pixel balance the has been set data line D1 at two ends places and the load of D5.
For the first row pixel and the second row pixel: the pixel P13 and the P23 that are positioned at pixel P11 and the P21 of secondary series and are positioned at the 4th row all are connected on the data line D2; Be positioned at tertial pixel P12 and P22 and be positioned at the 5th pixel P14 and the P24 that is listed as and all be connected on the data line D3; The pixel P15 and the P25 that are positioned at the 6th row are connected on the data line D4, and the pixel P16 and the P26 that are positioned at the 7th row are connected on the data line D5.
For the third line pixel and fourth line pixel: the pixel P31 and the P41 that are positioned at secondary series are connected on the data line D1; Being positioned at tertial pixel P32 and P42 is connected on the data line D2; Be positioned at pixel P33 and the P43 of the 4th row and be positioned at the 6th pixel P35 and the P45 that is listed as and all be connected on the data line D3; Be positioned at pixel P34 and the P44 of the 5th row and be positioned at the 7th pixel P36 and the P46 that is listed as and all be connected on the data line D4.
Here, also can be only in data line D1 and data line D5 any one arranged outside dummy pixel.
Embodiment three
Array base palte in the present embodiment comprises gate driver circuit, data drive circuit and pixel region.Wherein, comprise N pixel groups in the described pixel region, the structure of each pixel groups is identical with pixel groups structure among the embodiment one, and corresponding, gate driver circuit includes N*8 bar gate line, and data drive circuit includes N*5 bar data line.Wherein, N is not less than 2 integer.Described each data line is exported the data drive signal of same polarity in same frame picture, and the opposite data drive signal of adjacent data line output polarity.
Here, be arranged in two data lines at described pixel region two ends, the arranged outside dummy pixel of any data line perhaps, can also all arrange the dummy pixel in the outside of described two data lines therein.Described dummy pixel is arranged on the zone that described data line and each gate line intersect, for N*4 capable.
Embodiment four
The present embodiment provides a kind of display device, this display device includes any one above-mentioned array base palte, and described display device can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
The above is preferred embodiment of the present utility model only, is not be used to limiting protection domain of the present utility model.
Claims (5)
1. an array base palte is characterized in that, described array base palte comprises: at least five data lines, at least eight gate lines and pixel region, and described pixel region comprises at least one pixel groups; Wherein, described at least five data lines comprise the first data line, the second data line, the 3rd data line, the 4th data line and the 5th data line;
Described pixel groups is staggered to form by five data lines and eight gate lines, comprises four lines six row pixels;
One-row pixels connects two gate lines;
For the first row pixel and the second row pixel: be positioned at the pixel of first row and be positioned at tertial pixel and all be connected on the second data line; Be positioned at the pixel of secondary series and be positioned at the 4th pixel that is listed as and all be connected on the 3rd data line; The pixel that is positioned at the 5th row is connected on the 4th data line, and the pixel that is positioned at the 6th row is connected on the 5th data line;
For the third line pixel and fourth line pixel: the pixel that is positioned at first row is connected on the first data line; The pixel that is positioned at secondary series is connected on the second data line; Be positioned at tertial pixel and be positioned at the 5th pixel that is listed as and all be connected on the 3rd data line; Be positioned at the pixel of the 4th row and be positioned at the 6th pixel that is listed as and all be connected on the 4th data line;
Described each data line is exported the data drive signal of same polarity in same frame picture, and the opposite data drive signal of adjacent data line output polarity.
2. array base palte according to claim 1, it is characterized in that, the arranged outside of any one or two data line that is arranged in two data lines at described pixel region two ends has virtual pixel, the zone that described virtual pixel is arranged in the outside of described data line, is staggered to form with each described gate line.
3. array base palte according to claim 2 is characterized in that,
Be arranged in all virtual pixels in a data line outside, the virtual pixel on per two row is a virtual pixel group, has a virtual pixel group to connect on the described data line in adjacent two virtual pixel groups.
4. described array base palte according to claim 1 is characterized in that, described liquid crystal display comprises: five * N bar data lines, eight * N bar gate lines and the pixel region that both interlock and surround, and described pixel region comprises N pixel groups, N is not less than 1 integer.
5. a display device is characterized in that, described display device comprises such as each described array base palte of claim 1 to 4.
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| CN 201220302746 CN202837748U (en) | 2012-06-25 | 2012-06-25 | Array substrate and display device |
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| CN 201220302746 CN202837748U (en) | 2012-06-25 | 2012-06-25 | Array substrate and display device |
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