CN108281087B - Array substrate, manufacturing method and display screen - Google Patents
Array substrate, manufacturing method and display screen Download PDFInfo
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- CN108281087B CN108281087B CN201810053993.7A CN201810053993A CN108281087B CN 108281087 B CN108281087 B CN 108281087B CN 201810053993 A CN201810053993 A CN 201810053993A CN 108281087 B CN108281087 B CN 108281087B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2003—Display of colours
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Abstract
The application discloses an array substrate, a manufacturing method and a display screen. The array substrate includes: the pixel layer comprises first sub-pixels, second sub-pixels and third sub-pixels which are different in color and are arranged in columns; the driving circuit is provided with a first data line, a second data line and a third data line; the metal layer is provided with a first wire for connecting the first sub-pixel and the first data line, a second wire for connecting the second sub-pixel and the second data line and a third wire for connecting the third sub-pixel and the third data line; the metal layer comprises at least two layers, and the first routing, the second routing and the third routing are distributed on the at least two layers of metal layer, so that the driving circuit scans the sub-pixels according to a preset scanning sequence. In this way, the sub-pixels can be connected to the required data lines by arranging the traces, so that the driving circuit scans the sub-pixels in a preset scanning sequence.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a manufacturing method and a display screen.
Background
The resolution of the display screen can be characterized by PPI (Pixels Per Inch). With the progress of display technology, the resolution requirement of the display screen is higher, i.e. the number of pixels in a unit area is higher. As PPIs are higher and higher, the light emitting area of a single pixel is smaller and smaller, which makes FMM (Fine Metal Mask) manufacturing difficult.
At present, in order to solve this problem, a mask is proposed, as shown in fig. 1, the mask includes a flat plate body, where an opening is formed on the flat plate body, and the opening is used to form adjacent similar sub-pixels in adjacent main pixels; wherein the main pixel comprises three mutually separated sub-pixels R (red), B (blue), G (green). The mask plate is characterized in that the number of the openings of the mask plate is multiple, the openings are sequentially arranged along the row direction and the column direction, each opening is used for sharing four similar sub-pixels of the main pixel, the four similar sub-pixels are adjacent to each other from top to bottom and the four similar sub-pixels are adjacent to each other from left to right, and the sub-pixels corresponding to all the openings are the same in type. Through the mode, the manufacturing yield of the mask plate can be improved, and the resolution of the display panel can be improved.
However, as shown in fig. 1, the display panel manufactured in the above manner is limited by the wiring method, when the driving circuit scans the pixels, the scanning sequence is sequentially repeated for the first column red sub-pixel, the second column blue sub-pixel, the fourth column green sub-pixel, the third column blue sub-pixel, the fifth column green sub-pixel, the sixth column red sub-pixel, and the seventh column red sub-pixel, that is, the pixel scanning sequence is RBGBGR … … due to the wiring method, but some driving circuits do not support this scanning method.
Disclosure of Invention
The embodiment of the application provides an array substrate, which is used for solving the problem that when four sub-pixels with the same color share one FMM opening in the prior art, the pixel arrangement of the array substrate is not matched with the scanning mode of a driving circuit.
The embodiment of the application adopts the following technical scheme:
the application discloses array substrate includes:
the pixel layer comprises first sub-pixels, second sub-pixels and third sub-pixels which are different in color and are arranged in columns;
the driving circuit is provided with a first data line, a second data line and a third data line;
the metal layer is provided with a first wiring for connecting the first sub-pixel and the first data line, a second wiring for connecting the second sub-pixel and the second data line and a third wiring for connecting the third sub-pixel and the third data line;
the metal layer comprises at least two layers, and the first routing, the second routing and the third routing are distributed in the at least two layers of metal layer, so that the driving circuit scans the sub-pixels according to a preset scanning sequence.
Optionally, the first sub-pixel, the second sub-pixel and the third sub-pixel are repeatedly arranged every six columns, wherein in every six columns, the first sub-pixel is located in the first column and the sixth column, the second sub-pixel is located in the second column and the third column, and the third sub-pixel is located in the fourth column and the fifth column;
in every six rows, the first data lines are positioned in the first row and the fourth row, the first routing connected with the first sub-pixels in the first row extends to be connected with the first data lines in the first row, and the first routing connected with the first sub-pixels in the sixth row extends to be connected with the first data lines in the fourth row;
in every sixth row, the second data lines are positioned in a second row and a fifth row, the second routing connected with the second sub-pixels in the second row extends to be connected with the second data lines in the second row, and the second routing connected with the second sub-pixels in the third row extends to be connected with the second data lines in the fifth row;
in every sixth row, the third data lines are located in the third row and the sixth row, the third routing lines connected with the third sub-pixels in the fourth row extend to be connected with the third data lines in the third row, and the third routing lines connected with the third sub-pixels in the fifth row extend to be connected with the third data lines in the sixth row.
Optionally, the four adjacent sub-pixels with the same color, which are arranged vertically and horizontally, share one mask plate, wherein in every six rows, the second trace connected to the second sub-pixel in the third row and the first trace connected to the first sub-pixel in the sixth row and located in the same row as the second trace are located in different metal layers.
Optionally, every other second wire connected to the third row of the second sub-pixels is disposed in the first metal layer, the first wires connected to the sixth row of the first sub-pixels and located in different rows from the second wires located in the first metal layer are disposed in the first metal layer, and the rest of the first wires, the second wires, and the third wires are disposed in the second metal layer.
Optionally, the first metal layer and the second metal layer are disposed adjacent to each other, and an insulating layer is disposed between the first metal layer and the second metal layer.
Optionally, the first metal layer and the second metal layer are both made of ITO/Ag/ITO.
Optionally, the first metal layer is formed by a mask, and the second metal layer is formed by a mask.
Optionally, a via hole is formed at one end of each wire connected to the data line, and each wire is connected to the data line through metal filled in the via hole.
Optionally, the first sub-pixel is a red sub-pixel, the second sub-pixel is a blue sub-pixel, the third sub-pixel is a green sub-pixel, and the scanning sequence of the driving circuit is sequentially repeated red, blue, and green.
The manufacturing method of the array substrate comprises the following steps:
forming a substrate body;
forming a first metal layer by using a mask plate;
forming an insulating layer on the first metal layer;
forming a second metal layer by using a mask plate;
and forming a pixel layer by using a mask plate.
The display screen comprises the array substrate.
The embodiment of the application adopts at least one technical scheme which can achieve the following beneficial effects:
in the array substrate, the metal layer comprises at least two layers, and the first routing wire, the second routing wire and the third routing wire are distributed on the at least two layers of metal layer. With such an arrangement, interference among the wires can be reduced, and when the number of columns (where the number of columns refers to the number of columns of the sub-pixels) of some wires among the first wire, the second wire and the third wire is large, the wires can be arranged on one metal layer, and the other wires can be arranged on the other metal layer. In this way, the sub-pixels can be connected to the required data lines as required, enabling the drive circuit to scan the sub-pixels in a preset scan order.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic structural diagram of an array substrate in the prior art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a plan circuit diagram of an array substrate according to an embodiment of the present application.
In fig. 1-3:
a substrate body-1; a metal layer-2; a pixel layer-3; a drive circuit-4; an insulating layer-5; a first metal layer-21; a second metal layer-22 a first trace-23; a second trace-24; a third trace-25; (ii) a A first subpixel-31; a second subpixel-32; a third subpixel-33; contact hole-2A; a first data line-41; a second data line-42; a third data line-43; the first routing 231; a second trace-241.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 2 and 3, the array substrate of the present application includes a substrate body 1, a metal layer 2 sequentially disposed on the substrate body 1, a pixel layer 3, and a driving circuit 4 disposed on the substrate body 1. The pixel layer 3 includes first, second, and third sub-pixels 31, 32, and 33 of different colors and arranged in columns. The driving circuit 4 is provided with a first data line 41, a second data line 42, and a third data line 43. The metal layer 2 is provided with a first trace 23, a second trace 24 and a third trace 25, wherein the first trace 23 connects the first sub-pixel 31 and the first data line 41, the second trace 24 connects the second sub-pixel 32 and the second data line 42, and the third trace 25 connects the third sub-pixel 33 and the third data line 43.
In the array substrate, the metal layer 2 includes at least two layers, and the first trace 23, the second trace 24 and the third trace 25 are distributed on the at least two layers of metal layer 2. With such an arrangement, interference among the traces can be reduced, and when the number of columns (where the number of columns refers to the number of columns of the sub-pixels) spanned by some of the first trace 23, the second trace 24, and the third trace 25 is large, the traces can be disposed on one metal layer 2, and the rest of the traces can be disposed on the other metal layer 2. In this way, the sub-pixels can be connected to the required data lines as required, causing the drive circuit 4 to scan the sub-pixels in the preset scanning order.
It should be noted that the columns of the sub-pixels arranged in columns refer to a row arranged along the extending direction of the data lines, and the colors of the sub-pixels on the same data line are the same.
The material of the pixel layer 3 is the same as that of the normal pixel layer 3. The pixel layer 3 is provided with a plurality of rows of first subpixels 31, a plurality of rows of second subpixels 32, and a plurality of rows of third subpixels 33, and the arrangement of the three subpixels may be set as required. In one example, the first subpixel 31, the second subpixel 32, and the third subpixel 33 are repeatedly arranged every six columns, in which the first subpixel 31 is positioned in the first column and the sixth column, the second subpixel 32 is positioned in the second column and the third column, and the third subpixel 33 is positioned in the fourth column and the fifth column.
In other words, the above-mentioned sub-pixel arrangement means that the first column is a first sub-pixel 31, the second column is a second sub-pixel 32, the third column is a second sub-pixel 32, the fourth column is a third sub-pixel 33, the fifth column is a third sub-pixel 33, the sixth column is a first sub-pixel 31, the seventh column is a first sub-pixel 31, the eighth column is a second sub-pixel 32, the ninth column is a second sub-pixel 32, the tenth column is a third sub-pixel 33, the eleventh column is a third sub-pixel 33, the twelfth column is a first sub-pixel 31, and the thirteenth column is a first sub-pixel 31 … …, which are repeatedly arranged in sequence.
Through the arrangement, the upper, lower, left and right adjacent positions can be the same color sub-pixels. Therefore, when the pixel layer 3 is manufactured, the number of the openings of the mask plate can be four, four sub-pixels adjacent to each other in the vertical and horizontal directions share the same mask plate, and the manufacturing yield of the mask plate and the resolution of the array substrate are improved.
The first, second, and third sub-pixels 31, 32, and 33 may be R (red), B (blue), and G (green) sub-pixels, respectively. The red, green and blue sub-pixels are mixed according to different proportions and strengths to generate various color changes. Specifically, the first sub-pixel 31 may be any one of red, green and blue sub-pixels, and the second sub-pixel 32 may be one of any two sub-pixels except the first sub-pixel 31, for example, when the first sub-pixel 31 is a red sub-pixel, the second sub-pixel 32 may be any one of blue and green sub-pixels.
Preferably, the first sub-pixel 31 is a red sub-pixel, the second sub-pixel 32 is a blue sub-pixel, and the third sub-pixel 33 is a green sub-pixel. In this way, when the data lines are straight lines, it is convenient to realize the pixel arrangement order (red, blue, green, red, blue, green … …) supported by the driving circuit 4 by disposing the wirings.
Each sub-pixel is connected with one wire, namely the wires connected with different sub-pixels are separated from each other. The number of each type of routing can be set according to the number of corresponding sub-pixels. Each of the traces may include a portion extending along the data line and a portion extending perpendicular to the data line as needed. Each wire is located on the same metal layer 2, that is, the part of each wire extending in each direction is located on the same metal layer, so as to facilitate etching.
When the sub-pixels are repeatedly arranged every six columns in the above manner, in every six columns (corresponding to every six columns of the sub-pixels), the first data line 41 is located in the first column and the fourth column, the first routing line 23 connected to the first sub-pixel 31 in the first column extends to be connected to the first data line 41 in the first column, and the first routing line 23 connected to the first sub-pixel 31 in the sixth column extends to be connected to the first data line 41 in the fourth column. The second data lines 42 are located in the second column and the fifth column, the second traces 24 connected to the second column of the second sub-pixels 32 extend to be connected to the second column of the second data lines 42, and the second traces 24 connected to the third column of the second sub-pixels 32 extend to be connected to the fifth column of the second data lines 42. The third data line 43 is located in the third column and the sixth column, the third trace 25 connected to the third sub-pixel 33 in the fourth column extends to be connected to the third data line 43 in the third column, and the third trace 25 connected to the third sub-pixel 33 in the fifth column extends to be connected to the third data line 43 in the sixth column.
With this arrangement, when the scanning order of the driving circuit 4 is the first sub-pixel 31, the second sub-pixel 32, the third sub-pixel 33, and the first sub-pixel 31 … …, the data lines led out from the data driver of the driving circuit 4 are all straight lines, which facilitates etching of the data lines.
Every four sub-pixels which are adjacent from top to bottom and left to right (located on four corners of the rectangle) and have the same color share one mask plate, and in every six rows, the second wiring 241 connected with the third row of the second sub-pixels 32 and the first wiring 231 connected with the sixth row of the first sub-pixels 31 and located in the same row with the second wiring 241 are located on different metal layers. Due to the arrangement, the shape of the wiring is small, the wiring is convenient to etch, and trouble and labor are saved. In a specific example, every other one of the second traces 241 connected to the third row of the second sub-pixels 32 is disposed on the first metal layer 21, the first traces 231 connected to the sixth row of the first sub-pixels 31 and located in different rows from the second traces 241 located on the first metal layer 21 are disposed on the first metal layer 21, and the rest of the first traces 23, the second traces 24, and the third traces 25 are disposed on the second metal layer 22. Therefore, etching and wiring are further facilitated, and trouble and labor are saved.
Of course, the traces may be disposed in other manners, for example, in every six columns, the first traces 231 connected to the sixth column of the first sub-pixels 31 are all located in the first metal layer 21, and the rest of the traces are located in the second metal layer 22; or, in every six columns, the second traces 241 connected to the second sub-pixels 32 in the third column are all located in the first metal layer 21, and the rest of the traces are located in the second metal layer 22.
One end of each wire, which is connected with the data line, can be provided with a through hole 2A, and the through holes 2A are filled with metal to realize the electrical connection with the data line. So set up, simple structure, convenient processing preparation.
In the array substrate, only two metal layers 2 of the first metal layer 21 and the second metal layer 22 may be included. When the two metal layers 2 are arranged, the pixel arrangement mode can be matched with the scanning sequence of the driving circuit 4 through wiring, and the structure is simple and the manufacture is convenient. The two metal layers 2 can be made of the same material and are all ITO (indium tin oxide)/Ag/ITO, namely a three-layer structure, the bottom is provided with an ITO layer, the middle is covered with an Ag layer, the upper is covered with an ITO layer, and the indium tin oxide has low cost, good conductivity and convenient processing and etching. The thickness of the two metal layers 2 can be set as required.
The first metal layer 21 and the second metal layer 22 may be disposed adjacently. When two metal layers 2 are provided, the first metal layer 21 may be closer to the substrate body 1, or the second metal layer 22 may be closer to the substrate body 1. When the first metal layer 21 and the second metal layer 22 are disposed adjacently, the insulating layer 5 is disposed between the two metal layers 2, and the two metal layers 2 are insulated by the insulating layer 5.
The first metal layer 21 may be formed by a mask and the second metal layer 22 may be formed by a mask to facilitate processing of the metal layer 2. When the array substrate is manufactured, the substrate body 1 is formed, then the first metal layer 21 is formed by using the mask plate, the insulating layer 5 is formed on the first metal layer 21, the second metal layer 22 is formed by using the mask plate, and then the pixel layer 3 is formed by using the mask plate.
The display screen of this application includes foretell array substrate. In the display screen, the metal layer 2 includes at least two layers, and the first trace 23, the second trace 24 and the third trace 25 are distributed on the at least two layers of metal layer 2. With such an arrangement, interference among the traces can be reduced, and when the number of columns (where the number of columns refers to the number of columns of the sub-pixels) spanned by some of the first trace 23, the second trace 24, and the third trace 25 is large, the traces can be disposed on one metal layer 2, and the rest of the traces can be disposed on the other metal layer 2. In this way, the sub-pixels can be connected to the required data lines as required, causing the drive circuit 4 to scan the sub-pixels in the preset scanning order.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (8)
1. An array substrate, comprising:
the pixel layer comprises first sub-pixels, second sub-pixels and third sub-pixels which are different in color and are arranged in columns;
the driving circuit is provided with a first data line, a second data line and a third data line;
the metal layer is provided with a first wiring for connecting the first sub-pixel and the first data line, a second wiring for connecting the second sub-pixel and the second data line and a third wiring for connecting the third sub-pixel and the third data line;
the metal layer comprises at least two layers, and the first routing, the second routing and the third routing are distributed in the at least two layers of metal layer, so that the driving circuit scans the sub-pixels according to a preset scanning sequence;
the first sub-pixels, the second sub-pixels and the third sub-pixels are repeatedly arranged in every six columns, wherein in every six columns, the first sub-pixels are located in the first column and the sixth column, the second sub-pixels are located in the second column and the third column, and the third sub-pixels are located in the fourth column and the fifth column;
in every six rows, the first data lines are positioned in the first row and the fourth row, the first routing connected with the first sub-pixels in the first row extends to be connected with the first data lines in the first row, and the first routing connected with the first sub-pixels in the sixth row extends to be connected with the first data lines in the fourth row;
in every sixth row, the second data lines are positioned in a second row and a fifth row, the second routing connected with the second sub-pixels in the second row extends to be connected with the second data lines in the second row, and the second routing connected with the second sub-pixels in the third row extends to be connected with the second data lines in the fifth row;
in every sixth row, the third data line is positioned in a third row and a sixth row, the third routing connected with the third sub-pixel in the fourth row extends to be connected with the third data line in the third row, and the third routing connected with the third sub-pixel in the fifth row extends to be connected with the third data line in the sixth row;
four adjacent sub-pixels with the same color, namely, the upper sub-pixel, the lower sub-pixel, the left sub-pixel, the right sub-pixel and the color sub-pixel share one mask plate, wherein in every six rows, the second wiring connected with the second sub-pixel in the third row and the first wiring connected with the first sub-pixel in the sixth row and positioned in the same row with the second wiring are positioned on different metal layers;
every other second routing line connected with the second sub-pixels in the third row is arranged on the first metal layer, the first routing lines connected with the first sub-pixels in the sixth row and in different rows with the second routing lines located on the first metal layer are arranged on the first metal layer, and the rest first routing lines, the rest second routing lines and the rest third routing lines are arranged on the second metal layer.
2. The array substrate of claim 1, wherein the first metal layer and the second metal layer are disposed adjacent to each other with an insulating layer disposed therebetween.
3. The array substrate of claim 1, wherein the first metal layer and the second metal layer are made of ITO/Ag/ITO.
4. The array substrate according to claim 1, wherein the first metal layer is formed by a mask plate, and the second metal layer is formed by a mask plate.
5. The array substrate of claim 2, wherein one end of each trace connected to the data line is provided with a via hole, and each trace is connected to the data line through a metal filled in the via hole.
6. The array substrate of claim 1, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a blue sub-pixel, the third sub-pixel is a green sub-pixel, and the driving circuit sequentially scans red, blue, and green.
7. A manufacturing method of an array substrate is characterized by comprising the following steps:
forming a substrate body;
forming a first metal layer by using a mask plate;
forming an insulating layer on the first metal layer;
forming a second metal layer by using a mask plate;
forming a pixel layer by using a mask plate;
the pixel layer comprises first sub-pixels, second sub-pixels and third sub-pixels which are different in color and are arranged in columns;
the array substrate further includes: the driving circuit is provided with a first data line, a second data line and a third data line; a first wire connecting the first sub-pixel and the first data line, a second wire connecting the second sub-pixel and the second data line, and a third wire connecting the third sub-pixel and the third data line;
the first sub-pixels, the second sub-pixels and the third sub-pixels are repeatedly arranged in every six columns, wherein in every six columns, the first sub-pixels are located in the first column and the sixth column, the second sub-pixels are located in the second column and the third column, and the third sub-pixels are located in the fourth column and the fifth column;
in every six rows, the first data lines are positioned in the first row and the fourth row, the first routing connected with the first sub-pixels in the first row extends to be connected with the first data lines in the first row, and the first routing connected with the first sub-pixels in the sixth row extends to be connected with the first data lines in the fourth row;
in every sixth row, the second data lines are positioned in a second row and a fifth row, the second routing connected with the second sub-pixels in the second row extends to be connected with the second data lines in the second row, and the second routing connected with the second sub-pixels in the third row extends to be connected with the second data lines in the fifth row;
in every sixth row, the third data line is positioned in a third row and a sixth row, the third routing connected with the third sub-pixel in the fourth row extends to be connected with the third data line in the third row, and the third routing connected with the third sub-pixel in the fifth row extends to be connected with the third data line in the sixth row;
four adjacent sub-pixels with the same color, namely, the upper sub-pixel, the lower sub-pixel, the left sub-pixel, the right sub-pixel and the color sub-pixel share one mask plate, wherein in every six rows, the second wiring connected with the second sub-pixel in the third row and the first wiring connected with the first sub-pixel in the sixth row and positioned in the same row with the second wiring are positioned on different metal layers;
every other second routing line connected with the second sub-pixels in the third row is arranged on the first metal layer, the first routing lines connected with the first sub-pixels in the sixth row and in different rows with the second routing lines located on the first metal layer are arranged on the first metal layer, and the rest first routing lines, the rest second routing lines and the rest third routing lines are arranged on the second metal layer.
8. A display screen comprising the array substrate according to any one of claims 1 to 6.
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| CN201810053993.7A CN108281087B (en) | 2018-01-19 | 2018-01-19 | Array substrate, manufacturing method and display screen |
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| CN202837748U (en) * | 2012-06-25 | 2013-03-27 | 北京京东方光电科技有限公司 | Array substrate and display device |
| CN205231067U (en) * | 2015-12-24 | 2016-05-11 | 昆山国显光电有限公司 | Pixel , dot structure and display |
| CN106597802A (en) * | 2016-11-28 | 2017-04-26 | 武汉华星光电技术有限公司 | Mask, mask assembly and display panel |
| CN206619595U (en) * | 2017-03-10 | 2017-11-07 | 厦门天马微电子有限公司 | Display panel |
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