CN111463169B - 半导体装置的制造方法 - Google Patents
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
本发明提出一种半导体装置的制造方法,其包含在衬底上方形成第一介电层和穿过第一介电层的通孔;在通孔中形成多个虚设接触件;在虚设接触件上形成多个第一虚设导线;在上述第一虚设导线之间填入第二介电层,其中第二介电层具有第一气隙;移除虚设接触件和第一虚设导线以露出通孔并藉此于通孔上方形成第一导线沟槽;以及在通孔和第一导线沟槽中形成导孔和第一导线。本发明可以提升半导体装置的可靠度,同时降低成本并提升半导体装置的良品率。
Description
技术领域
本发明是关于半导体制造技术,特别是有关于具有互连结构的半导体装置的制造方法。
背景技术
随着半导体装置的尺寸持续缩减,邻近的互连结构、金属线或其他元件之间的电容耦合也增加,造成电阻电容延迟(RC delay)的问题变得严重,进而影响半导体装置的效能。解决上述问题的方法包含使用低介电常数介电材料形成介电层或者在介电层中形成气隙。与低介电常数介电材料相比,空气的介电常数更小,因此具有气隙的结构可以显著降低电容。
然而,这些方法虽大致符合需求,但仍无法在每个方面皆令人满意。因此需要进一步改良半导体装置的制造方法,以提升半导体装置的良品率。
发明内容
根据本发明的一些实施例,提供半导体装置的制造方法。此方法包含在衬底上方形成第一介电层和穿过第一介电层的通孔;在通孔中形成多个虚设接触件;在虚设接触件上形成多个第一虚设导线;在上述第一虚设导线之间填入第二介电层,其中第二介电层具有第一气隙;移除虚设接触件和第一虚设导线以露出通孔并藉此于通孔上方形成第一导线沟槽;以及在通孔和第一导线沟槽中形成接触件和第一导线。
本发明可以提升半导体装置的可靠度,同时降低成本并提升半导体装置的良品率。
附图说明
以下将配合所附图式详述本发明的实施例。应注意的是,依据产业上的标准做法,各种特征并未按照比例绘制且仅用以说明例示。事实上,可能任意地放大或缩小元件的尺寸,以清楚地表现出本发明的特征。
图1A~图1G是根据一些实施例绘示在制造半导体装置的各个阶段的剖面示意图。
图2A~图2C是根据一些其他实施例绘示在制造半导体装置的各个阶段的剖面示意图。
附图标记:
100、200~半导体装置 102~衬底
104、112、122、132、138~介电层 106、126~阻挡层
118、136~虚设导线 108、128~导线
120、121、134~沟槽 110~保护层
124~导线沟槽 114~通孔
127~接触件 116~虚设接触件
130、140、150~气隙
具体实施方式
以下根据本发明的一些实施例,描述半导体装置的制造方法。本发明提供新的形成气隙的方法,此方法藉由设置虚设导线,可以在不增加遮罩数量的情况下,避免形成气隙工艺时损伤导线,提升半导体装置的良品率,并且容易控制气隙的位置和尺寸,以调整成想要的介电常数值。
图1A~图1G是根据一些实施例绘示在制造半导体装置100的各个阶段的剖面示意图。本发明的半导体装置100的制造方法适用于在衬底102上形成互连结构,衬底102例如是一硅片,其上方可以形成任何所需的半导体元件,例如金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)、电阻、逻辑元件或类似的半导体元件,此处为了简化图式,仅以平整的衬底102表示。在本发明的叙述中,“衬底”一词包含半导体晶片上已形成的元件与覆盖在晶片上的各种涂层。
如图1A所示,半导体装置100包含衬底102。可以使用任何适用于半导体装置100的衬底材料。
然后,在衬底102上方形成介电层104、介电层中的导线108以及位于介电层104和导线108之间的阻挡层106。介电层104的材料可以包含二氧化硅、低介电常数介电材料或前述的组合。介电层104的形成可以使用沉积工艺,例如化学气相沉积工艺。
然后,可以腐蚀介电层104以形成沟槽,并且在沟槽中顺应性地形成阻挡层106。介电层104的腐蚀可以使用一或多层遮罩层(未绘示)。
然后在沟槽中顺应性地(conformally)形成阻挡层106,以防止导线108从沟槽中脱落,并且可以避免导线108的材料向外扩散而产生漏电等问题。阻挡层106的材料可以包含钛、氮化钛、氧化钛、钽、氮化钽、氧化钽、类似的材料或前述的组合。阻挡层106的形成可例如是原子层沉积工艺。
然后,在沟槽的剩余部分形成导线108。导线108的形成可以例如是物理气相沉积工艺。根据一些实施例,导线108的材料可以包含铜或多晶硅。
然后在介电层104和导线108上方形成保护层110,以防止后续工艺对导线108造成损伤或露出的导线108氧化。保护层110可以包含氮化硅,并可使用任何合适的沉积工艺,例如化学气相沉积工艺。
然后,如图1B所示,在介电层104和保护层110上方形成介电层112。介电层112的材料和形成方法可以选用介电层104的材料和形成方法。然后可以藉由一或多层遮罩层(未绘示)和腐蚀工艺腐蚀介电层112,以形成穿过介电层112的通孔114。其中,通孔114露出保护层110而不露出导线108,以防止导线108受损或氧化。
然后如图1C所示,在通孔114中形成虚设接触件116,且虚设接触件116位于110保护层正上方。根据一些实施例,虚设接触件116的材料可以包含光刻胶材料、旋涂碳、旋涂玻璃、旋涂有机硬遮罩(spin-on-hard mask,SOH)材料、有机平坦化层(organicplanarization layer,OPL)材料、非晶碳膜(amorphous carbon film)材料、抗反射膜(anti-reflection film)材料、类似的材料或前述的组合。虚设接触件116的形成可以使用任何合适的工艺,例如旋转涂布工艺或类似的工艺。
然后如图1D所示,在介电层112上方形成虚设导线118,其中虚设导线118的宽度大于虚设接触件116的宽度。虚设接触件116和虚设导线118将在后续工艺中被去除,并以实际具功能性的接触件和导线取代。根据一些实施例,可以在介电层112上方沉积虚设导线材料,然后可以藉由一或多层遮罩层(未绘示)和腐蚀工艺腐蚀虚设导线材料,以形成虚设导线118以及位于虚设导线118之间的沟槽120、121。可以使用任何合适的工艺形成虚设导线材料,例如等离子增强化学气相沉积工艺。在一些实施例中,虚设导线118的材料可以包含多晶硅、多晶锗、多晶硅锗、类似的材料或前述的组合。
虽然在此描述的实施例中,虚设接触件116和虚设导线118包含不同的材料,以具有较佳均匀度并减少孔洞的产生,但本发明不限于此。在另一些实施例中,虚设接触件116和虚设导线118可以包含相同的材料,以降低成本。
如图1D所示,由腐蚀所形成的沟槽120和121可延伸进入介电层112,使得沟槽120、121的底表面可低于虚设导线118的底表面。举例来说,沟槽120的底表面和沟槽121的底表面可以大致上对齐虚设导线118的底表面。此外,沟槽120的底表面大致上对齐沟槽121的底表面,但沟槽120的底表面也可以高于或低于沟槽121的底表面。沟槽120和121的深宽比和底表面的位置可以通过腐蚀来控制进而决定是否在其中形成气隙以及气隙的位置和尺寸,以调整间隙形成在想要的位置甚至想要的线宽间。举例来说,当沟槽的深宽比是在可以形成气隙的范围内,则较大的深宽比可以形成较大的气隙。
然后如图1E所示,在沟槽120和121中填入介电层122,然后将介电层122平坦化。介电层122的材料和形成方法可以选用介电层104的材料和形成方法,也可以使用其他合适的材料和形成方法。此外,虽然图1E未绘示介电层112和122之间的界面,但在介电层112和122使用不同材料的实施例中,介电层112和122之间会存在界面。
请参阅图1D及图1E所示,在深宽比较大的沟槽120中会形成气隙130,而深宽比较小的沟槽121中则不会形成气隙。因此,可以调整沟槽120和121的深宽比,使得沟槽120和121中皆具有气隙。根据一些实施例,用于形成气隙的沟槽的深宽比大于约2.5,例如大于约2.55,或大于约3.2。举例来说,宽度为约120纳米且深度为约386纳米的沟槽可以在其中形成气隙,且形成的气隙的高度为约201纳米且宽度为约87纳米。
值得一提的是,通过本发明的制造方法,沟槽120的底表面可低于虚设导线118的底表面,因此气隙130的底表面可低于虚设导线118的底表面。具体而言,本发明可透过调整沟槽120的底表面的位置以在想要的位置形成气隙130。此外,可以藉由控制沟槽120的深度和宽度来调整气隙130的尺寸,例如在可以形成气隙的深宽比范围内,较大的深宽比可以形成较大的气隙。因此,本发明容易控制气隙130的位置和尺寸。然后如图1F所示,移除虚设接触件116和虚设导线118,以再次露出通孔114并且形成导线沟槽124于通孔114上方。虚设接触件116和虚设导线118的移除可以使用干式腐蚀工艺、湿式腐蚀工艺或前述的组合。腐蚀工艺可以移除虚设接触件116和虚设导线118,而大致上不腐蚀介电层112和122,最后透过腐蚀工艺将通孔114下方的保护层110移除,准备进行后续导线电镀工艺。
然后如图1G所示,在通孔114和导线沟槽124中形成阻挡层126以及在阻挡层126上的接触件127和导线128。阻挡层126的材料和形成方法可以选用阻挡层106的材料和形成方法,并且接触件127和导线128的材料和形成方法可以选用导线108的材料和形成方法,但也可以使用其他合适的材料和形成方法。根据一些实施例,可以藉由双镶嵌(dualdamascene)工艺在一步骤中形成接触件127和导线128。在另一些实施例中,可以在不同步骤中形成接触件127和导线128。在形成导线128之后,可以藉由例如化学机械抛光工艺的平坦化工艺将导线128平坦化。
如图1G所示,气隙130的底表面低于导线128的底表面。当然,气隙130的底表面也可依实际需求而大致上等于或高于导线128的底表面。若气隙130的顶表面低于导线128的顶表面,可避免在导线128的平坦化工艺之后露出气隙130,其可能造成半导体装置100短路或失效等问题。举例来说,气隙130的顶表面可以低于导线128的顶表面约30纳米至约50纳米,例如约40纳米。
在上述实施例中,本发明提供一种具有气隙130的半导体装置100的制造方法,包含形成虚设接触件116和虚设导线118,然后在虚设导线118之间形成具有气隙130的介电层122,接着移除虚设接触件116和虚设导线118,并且形成接触件127和导线128。换句话说,本发明提供的方法是先形成介电层122再形成导线128,相较于先形成导线128再形成介电层122的方法,本发明提供的方法可以避免形成介电层122的工艺损伤导线128,提升半导体装置100的可靠度。
此外,由于无须担心导线128受损,可以更容易腐蚀出想要的沟槽形状,例如调整在其中形成气隙130的沟槽120的底表面的位置和深宽比,以控制气隙130的位置和尺寸,进而调整成想要的介电常数值。
另外,本发明提供的方法可以直接形成具有气隙130的介电层122,相较于腐蚀先形成的介电层再重新形成具有气隙的介电层的方法,本发明提供的方法可以减少使用的遮罩层的数量以及工艺步骤,并且可以使气隙130自对准地设置于导线128之间。
请参阅图2A~图2C,相较于图1A~图1G的实施例而言,以下的实施例不形成虚设接触件,只以虚设导线形成沟槽。举例而言,可在下方导线108之间设置气隙,以调整导线108之间的介电常数值。
如图2A所示,在衬底102上方形成介电层132,并且在介电层132上形成虚设导线136。介电层132的材料和形成方法可以选用前述介电层104的材料和形成方法,并且虚设导线136的材料和形成方法可以选用前述虚设导线118的材料和形成方法。
然后可以藉由一或多层遮罩层(未绘示)和腐蚀工艺腐蚀虚设导线136来形成沟槽134。在图2A中,沟槽134穿过虚设导线136,并且沟槽134的底表面低于虚设导线136的底表面,但本发明不限于此。可以调整沟槽134的底表面的位置和深宽比,以调整后续形成的气隙的位置和尺寸。
然后根据一些实施例,如图2B所示,可在虚设导线136之间填入介电层138,并且可以藉由化学机械抛光工艺将介电层138平坦化。介电层138的材料和形成方法可选用介电层132的材料和形成方法,但也可以使用其他合适的材料和形成方法。
然后根据一些实施例,如图2C所示,移除虚设导线136,以形成导线沟槽,并且在导线沟槽中形成阻挡层106和导线108。然后可以参照图1A~图1G和前述的方法,在导线108和介电层138上方形成保护层110、介电层112、122、阻挡层126、接触件127、导线128和气隙130,其中导线108位于接触件127和导线128正下方。另外,可以调整导线128之间的沟槽的深宽比,以形成额外的气隙150。
在上述实施例中,在导线108之间的介电层138和导线128之间的介电层122中形成气隙130、140和150,以调整成想要的介电常数值,减少电阻电容延迟的问题,提升半导体装置200的效能。
综上所述,本发明提供一种半导体装置的制造方法,其包含形成虚设接触件及/或虚设导线,然后在虚设导线之间形成具有气隙的介电层,接着移除虚设接触件及/或虚设导线,并且形成接触件及/或导线。由于本发明提供的方法是先形成介电层再形成导线,相较于先形成导线再形成介电层的方法,本发明提供的方法可以避免介电层的形成工艺损伤导线,提升半导体装置的可靠度。
此外,由于无须担心导线受损,可以更容易腐蚀出想要的沟槽形状,例如控制沟槽的底表面的位置和深宽比,以在沟槽中形成位于预定位置且具有预定尺寸的气隙,以调整成想要的介电常数值。
另外,由于本发明提供的方法直接形成具有气隙的介电层,相较于腐蚀原有的介电层再重新形成具有气隙的介电层的方法,本发明提供的方法可以减少遮罩层的数量并且减少工艺步骤,还可以使气隙自对准地设置于导线之间,因此可以降低成本并提升半导体装置的良品率。
虽然本发明已以多个实施例描述如上,但这些实施例并非用于限定本发明。本发明所属技术领域中技术人员应可理解,他们能以本发明实施例为基础,做各式各样的改变、取代和替换,以达到与在此描述的多个实施例相同的目的及/或优点。本发明所属技术领域中技术人员也可理解,此类修改或设计并未悖离本发明的精神和范围。因此,本发明的保护范围当视附的权利要求范围所界定的为准。
Claims (11)
1.一种半导体装置的制造方法,其特征在于,包括:
在一衬底上方形成一第一介电层和穿过该第一介电层的一通孔;
在该通孔中形成多个虚设接触件;
在所述多个虚设接触件上形成多个第一虚设导线;
在所述多个第一虚设导线之间填入一第二介电层,其中该第二介电层具有一第一气隙;
移除所述多个虚设接触件和所述多个第一虚设导线以露出该通孔并藉此于该通孔上方形成一第一导线沟槽;以及
在该通孔和该第一导线沟槽中形成一接触件和一第一导线;
其中,所述多个第一虚设导线的形成包括:
在该第一介电层上方沉积一第一虚设导线材料;以及
腐蚀该第一虚设导线材料,以形成所述多个第一虚设导线以及位于所述多个第一虚设导线之间的多个沟槽。
2.如权利要求1所述的半导体装置的制造方法,其特征在于,所述多个第一虚设导线的宽度大于所述多个虚设接触件的宽度。
3.如权利要求1所述的半导体装置的制造方法,其特征在于,所述多个沟槽延伸进入该第一介电层。
4.如权利要求1所述的半导体装置的制造方法,其特征在于,该第一气隙的顶表面低于该第一导线的顶表面。
5.如权利要求1所述的半导体装置的制造方法,其特征在于,该第一气隙的底表面低于该第一导线的底表面。
6.如权利要求1所述的半导体装置的制造方法,其特征在于,还包括在该通孔和该第一导线沟槽中顺应性地形成一第一阻挡层。
7. 如权利要求1所述的半导体装置的制造方法,其特征在于,还包括:
在形成该第一介电层之前,在该衬底上方形成一第三介电层;以及
在该第三介电层中形成一第二导线,其中该第二导线位于该接触件正下方。
8.如权利要求7所述的半导体装置的制造方法,其特征在于,该第二导线的形成包括:
在该衬底上方形成一第二虚设导线;
在该第二虚设导线之间填入该第三介电层;
移除该第二虚设导线以形成一第二导线沟槽;以及
在该第二导线沟槽中形成该第二导线。
9.如权利要求7所述的半导体装置的制造方法,其特征在于,该第三介电层具有一第二气隙。
10.如权利要求9所述的半导体装置的制造方法,其特征在于,该第二气隙的底表面低于该第二导线的底表面。
11. 如权利要求7所述的半导体装置的制造方法,其特征在于,包括:
在形成该第一介电层之前,形成一保护层覆盖该第二导线的顶表面;以及
在移除所述多个虚设接触件和所述多个第一虚设导线之后,移除该通孔下方的该保护层。
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