CN111463138A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN111463138A CN111463138A CN202010312290.9A CN202010312290A CN111463138A CN 111463138 A CN111463138 A CN 111463138A CN 202010312290 A CN202010312290 A CN 202010312290A CN 111463138 A CN111463138 A CN 111463138A
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- 239000003292 glue Substances 0.000 claims abstract description 56
- 238000004806 packaging method and process Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000009966 trimming Methods 0.000 claims abstract description 22
- 238000004026 adhesive bonding Methods 0.000 claims abstract description 10
- 238000000227 grinding Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 51
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract description 12
- 235000012431 wafers Nutrition 0.000 description 188
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- 238000000576 coating method Methods 0.000 description 1
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- 230000002542 deteriorative effect Effects 0.000 description 1
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- 238000010297 mechanical methods and process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Abstract
The invention discloses a semiconductor device and a preparation method thereof, wherein the preparation method comprises the steps of providing a packaged chip, forming a positioning groove on the edge of the packaged chip, and forming a bottom wall of the positioning groove to have a first thickness; trimming the positioning groove of the packaged chip to enable the bottom wall of the positioning groove to have a second thickness, wherein the second thickness is smaller than the first thickness; providing a packaging substrate, forming a glue layer on the packaging substrate, and arranging the packaging chip on the glue layer and gluing the packaging chip with the glue layer; and trimming and grinding the packaged chip to remove the bottom wall of the positioning groove. According to the preparation method of the semiconductor device, the damage of the semiconductor device can be reduced, and the yield of the semiconductor device can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
In a 3D IC technology platform, a wafer bonding technology is increasingly widely applied, the wafer quality requirement is high due to the fact that two or more wafers are bonded, a roughly hat-brim shape is formed on one side of a packaged chip formed after wafer bonding in the related technology when an FAB end goes out of a factory and enters PKG packaging, and therefore when the PKG packaging of the packaged chip is ground and thinned, the wafer is easy to crack due to grinding, the internal stress of the wafer is increased, the wafer is easy to break in the subsequent process, and the product yield is reduced.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which can reduce fragments caused in the packaging process of the semiconductor device and improve the yield of products.
The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a packaged chip, wherein a positioning groove is formed in the edge of the packaged chip, and the bottom wall forming the positioning groove has a first thickness; trimming the positioning groove of the packaged chip to enable the bottom wall of the positioning groove to have a second thickness, wherein the second thickness is smaller than the first thickness; providing a packaging substrate, forming a glue layer on the packaging substrate, and arranging the packaging chip on the glue layer and gluing the packaging chip with the glue layer; and trimming and grinding the packaged chip to remove the bottom wall of the positioning groove.
Therefore, according to the preparation method of the semiconductor device, the damage to the internal circuit of the packaged chip caused by the fracture of the bottom wall of the positioning groove can be avoided, the damage to the semiconductor device caused by the fracture of the edge part of the packaged chip forming the positioning groove is reduced, and the yield of the semiconductor device can be improved.
According to some embodiments of the invention, the second thickness is 387 μm to 750 μm.
According to some embodiments of the invention, the packaged chip includes a first wafer and a second wafer, the first wafer and the second wafer are bonded to form the packaged chip, and a lower surface of the first wafer is attached to an upper surface of the second wafer.
According to some embodiments of the invention, the notch extends through the first wafer and is formed partially on the second wafer, the second thickness T1 of the bottom wall of the notch and the thickness T2 of the second wafer being such that: 2T2 is less than or equal to T1.
According to some embodiments of the invention, the width of the positioning groove in the radial direction of the packaged chip is 1mm to 3 mm.
According to some embodiments of the invention, the positioning groove extends along a circumference of the packaged chip.
According to some embodiments of the invention, the glue layer is made of an epoxy material.
The invention also provides a preparation method of the semiconductor device.
The preparation method according to the embodiment of the invention comprises the following steps: providing a packaged chip, wherein a positioning groove is formed at the edge of the packaged chip; trimming the packaged chip to remove a bottom wall edge portion of the packaged chip forming the positioning groove; providing a packaging substrate, forming a glue layer on the packaging substrate, and arranging the packaging chip on the glue layer and gluing the packaging chip with the glue layer; and grinding and thinning the packaged chip.
According to some embodiments of the invention, the packaged chip includes a first wafer and a second wafer, the first wafer and the second wafer are bonded to form the packaged chip, and a lower surface of the first wafer is attached to an upper surface of the second wafer.
Optionally, after the upper surface of the first wafer is attached to the adhesive layer, the lower surface of the second wafer is ground and thinned.
According to some embodiments of the invention, the notch extends through the first wafer and is formed partially on the second wafer, the second thickness T2 of the bottom wall of the notch and the thickness T1 of the second wafer being such that: 2T2 is less than or equal to T1.
According to some embodiments of the invention, the width of the positioning groove in the radial direction of the packaged chip is 1mm to 3 mm.
According to some embodiments of the invention, the positioning groove extends along a circumference of the packaged chip.
According to some embodiments of the invention, the glue layer is made of an epoxy material.
The present invention also proposes a semiconductor device comprising: the packaging chip comprises a first wafer and a second wafer which are arranged in a stacking and bonding mode, the lower surface of the first wafer is attached to the upper surface of the second wafer, and the outer edge of the second wafer is flush with the outer edge of the first wafer; the packaging substrate is formed with a glue layer, the packaging chip is arranged on the glue layer, the upper surface of the first wafer is glued with the glue layer, and the radial size of the packaging chip is smaller than that of the packaging substrate.
According to some embodiments of the invention, the glue layer is formed on the bottom and the side of the packaged chip, and the glue layer is located on the side of the packaged chip and formed around the circumference of the first wafer.
Drawings
Fig. 1 is a sectional view of one manufacturing process of a manufacturing method of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of another manufacturing process of a manufacturing method of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a flow chart of a method of fabricating a semiconductor device according to one embodiment of the present invention;
fig. 4 is a flow chart of a method of fabricating a semiconductor device according to another embodiment of the present invention;
fig. 5 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Reference numerals:
100: a semiconductor device;
1: packaged chip, 11: first wafer, 12: second wafer, 121: bottom wall of positioning groove, 13: positioning a groove;
2: package substrate, 21: and (6) a glue layer.
Detailed Description
The semiconductor device and the method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings and the detailed description.
A method of manufacturing the semiconductor device 100 according to one embodiment of the present invention is described below with reference to the drawings.
As shown in fig. 3, the method of manufacturing the semiconductor device 100 according to the embodiment of the present invention includes:
providing a packaged chip 1, wherein a positioning groove 13 is formed at the edge of the packaged chip 1, and a bottom wall 121 forming the positioning groove 13 has a first thickness;
trimming the positioning groove 13 of the packaged chip 1 so that the bottom wall 121 of the positioning groove 13 has a second thickness, the second thickness being smaller than the first thickness;
providing a packaging substrate 2, forming a glue layer 21 on the packaging substrate 2, and arranging the packaging chip 1 on the glue layer 21 and gluing the packaging chip with the glue layer 21;
the packaged chip 1 is trimmed and ground to remove the bottom wall 121 of the positioning groove 13.
The above steps will be described with reference to fig. 1 and 3.
As shown in fig. 3, a packaged chip 1 is provided, and the edge of the packaged chip 1 forms a positioning groove 13, wherein the bottom wall 121 forming the positioning groove 13 has a first thickness.
As shown in fig. 1, a packaged chip 1 includes a first wafer 11 and a second wafer 12, where the first wafer 11 may be a carrier wafer (cell) and the second wafer 12 may be a device wafer (CMOS); specifically, as shown in fig. 1 and 2, the first wafer 11 and the second wafer 12 are stacked and the first wafer 11 is located above the second wafer 12, and the lower surface of the first wafer 11 and the upper surface of the second wafer 12 are tightly bonded through chemical and physical actions to form the packaged chip 1, for example, the first wafer 11 and the second wafer 12 can be bonded through a bonding device through processes of vacuumizing, spacing sheet vacuumizing, heating, pressure applying, temperature reducing, vacuum breaking and the like, so that the purpose of bonding the first wafer 11 and the second wafer 12 is achieved.
The edge of the packaged chip 1 is trimmed to form the positioning groove 13, and the positioning groove 13 is partially formed on the second wafer 12, wherein after the first wafer 11 and the second wafer 12 are bonded, the problem of insufficient bonding property is easily generated at the edge positions of the first wafer 11 and the second wafer 12, so that the bonding strength of the first wafer 11 and the second wafer 12 can be improved by trimming the edge of the packaged chip 1, and the falling risk is reduced. When trimming the edge of the packaged chip 1, the edge of the packaged chip 1 may be trimmed from the first wafer 11 toward the second wafer 12, that is, the edge of the packaged chip 1 is trimmed from top to bottom, wherein the trimming of the edge of the packaged chip 1 extends downward and crosses the bonding surface of the first wafer 11 and the second wafer 12.
Therefore, the bonding performance of the first wafer 11 and the second wafer 12 can be improved, the positioning groove 13 is formed at the edge of the packaged chip 1, the positioning groove 13 can be formed by the side surface of the first wafer 11 and part of the side surface and part of the edge of the second wafer 12, and the positioning groove 13 can be used for positioning a base platform of the packaged chip 1 in the preparation process of the packaged chip 1. Wherein for the trimming process of the edge pair of the packaged chip 1, the edge of the packaged chip 1 can be trimmed by physical mechanical processing.
The seating groove 13 of the packaged chip 1 is trimmed so that the bottom wall 121 of the seating groove 13 has a second thickness, which is smaller than the first thickness, the positioning groove 13 is trimmed again to increase the axial depth of the portion of the positioning groove 13 formed in the package chip 1 on the second wafer 12 in the second wafer 12, thereby reducing the thickness of the bottom wall 121 forming the positioning groove 13, wherein, alternatively, the second thickness may be 387 to 750 μm, so that trimming is deepened to the seating groove 13 until the thickness of the bottom wall 121 forming the seating groove 13 is 387 to 750 μm, the bottom wall 121 forming the positioning groove 13 can be trimmed to 387 to 750 μm, for example, the second thickness may be 400 μm to 600 μm, further, the second thickness may be 400 μm, 500 μm, 600 μm, 650 μm, or the like, the specific width of the bottom wall 121 of the positioning groove 13 can be set according to the grinding and thinning requirements of the packaged chip.
Providing a package substrate 2, forming a glue layer 21 on the package substrate 2, and arranging a package chip 1 on the glue layer 21 and gluing the package chip to the glue layer 21, as shown in fig. 1, the upper surface of the first wafer 11 can be attached to the glue layer 21, so that in the package process of the package chip 1, providing the package substrate 1 and coating glue on the package substrate 1 to form the glue layer 21, turning over the package chip 1, and realizing package connection with the package substrate 2 by gluing the first wafer 11 to the glue layer 21, at this time, the lower surface of the second wafer 12 is located above the first wafer 11 and the package substrate 2.
In the packaging process of the semiconductor device 100, the lower surface of the second wafer 12 needs to be polished to etch the second wafer 12 to a desired thickness, and the lower surface of the second wafer 12 is pressed, so that the edge portion of the second wafer 12 where the positioning groove 13 is formed is easily broken, and cracks are generated inside the second wafer 12. By deepening the axial depth of the positioning groove 13, the thickness of the bottom wall 121 of the positioning groove 13 is thinned, so that the damage to the internal circuit of the second wafer 12 caused by the fracture of the edge part of the second wafer 12 can be avoided in the packaging process of the semiconductor device 100, the damage to the semiconductor device 100 caused by the fracture of the edge part of the second wafer 12 is reduced, and the yield of the semiconductor device 100 can be improved.
In some embodiments of the present invention, the positioning groove 13 penetrates through the first wafer 11 and is partially formed on the second wafer 12, wherein the thickness T2 of the bottom wall 121 of the positioning groove 13 and the thickness T1 of the second wafer 12 satisfy 2T2 ≦ T1, that is, the thickness of the edge portion 121 of the second wafer 12 forming the positioning groove 13 may be less than or equal to half the thickness of the second wafer 12, so that after the first wafer 11 is glued with the glue layer 21, the lower surface of the second wafer 12 is ground to remove the edge portion 121 of the second wafer 12 forming the positioning groove 13.
Specifically, when the edge of the packaged chip 1 is trimmed, the trimming depth of the packaged chip 1 may be increased, or the positioning groove 13 may be trimmed twice, so that the portion of the positioning groove 13 formed in the packaged chip 1 on the second wafer 12 is increased in the axial direction of the second wafer 12, that is, the thickness of the remaining edge portion 121 of the second wafer 12 is reduced, thereby making the thickness of the remaining edge portion 121 of the second wafer 12 smaller, where the thickness of the edge portion 121 of the second wafer 12 is less than or equal to the thickness of the second wafer 12 that is required to be ground.
Therefore, in the process of packaging the packaged chip 1, when the second wafer 12 is ground and thinned, the remaining edge portion 121 of the second wafer 12 can be easily ground away in the grinding process due to the thinness of the remaining edge portion 121 of the second wafer 12, so that stress damage to the inside of the second wafer 12 caused by fracture of the packaged chip 1 can be avoided, and when the edge portion 121 of the second wafer 12 is fractured, the stress generated by fracture is small, the influence on the circuit inside the second wafer 12 is small, and the influence on the circuit inside the second wafer 12 can be reduced.
Referring to fig. 2 and 4, the present invention also provides a method for manufacturing a semiconductor device.
As shown in fig. 4, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:
providing a packaged chip 1, wherein a positioning groove 13 is formed at the edge of the packaged chip 1;
trimming the packaged chip 1 to remove the bottom wall edge portion 121 of the packaged chip 1 forming the positioning groove 13;
providing a packaging substrate 2, forming a glue layer 21 on the packaging substrate 2, and arranging the packaging chip 1 on the glue layer 21 and gluing the packaging chip with the glue layer 21;
the packaged chip 1 is ground and thinned.
The above steps will be described with reference to fig. 2 and 4.
As shown in fig. 4, a packaged chip 1 is provided, and a positioning groove 13 is formed at the edge of the packaged chip 1;
as shown in fig. 2, the packaged chip 1 includes a first wafer 11 and a second wafer 12, wherein the first wafer 11 may be a carrier wafer (cell), and the second wafer 12 may be a device wafer (CMOS); specifically, as shown in fig. 1 and 2, the first wafer 11 and the second wafer 12 are stacked and the first wafer 11 is located above the second wafer 12, and the lower surface of the first wafer 11 and the upper surface of the second wafer 12 are tightly bonded through chemical and physical actions to form the packaged chip 1, for example, the first wafer 11 and the second wafer 12 can be bonded through a bonding device through processes of vacuumizing, spacing sheet vacuumizing, heating, pressure applying, temperature reducing, vacuum breaking and the like, so that the purpose of bonding the first wafer 11 and the second wafer 12 is achieved.
The edge of the packaged chip 1 is trimmed to form the positioning groove 13, and the positioning groove 13 is partially formed on the second wafer 12, wherein after the first wafer 11 and the second wafer 12 are bonded, the problem of insufficient bonding property is easily generated at the edge positions of the first wafer 11 and the second wafer 12, so that the bonding strength of the first wafer 11 and the second wafer 12 can be improved by trimming the edge of the packaged chip 1, and the falling risk is reduced. When trimming the edge of the packaged chip 1, the edge of the packaged chip 1 may be trimmed from the first wafer 11 toward the second wafer 12, that is, the edge of the packaged chip 1 is trimmed from top to bottom, wherein the trimming of the edge of the packaged chip 1 extends downward and crosses the bonding surface of the first wafer 11 and the second wafer 12.
Therefore, the bonding performance of the first wafer 11 and the second wafer 12 can be improved, the positioning groove 13 is formed at the edge of the packaged chip 1, the positioning groove 13 can be formed by the side surface of the first wafer 11 and part of the side surface and part of the edge of the second wafer 12, and the positioning groove 13 can be used for positioning a base platform of the packaged chip 1 in the preparation process of the packaged chip 1. Wherein for the trimming process of the edge pair of the packaged chip 1, the edge of the packaged chip 1 can be trimmed by physical mechanical processing.
Trimming the packaged chip 1 to remove the bottom wall edge portion 121 of the packaged chip 1 forming the positioning groove 13; specifically, the packaged chip 1 may be trimmed before the packaged chip 1 is packaged, so as to remove the bottom wall edge portion 121 forming the positioning groove 13, and further remove the positioning groove 13 formed at the edge of the packaged chip 1, so that the edge of the packaged chip 1 is axially flush, i.e., the edges of the first wafer 11 and the second wafer 12 are flush.
Providing a packaging substrate 2, forming a glue layer 21 on the packaging substrate 2, and arranging the packaging chip 1 on the glue layer 21 and gluing the packaging chip with the glue layer 21; the packaged chip 1 is ground and thinned. Because the edges of the packaged chip 1 are flush with each other, when the packaged chip 1 is packaged, the damage of the internal circuit of the second wafer 12 caused by edge cracking stress when the packaged chip 1 is ground and thinned can be avoided, the internal stress generated by the semiconductor device in the subsequent process can be reduced, and the possibility of the breaking phenomenon is reduced.
Therefore, according to the method for manufacturing the semiconductor device 100 of the embodiment of the invention, before the packaged chip 1 is packaged, the bottom wall edge part 12 of the positioning groove 13 of the packaged chip 1 can be removed, so that the edge of the packaged chip 1 can be prevented from being broken when the package is ground and thinned, the internal circuit of the packaged chip 1 can be prevented from being damaged due to the internal stress generated by the breakage, and the possibility of the chip breaking phenomenon caused in the process can be reduced.
Alternatively, when the edge portion of the bottom wall of the positioning groove 13 is removed, the edge portion 121 of the positioning groove 13 formed on the second wafer 12 may be removed by physical mechanical process, which may be physically removed by using a rotating device. Specifically, for example, the packaged chip 1 may be subjected to center rotation, and the edge of the packaged chip 1 may be subjected to grinding trimming using a rotating blade or other shearing device to remove the edge portion 121 of the second wafer 12 forming the positioning groove 13.
In some embodiments of the present invention, the width of the positioning groove 13 in the radial direction of the package chip 1 is 1mm to 3mm, that is, the width of the positioning groove 13 in the radial direction of the package chip 1 is greater than or equal to 1mm and less than or equal to 3mm, for example, the width of the positioning groove 13 in the radial direction of the package chip 1 may be 1mm, 2mm or 3mm, as shown in fig. 1 and 2, the first wafer 11 and the second wafer 12 are stacked, the radial dimension of the second wafer 12 and the first wafer 11 is the radial dimension of the package chip 1, the width of the positioning groove 13 in the radial direction of the package chip 1 is the width of the edge portion 121 of the positioning groove 13 formed by the second wafer 12, the width of the edge portion 121 of the second edge 12 formed by the positioning groove 13 is greater than or equal to 1mm and less than or equal to 3mm, so that the influence of the edge portion 121 of the second wafer 12 on the fracture center area due to the excessive width of the edge portion, it is also avoided that the positioning groove 13 has a smaller width to affect the adhesion between the glue layer 21 and the first wafer 11.
As shown in fig. 1 and fig. 2, the positioning groove 13 extends a circle along the circumference of the packaged chip 1, that is, the positioning groove 13 extends along the circumference of the packaged chip 1 and surrounds the circumference of the packaged chip 1, so that the positioning of the packaged chip 1 is facilitated, the adhesive layer 21 on the side portion can surround the packaged chip 1 to form a circle, and the protection of the packaged chip 1 is improved.
The adhesive layer 21 may be made of an epoxy resin material, which has good moldability, high heat resistance, good mechanical strength and electrical insulation, a small thermal expansion coefficient, low water vapor permeability, low cost, and excellent electrical and adhesive properties, and can prevent the packaged chip 1 from deteriorating.
A semiconductor device 100 according to an embodiment of the present invention is described below with reference to the drawings.
As shown in fig. 1 to 2 and fig. 5, a semiconductor device 100 according to an embodiment of the present invention may include a packaged chip 1, a package substrate 2, and a glue layer 21 provided on the package substrate 2.
The packaged chip 1 includes a first wafer 11 and a second wafer 12 which are stacked and bonded, a lower surface of the first wafer 11 is bonded to an upper surface of the second wafer 12, and the second wafer 12 is flush with an outer edge of the first wafer 11, that is, the packaged chip 1 includes the first wafer 11 and the second wafer 12, the first wafer 11 and the second wafer 12 are stacked, centers of the first wafer 11 and the second wafer 12 are aligned and an outer edge of the first wafer is flush, wherein the first wafer 11 and the second wafer 12 are bonded through physical and chemical bonding, optionally, the first wafer may be a carrier wafer (cell), and the second wafer 12 is a device wafer (CMOS).
A glue layer 21 is formed on the package substrate 2, the package chip 1 is disposed on the glue layer 21, the upper surface of the first wafer 11 is glued with the glue layer 21, specifically, glue is coated on the package substrate 2 to form the glue layer 21, the package chip 1 and the package substrate 2 are glued through the glue layer 21, as shown in fig. 5, the upper surface of the first wafer 11 is glued with the glue layer 21, wherein the radial size of the package chip is smaller than the radial size of the package substrate, that is, the diameter size of the package chip 1 is smaller than the diameter size of the package substrate 2, as shown in fig. 5, the outer edge of the package substrate 2 exceeds the outer edge of the package chip 1, so that when the package chip 1 is glued with the glue layer 21, the glue layer 21 is formed on the bottom and the side of the package chip 1, and the glue layer 21 on the side of the package chip 1 is formed around the circumference of the second wafer.
Specifically, after the first wafer 11 and the second wafer 12 are bonded, in order to prevent the peeling, the edge of the packaged chip 1 is trimmed, so that the bonding strength between the first wafer 11 and the second wafer 12 can be improved, wherein the edge of the packaged chip 1 can be trimmed to form the positioning groove 13, so that the positioning groove can play a role in positioning a base table in the preparation process of the packaged chip.
When the packaged chip 1 is trimmed, the positioning groove 13 is partially formed on the second wafer 12, and the positioning groove 12 can be trimmed for a second time at the edge portion 121 of the second wafer 12 to deepen, so that the thickness of the edge portion 121 of the second wafer 12 where the positioning groove 13 is formed is smaller than or equal to the thickness of the second wafer 12 to be trimmed in the packaging process, and thus, the edge portion 121 of the second wafer 12 can be ground when the second wafer 12 is ground and thinned, and the outer edge of the second wafer 12 is flush with the outer edge of the first wafer 11, so that the chipping phenomenon generated in the subsequent process can be reduced, and the product yield is improved.
Or before the packaged chip 1 is packaged, the edge portion 121 of the second wafer 12 is removed by physical processing, for example, the edge of the packaged chip 1 may be ground and cut by a rotating blade or other cutting equipment, so that the outer edge of the second wafer 12 is flush with the outer edge of the first wafer 11, and then the packaged chip 1 is glued with a glue layer, so that when the second wafer 12 is ground and thinned, the fracture of the edge portion 121 of the second wafer 12 due to the pressure applied to the second wafer 12 can be avoided, the crack of the semiconductor device 100 caused by the force transmitted to the inside of the second wafer 12 due to the stress applied to the edge portion of the second wafer 12 can also be avoided, and the chipping phenomenon caused by the subsequent process can also be reduced.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (15)
1. A method of manufacturing a semiconductor device, comprising:
providing a packaged chip, wherein a positioning groove is formed in the edge of the packaged chip, and the bottom wall forming the positioning groove has a first thickness;
trimming the positioning groove of the packaged chip so that the bottom wall of the positioning groove has a second thickness, wherein the second thickness is smaller than the first thickness;
providing a packaging substrate, forming a glue layer on the packaging substrate, and arranging the packaging chip on the glue layer and gluing the packaging chip with the glue layer;
and trimming and grinding the packaged chip to remove the bottom wall of the positioning groove.
2. The method according to claim 1, wherein the second thickness is 387 μm to 750 μm.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the packaged chip comprises a first wafer and a second wafer, the first wafer and the second wafer are bonded to form the packaged chip, and a lower surface of the first wafer is attached to an upper surface of the second wafer.
4. The method of claim 1, wherein the positioning groove penetrates through the first wafer and is partially formed on the second wafer, and the second thickness T2 of the bottom wall of the positioning groove and the thickness T1 of the second wafer satisfy: 2T2 is less than or equal to T1.
5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the width of the positioning groove in the radial direction of the packaged chip is 1mm to 3 mm.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the positioning groove extends along a circumference of the packaged chip.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the adhesive layer is made of an epoxy resin material.
8. A method of manufacturing a semiconductor device, comprising:
providing a packaged chip, wherein a positioning groove is formed at the edge of the packaged chip;
trimming the packaged chip to remove a bottom wall edge portion of the packaged chip forming the positioning groove;
providing a packaging substrate, forming a glue layer on the packaging substrate, and arranging the packaging chip on the glue layer and gluing the packaging chip with the glue layer;
and grinding and thinning the packaged chip.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the packaged chip comprises a first wafer and a second wafer, the first wafer and the second wafer are bonded to form the packaged chip, and a lower surface of the first wafer is attached to an upper surface of the second wafer.
10. The method of claim 9, wherein the lower surface of the second wafer is thinned by grinding after the upper surface of the first wafer is bonded to the adhesive layer.
11. The manufacturing method of a semiconductor device according to any one of claims 8 to 10, wherein the width of the positioning groove in the radial direction of the packaged chip is 1mm to 3 mm.
12. The method of manufacturing a semiconductor device according to claim 8, wherein the positioning groove extends along a circumference of the packaged chip.
13. The method for manufacturing a semiconductor device according to claim 8, wherein the adhesive layer is made of an epoxy resin material.
14. A semiconductor device, comprising:
the packaging chip comprises a first wafer and a second wafer which are arranged in a stacking and bonding mode, the lower surface of the first wafer is attached to the upper surface of the second wafer, and the outer edge of the second wafer is flush with the outer edge of the first wafer;
the packaging substrate is formed with a glue layer, the packaging chip is arranged on the glue layer, the upper surface of the first wafer is glued with the glue layer, and the radial size of the packaging chip is smaller than that of the packaging substrate.
15. The semiconductor device according to claim 14, wherein the adhesive layer is formed on a bottom surface and a side surface of the packaged chip, and the adhesive layer on the side surface of the packaged chip is formed around a circumference of the first wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010312290.9A CN111463138B (en) | 2020-04-20 | 2020-04-20 | Semiconductor device and method for manufacturing the same |
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| CN111627845A (en) * | 2020-07-30 | 2020-09-04 | 中芯集成电路制造(绍兴)有限公司 | Bonding disassembling device and bonding disassembling method thereof |
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