JP4008931B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor element packaging technique, and more particularly to a semiconductor device in which a semiconductor element is packaged by resin sealing and a manufacturing method thereof.

  In recent years, a low dielectric layer having a relative dielectric constant of 3 or less has been used as a multilayer wiring interlayer insulator of a semiconductor element in order to reduce signal delay due to inter-wiring parasitic capacitance in the semiconductor element and leakage current of the element. Further, in order to realize a lower relative dielectric constant of 2 or less, fine pores of about 0.1 to 100 nm are formed inside the dielectric layer to form a porous insulator of air having a small relative dielectric constant. Such a low dielectric film is very fragile because the strength of the material itself is low and at the same time contains fine air.

  On the other hand, the semiconductor element is mechanically cut from the wafer with a grindstone and sealed with an epoxy or silicone resin to form a semiconductor package. At this time, since the end portion of the semiconductor element is cut with a grindstone, the end portion of the element has a shape that stands up at approximately 90 degrees, and the multilayer insulating layer on the element is also exposed. In addition, the sharp side surface of the semiconductor element has a cleavage shape in which pure silicon crystal orientations are aligned, and the adhesion strength with the sealing resin is low.

  When a semiconductor package is formed, stress is generated on the front surface, side surface, and back surface of the semiconductor element due to differences in thermal expansion coefficients of the sealing resin, the substrate, and the semiconductor element. In a semiconductor package as a structure, a higher stress is applied as the distance from the center to the periphery is increased, and particularly, a high stress is generated around the semiconductor element such as a peripheral edge or a side surface of the semiconductor element. Due to the stress, there is a problem that peeling occurs inside the low dielectric film or at the interface of the multilayer wiring layer inside the multilayer wiring film on the surface of the semiconductor element incorporating the low dielectric film. The surface of the semiconductor element has a greater thermal stress toward the end of the element, and when the end of the multilayer insulating film is peeled off even slightly, delamination progresses from this point.

Also, since the side surface of the semiconductor element and the vicinity where the semiconductor element is cut cannot obtain high adhesive strength with the sealing resin as described above, the sealing resin on the side surface of the semiconductor element with high thermal stress is easily peeled off, The stress on the representative surface including the multilayer wiring near the peripheral edge of the semiconductor element described above becomes extremely large, and there is a problem that the peeling of the fragile low dielectric layer is accelerated.
JP 2003-197564 A

  As described above, when a semiconductor element having a fragile low dielectric constant interlayer insulating film is sealed with a resin and a semiconductor package is formed, the low dielectric constant interlayer insulating film is peeled off by stress applied to the periphery of the semiconductor element. As a result, the reliability of the device is lowered.

  The present invention has been made in consideration of the above-mentioned circumstances, and the object of the present invention is to apply stress applied to the periphery of the element in a structure in which a semiconductor element having a fragile low dielectric constant interlayer insulating film is sealed with resin. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same that can prevent interlayer separation caused by the above-described problem and can improve element reliability.

  In order to solve the above problems, the present invention adopts the following configuration.

That is, according to one embodiment of the present invention, in a semiconductor device in which a semiconductor element is packaged by resin sealing, a plurality of layers including a low dielectric constant interlayer insulating film having a relative dielectric constant of 2 or less on a surface of a semiconductor substrate. A laminated film is formed, the laminated film is removed along a peripheral edge of the substrate at a certain distance from the peripheral edge, and the substrate is removed from the substrate surface to a predetermined depth. And a mounting substrate on which the semiconductor element is mounted, and a resin layer for resin-sealing at least the surface side of the semiconductor element.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device in which a semiconductor element is packaged by sealing a semiconductor element, and a low dielectric constant interlayer insulating film having a relative dielectric constant of 2 or less is formed on a surface of a semiconductor substrate. A depth at which the substrate surface is exposed at a part of the inner side of the semiconductor element formed with a plurality of layers including a plurality of layers along the peripheral edge of the substrate at a predetermined distance from the peripheral edge. Further, the step of removing the substrate from the substrate surface to a predetermined depth by RIE or a laser beam, the step of mounting the semiconductor element on a mount substrate, and at least the surface side of the semiconductor element are resin-sealed with a resin material And a process.

  According to the present invention, by removing the laminated film in the peripheral part of the semiconductor element and exposing the substrate surface in the peripheral part of the element, the peripheral part of the element can be made of a semiconductor such as silicon or an oxide film thereof. The adhesive strength with the resin can be dramatically increased. Therefore, when the surface side of the semiconductor element is sealed with resin, even if stress is generated in the peripheral portion of the element surface, the resin does not peel off, and the internal insulating layer can be prevented from peeling off. For this reason, the reliability of the semiconductor element can be improved.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device according to the first embodiment of the present invention.

  A semiconductor chip (semiconductor element) 12 is mounted on the mount substrate 11 with an adhesive 13, and electrode pads (not shown) of the semiconductor element 12 are connected to wiring (not shown) on the mount substrate 11 via bonding wires 14. It is connected. Solder balls 15 are provided on the lower surface of the mount substrate 11. The semiconductor element 12 is sealed with an epoxy or silicone resin 16.

  The packaged structure described above, that is, the basic structure of the P-BGA package is the same as the conventional one, but in this embodiment, the structure of the peripheral portion of the semiconductor element 12 is different from the conventional one as described below.

  FIG. 2 is an enlarged cross-sectional view showing the peripheral structure of the semiconductor element 12 used in this embodiment. In FIG. 2, the adhesive 13 and the solder balls 15 are omitted for the sake of simplicity.

  The semiconductor element 12 is configured by laminating various interlayer insulating films 22 on a semiconductor substrate 21 and forming wiring layers 23 between the insulating films 22. Here, at least one layer of the insulating film 22 includes a low dielectric film having a relative dielectric constant of 2 or less.

  The semiconductor element 12 is formed with a laminated film 24 (22, 23) in a wafer state, and finally separated into a plurality of chips by dicing. In this embodiment, before or after dicing for cutting out a semiconductor element from a wafer, a laminated film 24 including a low dielectric layer, which is an insulating film formed on the surface around the dicing line, is formed by, for example, RIE (Reactive Ion Etching), It is removed using non-contact high energy processing such as FIB (Focus Ion Beam Etching) or laser beam to expose the underlying silicon surface. Reference numeral 25 in FIG. 2 denotes a removed portion of the laminated film 24.

  With such a structure, the end portion of the semiconductor element 12 is stepped, and an exposed surface of the substrate silicon can be formed at the element end portion. This silicon surface has extremely high adhesion to the epoxy-based or silicone-based sealing resin 16, and the resin 16 does not easily peel off from the silicon. At the same time, a region without a fragile low dielectric layer serving as a starting point of peeling can be secured, and the stress applied to the laminated film 24 around the semiconductor element is borne by the sealing resin 16 adhered to the silicon surface. The stress at the fragile laminated film edge can be reduced by the distance moved into the element.

By taking a wide width from the peripheral edge of the semiconductor element as a region for removing the laminated film 24, the peeling stress applied to the low dielectric layer can be further reduced. The wider the width for removing the laminated film 24, the more effective. However, the wafer yield decreases as the width is increased. Therefore, when the laminated film 24 is removed, the laminated film 24 at the end portion where the thermal stress is high is removed. It is effective. According to the experiments by the present inventors, the range from the peripheral edge of the semiconductor element to the inner side of 300 μm was effective. More preferably, an example in which a conventional element is packaged is shown in FIG. 3 for comparison, which was in the range of 5 to 10 μm inward from the peripheral edge of the semiconductor element. The peripheral portion of the semiconductor element 12 is cut vertically, and the side other than the side surface of the silicon substrate 21 is not exposed, the contact area between the substrate silicon and the resin layer 16 is small, and strong adhesion strength cannot be obtained. .

  FIG. 4 is a diagram for explaining the prior art of FIG. 3, in which the maximum principal stress applied to the laminated film is plotted by the distance from the peripheral edge of the semiconductor element, and FIG. 5 is a diagram of FIG. FIG. 2 is a diagram for explaining the first embodiment, and plots and shows the maximum principal stress applied to a laminated film by the distance from the peripheral edge of the semiconductor element. In the conventional structure shown in FIG. 3, as shown in FIG. 4, the stress becomes extremely large in the vicinity of the peripheral edge portion of the semiconductor element, and this causes peeling of the film. On the other hand, in the structure of this embodiment shown in FIG. 1, the stress applied to the laminated film becomes extremely small as shown in FIG. 5 by removing the laminated film in the peripheral portion including the peripheral edge portion of the semiconductor element. . Also from this, it can be understood that film peeling at the end of the laminated film is eliminated by the present embodiment, and device reliability can be improved.

  Here, when RIE is used to remove the laminated film 24 on the semiconductor element 12, both the wall surface and the silicon portion including the laminated film 24 can be finished with a surface roughness of Rmax = 1 μm or less. Furthermore, no so-called film sag occurred at the end of the laminated film 24. On the other hand, in the conventional blade processing using a grindstone, the wall surface including the laminated film 24 has a surface roughness of Rmax = 10 to 100 μm, and the silicon portion has a surface roughness of Rmax = 5 μm. Film dripping occurred.

  This also confirms the usefulness in RIE. That is, the above-described effect according to the present embodiment is obtained by removing the laminated film by RIE. When the laminated film 24 is removed from the peripheral edge portion of the semiconductor element by blade processing, the above effect is obtained. It cannot be obtained. Also, in FIB, the same effect as RIE can be expected. Further, the fact that the surface roughness is small leads to an effect that the yield of the device can be increased without wasting the area of the device as a damage margin corresponding to the roughness.

  Further, for example, by using a carbon dioxide laser or a YAG laser to remove the laminated film 24 on the semiconductor element 12, the substrate silicon is exposed and the silicon surface is oxidized at the same time to oxidize the peripheral portion of the element to a thickness of 1 μm or less. A silicon film can be formed. Sealing resin mainly composed of epoxy, for example, sealing with injection mold, liquid epoxy, or silicone resin improves adhesion strength because the adherend is a silicon oxide film. That is, by processing with a laser and forming a silicon oxide film on the exposed surface of the substrate 21, the adhesion with the resin 16 can be further enhanced.

  Furthermore, by using a laser for processing the laminated film 24, fine irregularities that cannot be obtained by normal mechanical polishing can be formed on the substrate surface, and the peripheral portion of the semiconductor element 12 to be adhered can be sealed. The adhesion strength with the stop resin 16 is further improved. By increasing the adhesion strength between the peripheral portion of the element and the sealing resin, the peeling stress of the fragile film can be reduced. Such an effect can more reliably prevent fragile low dielectric multilayer film from peeling inside the package.

  Note that the shear adhesion strength between the machined silicon and the sealing resin is an average of 32 MPa, and the peeling interface is an interface between the silicon and the resin. On the other hand, when the silicon oxide film and resin produced when laser processing is performed on the silicon surface, peeling does not occur at the interface between the silicon oxide film and the resin, and bulk silicon is destroyed. Will do. That is, the adhesion strength between the silicon oxide film and the resin reaches an unmeasurable adhesion strength of bulk silicon breakdown strength of 37 MPa or more.

  As described above, according to the present embodiment, with respect to the semiconductor element 12 in which the laminated film 24 including a plurality of layers including the insulating film is formed on the surface of the Si substrate 21, the laminated film 24 is formed in the peripheral portion of the substrate by RIE, By removing it with FIB or laser, the substrate silicon can be exposed at the periphery of the element. For this reason, when the surface side of the element is resin-sealed, the adhesiveness between the resin 16 and the substrate silicon is high, so that the adhesiveness of the resin 16 can be enhanced at the periphery of the element. Therefore, for example, in the semiconductor element 12 having a fragile low dielectric constant interlayer insulating film, interlayer isolation due to stress applied to the periphery of the element can be prevented, and reliability can be improved.

  In particular, by removing the laminated film 24 around the element by laser processing using a YAG laser or a carbon dioxide gas laser, an Si oxide film can be formed on the exposed substrate silicon surface, thereby improving the adhesion to the resin. It can be further increased, and the reliability can be further improved.

(Second Embodiment)
FIG. 7 is an enlarged cross-sectional view showing the peripheral structure of the semiconductor element used in the second embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The difference between the present embodiment and the first embodiment described above is not the peripheral portion including the peripheral end portion of the semiconductor element 12, but along the peripheral end portion inside a certain distance from the peripheral end portion of the element. The groove 25 is formed so as to expose the substrate silicon.

  As the processing means for the groove 25, the RIE, FIB, or laser beam described above may be used. The position where the groove 25 is formed is centered on the inside of the semiconductor element, for example, 10 to 300 μm, and the width of the groove may be 5 to 295 μm, for example.

  In this way, by digging the groove 25 inside a certain distance from the peripheral edge of the semiconductor element, the end of the laminated film that becomes the starting point of the separation is separated from the high stress range of the peripheral edge of the element, and at the same time in the groove 25 As described above, the resin 16 has high adhesion strength, and the resin 16 relieves stress at the end of the laminated film. As shown in FIG. 6, the stress applied to the laminated film 24 in the present embodiment is formed by forming a groove 25 on the inner side at a certain distance from the element peripheral end portion, although a point having a large stress remains at the element peripheral end portion. The stress can be made extremely small inside the groove 25.

  Therefore, also in the present embodiment, interlayer isolation due to stress applied to the peripheral portion of the semiconductor element 12 can be prevented, and the same effect as in the first embodiment can be obtained. Further, it is the same as in the first embodiment that a further effect can be obtained by using a laser for processing the groove 25.

(Third embodiment)
FIG. 8 shows a cross section when the peripheral structure of the semiconductor element is processed using a laser according to the third embodiment of the present invention.

  In this embodiment, the case where the groove is formed by removing the silicon film from the laminated film 24 including the low dielectric film on the peripheral portion including the peripheral edge portion of the semiconductor element 12 and exposing the silicon substrate is shown in FIG. As described above, not only the removal of the laminated film 24 including the low dielectric film, but also the silicon substrate is removed deeply by 1 μm or more from the surface, and the exposed surface of the silicon substrate 11 is formed deeply by 1 μm or more from the surface. As described above, when the exposed bottom surface of the silicon substrate 11 is deepened by 1 μm or more from the surface, the sealing resin is in close contact with not only the exposed bottom surface of the silicon substrate 11 but also the exposed side surface of the silicon substrate 11. Since the effective exposed-side area between the resin and the silicon substrate 11 is increased, the adhesion strength with the sealing resin is improved, and the peeling of the low dielectric film and the peeling of the laminated film 24 including the low dielectric film are prevented. Further, the roughness of the exposed bottom surface of the silicon substrate 11, that is, the depth of the unevenness of the exposed bottom surface of the silicon substrate 11, is formed to be 3 μm or more deep. In this way, by forming an unevenness having a depth of 3 μm or more on the exposed bottom surface of the silicon substrate 11, an amount sufficient for the sealing resin to have a close contact effect enters the recess, and thereby the close contact between the silicon substrate 11 and the sealing resin. The strength is improved, and the peeling of the low dielectric film and the peeling of the laminated film 24 including the low dielectric film are prevented. For these treatments using a laser, for example, a third harmonic (355 nm) of a YAG laser can be used. The output conditions such as the laser output value and the number of output pulses of the laser to be used are appropriately set according to the removal target layer. Further, the range of removal of the laminated film 24 including the low dielectric film and the removal of the silicon substrate is limited to the effective use of the semiconductor wafer, that is, the effective use of the semiconductor wafer for cutting out the maximum number of semiconductor chips from one semiconductor wafer. This is determined in consideration of the viewpoint and the viewpoint of the substrate exposure range required to obtain the desired adhesion strength between the semiconductor element and the sealing resin in each semiconductor chip. However, this removal range is at least a range from the peripheral end of the semiconductor element 12 to the inside of 300 μm. Preferably, it is in the range of 5 to 10 μm from the peripheral edge of the semiconductor element 12.

  Further, it is preferable that the laser output when removing the laminated film 24 including the low dielectric film and the silicon substrate on the peripheral side portion of the semiconductor chip and the laser output when removing the silicon substrate are different. That is, since the laminated film 24 including the low dielectric film is not so strong in mechanical strength, it is removed by a low output laser, for example, a laser having an output of 1 W or less, and the exposed surface of the laminated film 24 including the low dielectric film is received. Minimize damage. On the other hand, since the silicon substrate has high mechanical strength, even if it is removed by a laser having a high output energy, for example, a laser having an output of 1 W or more, the damage is small, but the silicon substrate can be removed to a predetermined depth in a short time. As described above, the laser processing efficiency is improved by appropriately changing the output conditions such as the laser output value and the number of output pulses of the laser to be used.

  FIG. 9 is a view showing a cross section of the peripheral structure of the semiconductor element of FIG. 8 after resin sealing. The peripheral structure of the semiconductor element shown in FIG. 9 is the same as the peripheral structure of the semiconductor element shown in FIG. 8 except that the peripheral structure is sealed by the resin 16. Description is omitted.

(Fourth embodiment)
FIG. 10 shows a cross section of another example of processing a peripheral structure of a semiconductor element using a laser according to the fourth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 8 and an identical part, and the detailed description is abbreviate | omitted.

  This embodiment is different from the embodiment of FIG. 8 in that the substrate silicon is exposed along the peripheral end portion not inside the peripheral portion including the peripheral end portion of the semiconductor element 12 but inside a certain distance from the peripheral end portion. Thus, the groove 25 is formed.

  The groove 25 may be formed at a center of, for example, 10 to 300 μm from the peripheral edge of the semiconductor element, and the groove width may be, for example, 5 to 295 μm.

  In this way, by digging the groove 25 inside a certain distance from the peripheral edge of the semiconductor element, the end of the laminated film that becomes the starting point of the separation is separated from the high stress range of the peripheral edge of the element, and at the same time in the groove 25 As described above, the resin 16 has high adhesion strength, and the resin 16 relieves stress at the end of the laminated film. In the present embodiment, the stress applied to the laminated film 24 remains at the inner side of the groove 25 by forming the groove 25 on the inner side at a constant distance from the terminal end of the element, although a point having a large stress remains at the peripheral edge of the element. Can be made extremely small.

  Therefore, also in this embodiment, interlayer separation due to stress applied to the peripheral portion of the semiconductor element 12 can be prevented, and the same effect as that of the embodiment of FIG. 8 can be obtained. Further, the use of a laser for the processing of the groove 25 can provide further effects as in the embodiment of FIG.

  11 is a view showing a cross section of the peripheral structure of the semiconductor element of FIG. 10 after resin sealing. The peripheral structure of the semiconductor element shown in FIG. 11 is the same as the peripheral structure of the semiconductor element shown in FIG. 10 except that the peripheral structure is sealed with resin 16. Description is omitted.

(Fifth embodiment)
FIG. 12 shows a cross section when the peripheral structure of the semiconductor element is processed using a laser according to the fifth embodiment of the present invention.

  When the laser is used to remove the laminated film 24 including the low dielectric film on the peripheral portion including the peripheral edge of the semiconductor element 12 and to remove the silicon substrate to expose the silicon substrate 21, the low dielectric material is irradiated by laser irradiation. The laminated film 24 including the film and the silicon component of the silicon substrate are scattered. If the scattered silicon component adheres to the pattern wiring portion formed on the silicon substrate, a short circuit is generated between the wirings, resulting in a defective element. Therefore, as shown in FIG. 12, in order to prevent the scattered silicon component from adhering to the pattern wiring portion formed on the silicon substrate and causing a short circuit between the wirings, a surface protection film ( An anti-adhesion film) 31 is provided. In the case where the surface protective film is formed using a third harmonic (355 nm) of a YAG laser, its refractive index n is larger than 1.5 when measured with an ellipsometer using a light beam having a wavelength of 365 nm ( n> 1.5) a surface protective film, for example, PVA (polyvinyl alcohol).

  By providing a surface protective film on the laminated film 24 including the low dielectric film, the laminated film 24 including the low dielectric film on the peripheral portion including the peripheral edge portion of the semiconductor element 12 using a laser and the silicon substrate Scattered silicon components generated when removing are adhered to the surface protective film 31, thereby preventing them from adhering to the pattern wiring portion. PVA has high absorption efficiency when irradiated with laser, and therefore has high heat generation efficiency. Therefore, the temperature of the laminated film 24 including the low dielectric film and the silicon substrate is also increased during laser irradiation. It also has an effect of promoting the removal of the laminated film 24 and the silicon substrate. Usually, the surface protective film 31 is processed with a laser to remove the scattered silicon component. For this removal, water washing or solvent washing is usually used.

  Further, as shown in FIG. 12, an insulating film 32 having a refractive index of 1.5 or less, for example, TEOS having a refractive index of 1.49 is formed in the lower layer between the laminated film 24 including the low dielectric film and the surface protective film 31. If an insulating film 33 having a refractive index greater than 1.5, for example, polyimide having a refractive index of 1.5 to 1.8, is formed on the upper layer, processing for forming a groove in the low dielectric film with a laser. Sex is promoted. The reason is that if the refractive index of the upper layer films (surface protective film and insulating film having a refractive index of 1.5 or more) 31, 33 is larger than the refractive index of the lower layer film (insulating film having a refractive index of 1.5 or less) 32, the laser This is because not only the absorption of the upper layer films 31 and 33 with respect to the film can be increased, but also the thermal processing of the laminated film 24 including the low dielectric film can be expected by being heated by the laser. Another reason is that when the upper layer films (surface protective film and insulating film having a refractive index of greater than 1.5) 31 and 33 are processed to form a deletion portion, it works like a lid with the deletion portion opened. Thus, the gas generated during the processing of the lower layer film can be effectively discharged to the outside, and damage to the laminated film due to the pressure can be prevented. An insulating film 33 having a refractive index higher than 1.5, for example, a polyimide having a refractive index of 1.5 to 1.8, formed between the laminated film 24 including the low dielectric film and the surface protective film 31 is used for surface protection. In addition to functioning as a film, as described above, it has the effect of promoting thermal processing of the laminated film 24 including a low dielectric film.

  FIG. 13 is a view showing a cross section of the peripheral structure of the semiconductor element of FIG. 12 after removing the surface protective film and sealing with resin. The peripheral structure of the semiconductor element shown in FIG. 13 is the same as the peripheral structure of the semiconductor element shown in FIG. 12 except that the surface protective film is removed and the resin 16 is sealed. Are given the same numbers and their explanation is omitted.

(Sixth embodiment)
FIG. 14 shows a cross section of another example of processing a peripheral structure of a semiconductor element using a laser according to the sixth embodiment of the present invention. The same parts as those in FIG. 12 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The present embodiment is different from the embodiment of FIG. 12 in that the substrate silicon is exposed along the peripheral end portion not inside the peripheral portion including the peripheral end portion of the semiconductor element 12 but inside a certain distance from the peripheral end portion. Thus, the groove 25 is formed.

  The groove 25 may be formed at a center of, for example, 10 to 300 μm from the peripheral edge of the semiconductor element, and the groove width may be, for example, 5 to 295 μm.

  In this way, by digging the groove 25 inside a certain distance from the peripheral edge of the semiconductor element, the end of the laminated film that becomes the starting point of the separation is separated from the high stress range of the peripheral edge of the element, and at the same time in the groove 25 As described above, the resin 16 has high adhesion strength, and the resin 16 relieves stress at the end of the laminated film. In the present embodiment, the stress applied to the laminated film 24 remains at the inner side of the groove 25 by forming the groove 25 inside a certain distance from the peripheral edge of the element, although a point having a large stress remains at the peripheral edge of the element. The stress can be made extremely small.

  Therefore, also in the present embodiment, interlayer separation due to stress applied to the peripheral portion of the semiconductor element 12 can be prevented, and the same effect as that of the embodiment of FIG. 12 can be obtained. Further, the use of a laser for the processing of the groove 25 can provide further effects as in the embodiment of FIG.

  FIG. 15 is a view showing a cross section of the peripheral structure of the semiconductor element of FIG. 14 after resin sealing. The peripheral structure of the semiconductor element shown in FIG. 15 is the same as the peripheral structure of the semiconductor element shown in FIG. 14 except that the peripheral structure is sealed by the resin 16. Description is omitted.

(Modification)
In addition, this invention is not limited to each embodiment mentioned above. In the embodiment, the example of the P-BGA package has been described. However, the present invention is not limited to this. In the E-BGA package as shown in FIG. 16, the FC-BGA package as shown in FIG. 17, and the T-BGA package as shown in FIG. Can be applied similarly. 16, 17, and 18, the same parts as those in FIG. 1 are denoted by the same reference numerals. Reference numeral 17 denotes a stiffener, and 18 denotes a bump. Other packages can also be applied as long as the surface side or the whole of the semiconductor element is sealed with resin.

  In the embodiment, the edge removal or groove processing of the laminated film is performed over the entire circumference of the semiconductor element. However, it is not always necessary to perform the entire circumference, and the semiconductor element in particular has a high thermal stress applied to the semiconductor element inside the package. It is also effective to apply only to the corners. In this way, in the region where the thermal stress between the sealing resin and the substrate and silicon is high, the laminated film only needs to be removed continuously by at least 500 μm or more along the dicing line.

  Also, the substrate is not necessarily limited to silicon, and GaAs or other semiconductor substrates can be used. Further, the sealing resin is not limited to the epoxy type or the silicone type, and any sealing resin may be used as long as sufficient adhesion to the base semiconductor substrate or its oxide film can be obtained.

  The present invention is not limited to the contents described in the claims, and it is possible to obtain the unique effects as described above by providing the structural features as described below.

  7. The width of the removed portion of the laminated film is 5 to 10 μm.

  In Claim 1, the said part of the said board | substrate is removed deeply 1 micrometer or more from the surface of the said board | substrate.

  In Claim 1, the exposed surface of the said board | substrate has a surface roughness of 3 micrometers or more.

  8. The protective film according to claim 7, wherein the film having a refractive index greater than 1.5 is a protective film for preventing adhesion of scattered semiconductor components generated when the laminated film is removed. In this case, when measured with an ellipsometer between the protective film and the laminated film using a light beam having a wavelength of 365 nm, an insulating film having a refractive index of 1.5 or less is formed in the lower layer, and the refractive index is 1.5. A larger insulating film is formed in the upper layer.

  9. The RIE condition is set so that the exposed surface of the laminated film and the exposed surface of the substrate by removing the laminated film have a surface roughness of 1 μm or less.

  9. The oxide film according to claim 8, wherein an oxide film is formed on the exposed surface of the semiconductor element.

  9. The laser according to claim 8, wherein the laser is applied so as to remove the part of the substrate deeply by 1 μm or more from the surface of the substrate. In this case, the third harmonic of the YAG laser is used as the laser beam.

  The laser beam is applied so that the exposed surface of the substrate has a surface roughness of 3 μm or less. In this case, the third harmonic of the YAG laser is used as the laser beam.

  The width of the removed portion of the laminated film is 1 to 300 μm. In this case, the third harmonic of the YAG laser is used as the laser beam.

  The width of the removed portion of the laminated film is 5 to 10 μm. In this case, the third harmonic of the YAG laser is used as the laser beam.

  The film having a refractive index larger than 1.5 when measured with an ellipsometer using a light beam having a wavelength of 365 nm is provided above the laminated film. In this case, the film having a refractive index greater than 1.5 is a protective film for preventing adhesion of scattered semiconductor components generated when the laminated film is removed. In this case, when measured with an ellipsometer between the protective film and the laminated film using a light beam having a wavelength of 365 nm, an insulating film having a refractive index of 1.5 or less is formed in the lower layer, and the refractive index is 1.5. A larger insulating film is formed on the upper layer.

  In addition, various modifications can be made without departing from the scope of the present invention.

1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to a first embodiment. FIG. 2 is an enlarged cross-sectional view showing a peripheral structure of a semiconductor element used in the semiconductor device of FIG. 1. Sectional drawing which shows schematic structure of the conventional semiconductor element. FIG. 4 is a diagram for explaining the prior art of FIG. 3 and plots the maximum principal stress applied to the laminated film by plotting the distance from the element end. FIG. 2 is a diagram for explaining the first embodiment of FIG. 1 and plotting the maximum principal stress applied to a laminated film by the distance from the peripheral edge of the element. FIG. 8 is a diagram for explaining the second embodiment of FIG. 7 and plots the maximum principal stress applied to the laminated film by plotting the distance from the peripheral edge of the element. Sectional drawing which expands and shows the peripheral part structure of the semiconductor element used for 2nd Embodiment. FIG. 6 is a view showing a cross section when a peripheral structure of a semiconductor element is processed using a laser according to a third embodiment. The figure which shows the cross section of the peripheral part structure of the semiconductor element of FIG. 8 after resin sealing. The figure which shows the cross section at the time of processing the peripheral part structure of a semiconductor element based on 4th Embodiment using the laser. The figure which shows the cross section of the peripheral part structure of the semiconductor element of FIG. 10 after resin sealing. The figure which shows the cross section at the time of processing the peripheral part structure of a semiconductor element using a laser based on 5th Embodiment. The figure which shows the cross section of the peripheral part structure of the semiconductor element of FIG. 12 after surface protection film removal and resin sealing. The figure which shows the cross section at the time of processing the peripheral part structure of a semiconductor element based on 6th Embodiment using the laser. The figure which shows the cross section of the peripheral part structure of the semiconductor element of FIG. 14 after surface protection film removal and resin sealing. Sectional drawing when a semiconductor element is made into the mount structure of an E-BGA type | mold for demonstrating the modification of this invention. Sectional drawing when it is for demonstrating the modification of this invention, and a semiconductor element is made into the mounting structure of FC-BGA type | mold. Sectional drawing when a semiconductor element is made into the T-BGA type mount structure for demonstrating the modification of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Mount substrate 12 ... Semiconductor element 13 ... Adhesive 14 ... Bonding wire 15 ... Solder ball 16 ... Sealing resin 17 ... Stiffener 18 ... Bump 21 ... Si substrate (semiconductor)
DESCRIPTION OF SYMBOLS 22 ... Interlayer insulating layer 23 ... Wiring layer 24 ... Laminated film 25 ... Groove 31 ... Surface protective film 32 ... Insulating film 33 ... Insulating film

Claims (5)

A laminated film including a plurality of layers including a low dielectric constant interlayer insulating film having a relative dielectric constant of 2 or less is formed on the surface of the semiconductor substrate, and a certain distance from the peripheral edge along the peripheral edge of the substrate A semiconductor element in which the laminated film is removed in a part of the inner side and the substrate is removed from the substrate surface to a predetermined depth;
A mounting substrate on which the semiconductor element is mounted;
A resin layer for resin-sealing at least the surface side of the semiconductor element;
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the predetermined depth from which the substrate is removed is 1 μm or more . The semiconductor device according to claim 1 , wherein an oxide film is formed on the exposed surface of the semiconductor element . 2. The semiconductor device according to claim 1, wherein the width of the removed portion of the laminated film is 1 to 300 [mu] m . For a semiconductor element in which a laminated film including a plurality of layers including an interlayer insulating film having a low relative dielectric constant of 2 or less is formed on the surface of a semiconductor substrate, the periphery of the semiconductor element along the peripheral edge of the substrate Removing the substrate by a RIE or laser beam from the substrate surface to a predetermined depth to a depth at which the substrate surface is exposed in a part of the inner side at a certain distance from the end; and
Mounting the semiconductor element on a mounting substrate;
A step of resin-sealing at least a surface side of the semiconductor element with a resin material;
A method for manufacturing a semiconductor device, comprising:

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