CN111445837A - Connector group, display control card, adapter plate and display screen system - Google Patents
Connector group, display control card, adapter plate and display screen system Download PDFInfo
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- CN111445837A CN111445837A CN201811620329.2A CN201811620329A CN111445837A CN 111445837 A CN111445837 A CN 111445837A CN 201811620329 A CN201811620329 A CN 201811620329A CN 111445837 A CN111445837 A CN 111445837A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
- H01R13/6461—Means for preventing cross-talk
- H01R13/6471—Means for preventing cross-talk by special arrangement of ground and signal conductors, e.g. GSGS [Ground-Signal-Ground-Signal]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
The embodiment of the invention discloses a connector group, a display control card, an adapter plate and a display screen system, wherein the connector group comprises: a first connector and a second connector arranged in a pair; wherein the first connector comprises: the power supply pin group, the first grounding pin group and the first multi-channel data group output pin group; the second connector includes: the second multi-channel data set output pin set, the display control signal output pin set, the multi-channel Ethernet interface pin set and the second grounding pin set; and a grounding pin is arranged between every two adjacent pairs of differential signal pin groups in each path of Ethernet interface pin group. The embodiment of the invention provides a new display control card interface scheme, and the related connector group has no strict requirement on the thickness of a circuit board.
Description
Technical Field
The invention relates to the technical field of display, in particular to a connector set, a display control card, an adapter plate and a display screen system.
Background
With the development of L ED display industry, the structure of the display box provided by the display screen manufacturer is gradually solidified, and in order to adapt to more display boxes provided by the display screen manufacturer, the receiving card product needs to be made into a core card with a smaller size.
At present, there are two interface schemes for receiving cards: the golden finger connection scheme has great requirements on the thickness of a circuit board, the circuit board needs to be designed to be 1 mm thick, but the circuit board with the thickness is easily deformed under the action of stress in the using process to cause chip cracking and the like, the requirement on the using environment of the golden finger connection scheme is higher, and when dust in the using environment is larger, interface connection failure is easily caused, and the golden finger connection scheme cannot be applied to the occasion of solid mounting; in addition, the connector involved in the high-density board-to-board connector scheme is generally 120 pins in the industry, the cost is high, a lot of pins are vacant and are not used, resources are wasted, and the product competitiveness is influenced.
Disclosure of Invention
The embodiment of the invention provides a connector set, a display control card, an adapter plate and a display screen system, and aims to overcome the defects of the prior related technical scheme.
Specifically, an embodiment of the present invention provides a connector set, including: a first connector and a second connector arranged in a pair; wherein the first connector comprises: the power supply pin group, the first grounding pin group and the first multi-channel data group output pin group; the second connector includes: the second multi-channel data set output pin set, the display control signal output pin set, the multi-channel Ethernet interface pin set and the second grounding pin set; and a grounding pin is arranged between every two adjacent pairs of differential signal pin groups in each path of Ethernet interface pin group.
In one embodiment of the present invention, the first connector further comprises: a reserved function expansion interface pin group which is arranged between the power supply pin group and the first multi-path data group output pin group; and the liquid crystal screen interface pin group is arranged at one end of the first multi-channel data group output pin group far away from the power supply pin group.
In one embodiment of the present invention, the second connector further comprises: and the test key and the state indicator lamp interface pin group are arranged between the display control signal output pin group and the multipath Ethernet interface pin group.
In one embodiment of the present invention, the first connector and the second connector have the same number of pins, and have 80 pins, 90 pins or 100 pins, respectively.
In one embodiment of the invention, the pin pitch of the first connector and the second connector is the same and is 1.27 mm or 2.0 mm, respectively.
In addition, an embodiment of the present invention provides a display control card, including: a first circuit board having a first surface and a second surface opposite to the first surface; a first connector set disposed on the first surface and being any one of the connector sets described above; the programmable logic device, the microcontroller and the multi-path Ethernet PHY chip are arranged on the second surface; the microcontroller is connected with the programmable logic device and the first connector group respectively, the programmable logic device is connected with the multi-path Ethernet interface pin group of the first connector group respectively through the multi-path Ethernet PHY chip, and the programmable logic device is also connected with the first multi-path data group output pin group, the second multi-path data group output pin group and the display control signal output pin group of the first connector group.
Furthermore, an embodiment of the present invention provides an interposer for connecting a display control card to a board, where the interposer includes: a second circuit board; the second connector group, the plurality of network ports and the plurality of lamp panel interfaces are arranged on the same side of the second circuit board; the second connector group is used for being connected with a display control card and is the connector group as described in any one of the preceding items; a plurality of net gapes are located the first side of second connector group, a plurality of lamp plate interfaces are located second connector group with the second side that first side is relative, a plurality of net gapes are connected respectively second connector group multichannel ethernet interface pin group, a plurality of lamp plate interface connection second connector group first multichannel data set output pin group second multichannel data set output pin group with show control signal output pin group.
In one embodiment of the present invention, the interposer further comprises: the network transformer, the driving chip set, the test key and the status indicator lamp are arranged on the second circuit board; the plurality of net gapes pass through network transformer connects the second connector group multichannel ethernet interface pin group, a plurality of lamp plate interfaces pass through drive chip group connects the second connector group first multichannel data set output pin group, second multichannel data set output pin group with show control signal output pin group, test button and status indicator lamp connect the second connector group.
Furthermore, the embodiment of the invention provides a display screen system, which comprises an L ED display screen, the display control card and the adapter plate, wherein the display control card and the adapter plate are connected through the first connector group and the second connector group, and the L ED display screen is connected with the lamp panel interfaces of the adapter plate.
In an embodiment of the invention, the second connector group is a simple ox horn pin header connector, and the first connector is a female header connector.
The technical scheme in the embodiment has the following advantages or beneficial effects: the method provides a new interface scheme applied to a display control card (such as a receiving card), adds a new choice for a user, does not need to consider the thickness of a circuit board, avoids the condition that the existing golden finger connection scheme has strict requirements on the thickness of the circuit board, and avoids the condition that the circuit board is too thin and is easy to deform under stress so as to cause the cracking of a chip in the golden finger connection scheme; the requirement on the use environment is not high, and the limitation of a golden finger connection scheme on the high requirement on the use environment is avoided; when the related connector group is a pin header connector or a female header connector, the conditions that the high-density board-to-board connector scheme is high in cost, a large number of pins are vacant and resources are not wasted are avoided, the number of the vacant pins is greatly reduced, the application rate of the pins is improved, the cost is saved, the probability of product abnormity is effectively reduced, the competitiveness of products is improved, and the intra-industry universality is high; the pins of the connectors arranged in pairs in the connector group are divided and reasonably distributed, so that the standardization of the definition of the input and output interfaces is facilitated; in addition, a grounding pin is arranged between every two adjacent pairs of differential signal pin groups in each path of Ethernet interface pin group, so that mutual interference of signals between differential signal pairs is avoided, the stability performance is better, and the anti-interference capability is stronger.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a connector set according to a first embodiment of the present invention;
fig. 2a and 2b are schematic pin distributions of the connectors in the connector group 10 of fig. 1 according to the first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a first surface of a display control card according to a second embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a second surface of a display control card according to a second embodiment of the present invention;
FIG. 5 is a diagram illustrating the connection relationship of components in a display control card according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of an interposer according to a third embodiment of the present invention;
fig. 7 is a schematic structural diagram of an interposer according to a third embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a display screen system according to a fourth embodiment of the present invention;
fig. 9 is a schematic diagram illustrating a specific connection relationship of connector groups of a display screen system according to a fourth embodiment of the present invention.
[ brief description of the drawings ]
10: a connector set; 11: a connector; 111: a power supply pin group; 112: a plurality of data group output pin groups; 113: a ground pin group; 114: reserving a function expansion interface pin group; 115: a liquid crystal screen interface pin group; 12: a connector; 121: a plurality of data group output pin groups; 122: a display control signal output pin group; 123: a plurality of Ethernet interface pin groups; 124: a ground pin group; 125: testing the key and the state indicator light interface pin group;
30: displaying a control card; 31: a circuit board; 311: a surface; 312: a surface; 32: a connector set; 33: a programmable logic device; 34: a microcontroller; 35: a plurality of Ethernet PHY chips; 36: a volatile memory; 37: a non-volatile memory; 38: a temperature and voltage sampling circuit;
40: an adapter plate; 41: a circuit board; 42: a connector set; 43: a plurality of network ports; 44: a plurality of light panel interfaces; 45: a network transformer; 46: a driver chipset; 47: testing the key and the status indicator lamp;
50 display screen system, 51 display control card, 511 connector group, 511a bus connector, 511b bus connector, 52 adapter board, 521 connector group, 521a pin connector, 521b pin connector, 522 lamp panel interface and 53L ED display screen.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The invention will be described in connection with embodiments with reference to the drawings.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not a whole embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the division of the embodiments of the present invention is only for convenience of description and should not be construed as a limitation, and features of various embodiments may be combined and referred to each other without contradiction.
[ first embodiment ] A method for manufacturing a semiconductor device
Referring to fig. 1, a first embodiment of the present invention provides a connector set. As shown in fig. 1, the connector set 10 includes: a connector 11 and a connector 12 arranged in pairs.
The connector 10 includes, for example: a power pin group 111, a multi-path data group output pin group 112, and a ground pin group 113. The connector 12 includes, for example: a multi-channel data set output pin set 121, a display control signal output pin set 122, a multi-channel ethernet interface pin set 123 and a ground pin set 124. A ground pin is disposed between every two adjacent pairs of differential signal pin sets in each ethernet interface pin set 123.
Further, as shown in fig. 1, the connector 11 further includes, for example: a reserved function expansion interface pin group 114 and a liquid crystal display interface pin group 115. The connector 12 further includes, for example: test key and status indicator light interface pin set 125.
The connector set 10 according to the first embodiment of the present invention will be described in detail with reference to fig. 2a and 2 b.
The connector 11 and the connector 12 in the connector group 10 provided in the first embodiment of the present invention are, for example, the connector JH1 shown in fig. 2a and the connector JH2 shown in fig. 2 b. The connector JH1 mainly includes a power supply pin group VCC, a ground pin group GND, a multi-path data group output pin group, and preferably also includes a reserved function extension interface pin group and a liquid crystal screen interface pin group. The connector JH2 mainly includes a ground pin group GND, a display control signal output pin group, a multi-path data group output pin group, an ethernet interface pin group, and preferably also includes a test key and a status indicator light interface pin group.
Specifically, in fig. 2a, pins 87-90 of connector JH1 correspond to a power pin group, VCC is, for example, a 5V power supply, pins 75-84 correspond to a reserved function extension interface pin group for extending functions of an intelligent module, a lamp panel F L ASH, etc., which are, for example, distributed between a multiple data set output pin group (corresponding pins 13-72) of connector JH1 and a power pin group, pins 13-72 of connector JH1 correspond to a multiple data set output pin group, for example, a multiple RGB data set output pin group, for outputting multiple RGB data signals to drive a L ED lamp panel of a L ED display screen for image display, each of the multiple data set output pin groups includes a red data (R) output pin, a green data (G) output pin, and a blue data (B) output pin, in this embodiment, connector JH1 and connector JH2 may be summed up to support 32 data sets, that is, a red data set output pin, a green data set (G) output pin, a blue data set (G) output pin, and a blue data set (B) output pin, which may be, a CD 8-8 pin, a keyboard controller may be set, a keyboard controller for receiving a keyboard, a keyboard.
Further, in FIG. 2B, pins 43-90 of connector JH2 correspond to a multi-data set output pin set, such as a multi-RGB data set output pin set, for outputting multi-RGB data signals to drive a L ED lamp panel of a L ED display screen for image display, each RGB data set output pin set includes a red data (R) output pin, a green data (G) output pin, and a blue data (B) output pin, pins 31-40 of connector JH2 correspond to a display control signal output pin set, wherein pins 40, 38, 36, 34, and 32 correspond to, respectively, A, B, C, D, E, which represent row selection signals, pins, 39 correspond to OE, which represent enable signal pins, pin 37 corresponds to CTR L, which represent blanking signal pins, pin 35 corresponds to L, which represent latch signal pins, pins 33, 31 correspond to DC L K2, DC L K2, which represent clock pins, 27, 7, 19, 27.
In addition, it is worth to be noted that, in the signal pin function assignment rule of the connector JH1 and the connector JH2, signal pins of the same type are assigned together, so that the wiring is convenient. Because the differential signals are high-speed signals and are susceptible to interference, preferably, a ground pin is arranged between every two adjacent pairs of differential signal pin groups in each path of ethernet interface pin group so as to avoid mutual interference between the differential signal pairs, and the ground pin has better anti-interference performance and is more stable. In addition, in order to improve the signal output reliability of the RGB data set, for each of the data set output pin groups on the pin group JH1 and the pin group JH2, a ground pin may be provided between each of the six data set output pin groups and another adjacent six data set output pin groups, and of course, the number of the data set output pin groups on both sides of the ground pin may not be limited to six and may be different.
The connector JH1 shown in fig. 2a and the JH2 shown in fig. 2b are both 90-pin connectors, but the embodiment is not limited thereto, and the number of pins of the connectors JH1 and JH2 of the embodiment is the same, for example, the number of pins may also be 80 pins or 100 pins. Also, the pin pitch of connector JH1 and connector JH2 is the same, for example, 1.27 mm or 2 mm. In addition, when the number of pins of the connector is 80, the multi-channel data set output pin group can be set to 24 channels of RGB data sets in the pin layout, and other pins can be adjusted accordingly. When the number of pins is 100, dummy pins and ground pins may be added as appropriate.
The connector JH1 or JH2 in this embodiment is, for example, a pin header connector or a female header connector, where the pin header connector is, for example, a simple ox horn pin header connector, abbreviated as "simple cow" connector, and is composed of a square plastic socket and a plurality of regularly arranged square pins.
Taking the connector JH1 and the connector JH2 as 90 pins as an example, the functions of the pins are defined as shown in table 1 and table 2.
TABLE 1 respective Pin function definitions for connector JH1
TABLE 2 respective Pin function definitions for connector JH2
In summary, the connector set 10 provided in the first embodiment of the present invention does not need to consider the thickness of the circuit board, thereby avoiding the situation that the existing gold finger connection scheme has strict requirements on the thickness of the circuit board, and avoiding the situation that the circuit board is too thin and is easily subjected to stress deformation to cause cracking of the chip in the gold finger connection scheme; the requirement on the use environment is not high, and the limitation of a golden finger connection scheme on the high requirement on the use environment is avoided; when the related connector group is a pin header connector or a female header connector, the conditions that the high-density board-to-board connector scheme is high in cost, a large number of pins are vacant and resources are not wasted are avoided, the number of the vacant pins is greatly reduced, the application rate of the pins is improved, the cost is saved, the probability of product abnormity is effectively reduced, the competitiveness of products is improved, and the intra-industry universality is high; the pins of the connectors arranged in pairs in the connector group are divided and reasonably distributed, so that the standardization of the definition of the input and output interfaces is facilitated; in addition, a grounding pin is arranged between every two adjacent pairs of differential signal pin groups in each path of Ethernet interface pin group, so that mutual interference of signals between differential signal pairs is avoided, the stability performance is better, and the anti-interference capability is stronger.
[ second embodiment ]
Referring to fig. 3 and 4, a second embodiment of the present invention provides a display control card. As shown in fig. 3 and 4, the display control card 30 includes, for example: circuit board 31, connector set 32, programmable logic device 33, microcontroller 34, and multiplexed ethernet PHY chip 35. In addition, as shown in fig. 5, the display control card 10 further includes some auxiliary components such as a volatile memory 36 and a non-volatile memory 37, and may further include additional functional circuits such as a temperature and voltage acquisition circuit 38.
Wherein the circuit board 31 has a surface 311 and a surface 312 opposite to the surface 311. As shown in fig. 3, the connector set 32 is disposed on the surface 311. As shown in fig. 4, programmable logic device 33, microcontroller 34, and multiplexed ethernet PHY chip 35 are all disposed on surface 312. Such a connector set 32 is separated from other circuit elements such as a programmable logic device 33, a microcontroller 34 and a multiplexed ethernet PHY chip 35 on different surfaces of the circuit board 31, which is advantageous for improving the convenience of plugging and for facilitating the heat dissipation of the circuit elements.
The connector set 32 is the connector set 10 according to the first embodiment of the present invention. The description of the connector set 32 may refer to the first embodiment, and for the sake of brevity, the description of the connector set 32 will not be repeated here.
Further, as shown in fig. 5, the microcontroller 34 is connected to the programmable logic device 33 and the connector set 32, the programmable logic device 33 is connected to the multiple ethernet interface pin sets (corresponding to pins 3-24 of the connector JH 2) of the connector set 32 through the multiple ethernet PHY chips 35, and the programmable logic device 33 is further connected to the multiple data set output pin sets (corresponding to pins 13-72 of the connector JH 1), the multiple data set output pin sets (corresponding to pins 43-90 of the connector JH 2), and the display control signal output pin set (corresponding to pins 31-40 of the connector JH 2) of the connector set 32.
Where the programmable logic device 33 is typically a Field Programmable Gate Array (FPGA) device, the microcontroller 34 is typically an MCU (e.g., an ARM core based MCU, etc.), and the ethernet PHY chip 35 is, for example, a two-way gigabit PHY chip. The volatile memory 36 is connected to the programmable logic device 33, which is, for example, a DDR memory. The nonvolatile memory 37, which is, for example, a Flash memory (Flash memory), is connected to the programmable logic device 33 and the microcontroller 34 so as to be shared by both.
The display control card 30 of this embodiment is, for example, a receiving card, and completes communication with a sending card and/or other cascaded receiving cards through a two-way gigabit network, a gigabit network signal passes through the ethernet PHY chip 35, and is converted into a media independent interface signal such as an RGMII signal by the ethernet PHY chip 35, and then communicates with the programmable logic device 33, the processing of the data is completed by the programmable logic device 33, the programmable logic device 33 processes data from the sending card or a preceding receiving card, and then converts the data into RGB data group signals and display control signals for controlling a L ED lamp panel in a L ED display screen, and outputs the RGB data group signals and the display control signals to an L ED lamp panel, the programmable logic device 33 temporarily stores the data in a volatile memory 36, the microcontroller 34 completes loading of the programmable logic device 33 and driving of liquid crystal, in addition, the microcontroller 34 further collects temperature and power supply information on the circuit board 31 through a temperature and voltage sampling circuit 38, and sends the temperature and power supply information to the programmable logic device 33, a nonvolatile memory 37 connected with the microcontroller 34 stores programs of the programmable logic device 33, and also stores L ED data, and generates correction data required for correct scanning in the data processing process in the lamp panel.
In summary, in this embodiment, the connector set of the first embodiment is configured on the display control card, so that the thickness of the circuit board does not need to be considered, the condition that the existing gold finger connection scheme has strict requirements on the thickness of the circuit board is avoided, and the condition that the circuit board is too thin and is easily subjected to stress deformation to cause cracking of the chip in the gold finger connection scheme is avoided; the requirement on the use environment is not high, and the limitation of a golden finger connection scheme on the high requirement on the use environment is avoided; when the related connector group is a pin header connector or a female header connector, the conditions that the high-density board-to-board connector scheme is high in cost, a large number of pins are vacant and resources are not wasted are avoided, the number of the vacant pins is greatly reduced, the application rate of the pins is improved, the cost is saved, the probability of product abnormity is effectively reduced, the competitiveness of products is improved, and the intra-industry universality is high; the pins of the connectors arranged in pairs in the connector group are divided and reasonably distributed, so that the standardization of the definition of the input and output interfaces is facilitated; in addition, a grounding pin is arranged between every two adjacent pairs of differential signal pin groups in each path of Ethernet interface pin group, so that mutual interference of signals between differential signal pairs is avoided, the stability performance is better, and the anti-interference capability is stronger.
[ third embodiment ]
Referring to fig. 6, a third embodiment of the present invention provides an adapter board for connecting with a display control card board. As shown in fig. 6, the interposer 40 includes, for example: circuit board 41, connector group 42, a plurality of net gapes 43 and a plurality of lamp plate interfaces 44.
The connector group 42, the plurality of network ports 43, and the plurality of lamp panel interfaces 44 are disposed on the same side of the circuit board 41.
The connector group 42 is the connector group 10 according to the first embodiment of the present invention. The description of the connector set 42 may refer to the first embodiment, and for the sake of brevity, the description of the connector set 42 will not be repeated here.
The network ports 43 are located on a first side of the connector group 42, the lamp panel interfaces 44 are located on a second side of the connector group 42 opposite to the first side, the network ports 43 are respectively connected with the multiple paths of ethernet interface pin groups (corresponding to pins 3-24 of the connector JH 2) of the connector group 42, and the lamp panel interfaces 44 are connected with the multiple paths of data group output pin groups (corresponding to pins 13-72 of the connector JH 1), the multiple paths of data group output pin groups (corresponding to pins 43-90 of the connector JH 2) and the display control signal output pin groups (corresponding to pins 31-40 of the connector JH 2) of the connector group 42. This kind of net gape 43 and lamp plate interface 44 divide the design of locating the opposite both sides of connector 42, and it is connected with the cable of external equipment to be favorable to keysets 40.
Further, as shown in fig. 7, the interposer 40 further includes: the network transformer 45, the driving chipset 46, and the test button and status indicator lamp 47 are disposed on the circuit board 41.
It should be noted that the network transformer 45 is moved from the display control card to the interposer 40, so that the transmission performance can be better optimized in terms of layout and wiring.
Further, the plurality of network ports 43 are connected to the multiple ethernet interface pin sets of the connector set 42 through the network transformer 45, for example, the plurality of network ports 43 are two network ports, which correspond to the two-way ethernet interface pin sets (corresponding to pins 3-24 of the connector JH 2) of the connector JH2 shown in fig. 2b, and the number of network ports can be set by referring to the number of the ethernet interface pin sets in the connector set 42. The plurality of lamp panel interfaces 44 are connected to the multi-path data set output pin set (corresponding to pins 13 to 72 of the connector JH 1), the multi-path data set output pin set (corresponding to pins 43 to 90 of the connector JH 2) and the display control signal output pin set (corresponding to pins 31 to 40 of the connector JH 2) of the connector set 42 through the driver chipset 46, and the test key and status indicator lamp 47 is connected to the test key and status indicator lamp interface pin set (corresponding to pins 27 to 28 of the connector JH 2) of the connector set 42.
In summary, in this embodiment, the connector set of the first embodiment is configured on the interposer 40, without considering the thickness of the circuit board, so as to avoid the situation that the existing gold finger connection scheme has strict requirements on the thickness of the circuit board, and avoid the situation that the circuit board is too thin and is easily subjected to stress deformation to crack the chip in the gold finger connection scheme; the requirement on the use environment is not high, and the limitation of a golden finger connection scheme on the high requirement on the use environment is avoided; when the related connector group is a pin header connector or a female header connector, the conditions that the high-density board-to-board connector scheme is high in cost, a large number of pins are vacant and resources are not wasted are avoided, the number of the vacant pins is greatly reduced, the application rate of the pins is improved, the cost is saved, the probability of product abnormity is effectively reduced, the competitiveness of products is improved, and the intra-industry universality is high; the pins of the connectors arranged in pairs in the connector group are divided and reasonably distributed, so that the standardization of the definition of the input and output interfaces is facilitated; in addition, a grounding pin is arranged between every two adjacent pairs of differential signal pin groups in each path of Ethernet interface pin group, so that mutual interference of signals between differential signal pairs is avoided, the stability performance is better, and the anti-interference capability is stronger.
[ fourth example ] A
Referring to fig. 8, a display screen system 50, for example, includes a display control card 51, a patch panel 52 and an L ED display screen 53 as shown in fig. 8.
The display control card 51 and the interposer 52 are connected by the connector set 511 and the connector set 521, and the L ED display 53 is connected to a plurality of lamp panel interfaces 522 of the interposer 52, for example, only one lamp panel interface 522 is illustrated in fig. 8.
The display control card 51 according to the fourth embodiment of the present invention is, for example, the display control card 30 according to the second embodiment, and the description of the display control card 51 refers to the second embodiment, and for brevity, repeated descriptions of the display control card 51 are omitted. The interposer 52 according to the fourth embodiment of the present invention is, for example, the interposer 40 according to the third embodiment, and the interposer 52 can be described with reference to the third embodiment, and for brevity, the description of the interposer 52 will not be repeated here.
Further, as shown in fig. 9, the connector group 511 is mentioned as including a female row connector 511a and a female row connector 511b provided in pairs, for example. The mentioned connector group 521 is, for example, a group including a pin header connector 521a and a pin header connector 521b arranged in pairs, and the pin header connector are connected in one-to-one correspondence to form a connection between the interposer 52 and the display control card 51. The pin header connector 521a/521b is, for example, a simple pin header connector, which is abbreviated as "simple pin" connector and is composed of a square plastic socket and a plurality of regularly arranged square pins.
Reference is made to L ED display 53, for example, a display assembled from L ED boxes, each L ED box including, for example, a L ED light panel or a plurality of L ED light panels, it is noted that a plurality of network cable interfaces, for example, RJ45 interfaces, are typically provided on the patch panel 52, and these network cable interfaces are connected to the plurality of ethernet interface pin sets (corresponding to pins 3-24 in the connector JH 2) of the connector JH2 shown in fig. 2 b.
In summary, in the display screen system 50 provided in this embodiment, the connector set of the first embodiment is configured on the display control card and the interposer, without considering the thickness of the circuit board, so as to avoid the situation that the existing golden finger connection scheme has a strict requirement on the thickness of the circuit board, and avoid the situation that the circuit board is too thin and is easily subjected to stress deformation in the golden finger connection scheme, so that the chip is cracked; the requirement on the use environment is not high, and the limitation of a golden finger connection scheme on the high requirement on the use environment is avoided; when the related connector group is a pin header connector or a female header connector, the conditions that the high-density board-to-board connector scheme is high in cost, a large number of pins are vacant and resources are not wasted are avoided, the number of the vacant pins is greatly reduced, the application rate of the pins is improved, the cost is saved, the probability of product abnormity is effectively reduced, the competitiveness of products is improved, and the intra-industry universality is high; the pins of the connectors arranged in pairs in the connector group are divided and reasonably distributed, so that the standardization of the definition of the input and output interfaces is facilitated; in addition, a grounding pin is arranged between every two adjacent pairs of differential signal pin groups in each path of Ethernet interface pin group, so that mutual interference of signals between differential signal pairs is avoided, the stability performance is better, and the anti-interference capability is stronger.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A connector set, comprising: a first connector and a second connector arranged in a pair; wherein the first connector comprises: the power supply pin group, the first grounding pin group and the first multi-channel data group output pin group; the second connector includes: the second multi-channel data set output pin set, the display control signal output pin set, the multi-channel Ethernet interface pin set and the second grounding pin set; and a grounding pin is arranged between every two adjacent pairs of differential signal pin groups in each path of Ethernet interface pin group.
2. The connector set of claim 1, wherein the first connector further comprises: a reserved function expansion interface pin group which is arranged between the power supply pin group and the first multi-path data group output pin group; and the liquid crystal screen interface pin group is arranged at one end of the first multi-channel data group output pin group far away from the power supply pin group.
3. The connector set of claim 1, wherein the second connector further comprises: and the test key and the state indicator lamp interface pin group are arranged between the display control signal output pin group and the multipath Ethernet interface pin group.
4. The connector set of claim 1, wherein the first connector and the second connector have the same number of pins and have 80 pins, 90 pins, or 100 pins, respectively.
5. The connector set of claim 1, wherein the pin pitch of the first connector and the second connector is the same and is 1.27 mm or 2.0 mm, respectively.
6. A display control card, comprising:
a first circuit board having a first surface and a second surface opposite to the first surface;
a first connector set provided on the first surface and being the connector set according to any one of claims 1 to 5; and
the programmable logic device, the microcontroller and the multi-path Ethernet PHY chip are arranged on the second surface;
the microcontroller is connected with the programmable logic device and the first connector group respectively, the programmable logic device is connected with the multi-path Ethernet interface pin group of the first connector group respectively through the multi-path Ethernet PHY chip, and the programmable logic device is also connected with the first multi-path data group output pin group, the second multi-path data group output pin group and the display control signal output pin group of the first connector group.
7. The utility model provides an adapter plate which characterized in that for be connected to the board with the display control cardboard, the adapter plate includes:
a second circuit board; and
the second connector group, the plurality of network ports and the plurality of lamp panel interfaces are arranged on the same side of the second circuit board;
wherein the second connector set is used for connecting with a display control card and is the connector set according to any one of claims 1 to 5;
a plurality of net gapes are located the first side of second connector group, a plurality of lamp plate interfaces are located second connector group with the second side that first side is relative, a plurality of net gapes are connected respectively second connector group multichannel ethernet interface pin group, a plurality of lamp plate interface connection second connector group first multichannel data set output pin group second multichannel data set output pin group with show control signal output pin group.
8. The interposer as recited in claim 7, further comprising: the network transformer, the driving chip set, the test key and the status indicator lamp are arranged on the second circuit board; the plurality of net gapes pass through network transformer connects the second connector group multichannel ethernet interface pin group, a plurality of lamp plate interfaces pass through drive chip group connects the second connector group first multichannel data set output pin group, second multichannel data set output pin group with show control signal output pin group, test button and status indicator lamp connect the second connector group.
9. A display screen system, comprising:
l ED display screen;
the display control card of claim 6; and
the interposer as recited in claim 7 or 8;
the display control card and the adapter plate are connected through the first connector group and the second connector group, and the L ED display screen is connected with the lamp panel interfaces of the adapter plate.
10. The display screen system of claim 9, wherein the second set of connectors is a simple header connector and the first connector is a header connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811620329.2A CN111445837A (en) | 2018-12-28 | 2018-12-28 | Connector group, display control card, adapter plate and display screen system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811620329.2A CN111445837A (en) | 2018-12-28 | 2018-12-28 | Connector group, display control card, adapter plate and display screen system |
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| Publication Number | Publication Date |
|---|---|
| CN111445837A true CN111445837A (en) | 2020-07-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811620329.2A Pending CN111445837A (en) | 2018-12-28 | 2018-12-28 | Connector group, display control card, adapter plate and display screen system |
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| CN (1) | CN111445837A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113745865A (en) * | 2021-08-30 | 2021-12-03 | 武汉华星光电技术有限公司 | Pin connector and display panel |
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Application publication date: 20200724 |