CN210200192U - Plug-in assembly, display control card and display system - Google Patents

Abstract

The embodiment of the utility model discloses connect and insert subassembly, include: the first connector comprises a power pin group, a function expansion pin group and a plurality of first data output pin groups, wherein the function expansion pin group is positioned between the plurality of first data output pin groups and the power pin group in the length direction of the first connector; the second connector comprises a display control signal output pin group, a plurality of Ethernet interface pin groups and a plurality of second data output pin groups, and the display control signal output pin group is positioned between the plurality of second data output pin groups and the plurality of Ethernet interface pin groups in the length direction of the second connector; and a grounding pin pair is arranged between two adjacent first data output pin groups, and a grounding pin pair is arranged between two adjacent second data output pin groups. The embodiment of the utility model provides a display control card and display system who adopts this kind of plug subassembly are still disclosed.

Description

Plug-in assembly, display control card and display system

Technical Field

The utility model relates to a show technical field, especially relate to a connect and insert subassembly, a display control board and a display system.

Background

With the development of the LED display industry, the structure of the display box provided by the display screen manufacturer is gradually solidified. In order to adapt to more display boxes provided by display screen manufacturers, the receiving card product needs to be made into a core card with smaller size. The core card is usually used with an adapter board (or HUB board) connected together through a connector to drive a display box in the LED display screen. Currently common connectors are gold fingers and board-to-board connectors. However, the gold finger connection has high requirements on the thickness and the error of the core board, so that the gold finger connection is easily subjected to stress deformation during use, so that the chip cracks and other problems are caused, and on the other hand, the signal transmission is greatly influenced by the abrasion of the core board or the error caused by the thickness of the board. At present, a board-to-board connector which is the mainstream in the industry is a 120pin connector, but a plurality of pins used for function expansion are not used, so that the problems of not compact pin arrangement, waste of interface pin resources and higher production cost exist.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides a connect and insert subassembly, a display control board and a display system realizes that interface pin is compact to be arranged, practices thrift interface resource, reduction in production cost.

In one aspect, an embodiment of the present invention provides a connector assembly, including a first connector and a second connector arranged in pair, where the first connector includes a power pin group, a function expansion pin group, and a plurality of first data output pin groups, and the function expansion pin group is located between the plurality of first data output pin groups and the power pin group in a length direction of the first connector; the second connector comprises a display control signal output pin group, a plurality of Ethernet interface pin groups and a plurality of second data output pin groups, and the display control signal output pin group is positioned between the plurality of second data output pin groups and the plurality of Ethernet interface pin groups in the length direction of the second connector; a grounding pin pair is arranged between two adjacent first data output pin groups, and a grounding pin pair is arranged between two adjacent second data output pin groups; each first data output pin group comprises M groups of data output pins; each second data output pin group comprises N groups of data output pins, wherein M and N are respectively positive even numbers, and M is larger than N; each set of the data output pins includes a red data output pin, a green data output pin, and a blue data output pin.

The socket assembly of the embodiment is centralized and compactly arranged by butting all pin groups in the socket assembly, so that the reasonable distribution of interface resources is realized, and the cost is reduced.

In an embodiment of the present invention, the plurality of ethernet interface pin groups are arranged in series on both sides of the second connector, and a pair of ground pins is disposed between the plurality of ethernet interface pin groups and the display control signal output pin group.

In an embodiment of the present invention, a pair of ground pins is provided between the function extension pin group and the plurality of first data output pin groups, and an idle pin is provided between the function extension pin group and the power supply pin group.

In an embodiment of the present invention, the first connector includes eighty-four pins and the length direction of the first connector is sequentially: the power supply circuit comprises two grounding pins, eighteen data output pins, two grounding pins, sixteen function expansion pins, two idle connection pins and four power supply pins; the second connector includes eighty-four pins and is in the length direction of second connector is in proper order: two ground pins, sixteen ethernet interface pins, two ground pins, a test key input signal pin, a status light signal pin, two ground pins, ten display control signal output pins, two ground pins, twelve data output pins, two ground pins, and six data output pins.

The utility model discloses an embodiment, function extension pin group is including five lamp plate memory control interface pins, a lamp plate memory serial clock signal pin, a lamp plate memory serial interface chip selection signal pin, a shift register data signal pin, a shift register clock signal pin, a lamp plate memory storage data input pin or an intelligent module data transmission signal pin, a lamp plate memory storage data output pin or an intelligent module data reception signal pin, a double cassette connect signal pin, a double cassette identification signal pin and two power detection signal pins.

On the other hand, the embodiment of the utility model provides a display control card includes: the device comprises a circuit board, a programmable logic device, a microcontroller, an Ethernet physical layer transceiver and a first plug-in assembly; the first connector assembly is the connector assembly as described above; the programmable logic device, the microcontroller, the Ethernet physical layer transceiver and the first socket assembly are arranged on the circuit board; the microcontroller is connected with the programmable logic device and the power pin group of the first connector, the Ethernet physical layer transceiver is connected between the programmable logic device and the multi-path Ethernet interface pin group of the second connector of the first connector assembly, and the programmable logic device is connected with the power pin group of the first connector assembly, the function expansion pin group, the plurality of first data output pin groups and the plurality of second data output pin groups of the second connector of the first connector assembly and the display control signal output pin group.

The technical scheme has the following advantages and effects: the plug-in assembly is configured on the display control card, so that the input and output interfaces of the display control card tend to be standardized, and the convenience of connection is improved.

In an embodiment of the present invention, the display control card further includes an adapter plate, a second connector assembly having the same pin definition as the connector assembly is disposed on the adapter plate, and the adapter plate is connected to the first connector assembly through the second connector assembly; the patch board is also provided with a network transformer and an Ethernet interface connected with the network transformer, and the Ethernet interface is connected with the multi-path Ethernet interface pin group of the first plug assembly through the network transformer and the second plug assembly.

In another aspect, an embodiment of the present invention provides a display system, including: the display control card and the LED lamp panel are as described above; a data output interface is arranged on the adapter plate of the display control card, the data output interface is connected with the second socket assembly, and the data output interface is connected with the plurality of first data output pin groups of the first socket assembly, the plurality of second data output pin groups of the second socket assembly and the display control signal output pin group through the second socket assembly; and the LED lamp panel is provided with a lamp panel input interface, and the LED lamp panel is connected with the data output interface through the lamp panel input interface.

Still another technical scheme in above-mentioned technical scheme has following advantage or beneficial effect: the various pin groups in the plug-in component are intensively and compactly arranged, so that the reasonable distribution of interface resources is realized, and the cost is reduced. In addition, the plug-in assembly is configured on the display control card, so that the input and output interfaces of the display control card tend to be standardized, and the connection between the plug-in assembly and the rear end adapter plate is facilitated. Moreover, through defining the pins of the function extension pin group and designing a corresponding display control card and an LED lamp panel, the backup of correction coefficients and parameters of the LED lamp panel, the intelligent monitoring function extension of the LED lamp panel module, the dual-power monitoring, the data transmission of the dual-receiving card and the like are realized to ensure the display effect of the LED lamp panel.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 and 2 are schematic diagrams showing pin distributions of two connectors arranged in pairs in a connector assembly according to a first embodiment of the present invention.

Fig. 3a is a schematic structural diagram of a display control card according to a second embodiment of the present invention.

Fig. 3b is a schematic structural diagram of another display control card according to a second embodiment of the present invention.

Fig. 3c-3e are circuit connection diagrams of some components in the display control card according to the second embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a display system according to a third embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

First embodiment

As shown in FIGS. 1 and 2, a connector assembly according to a first embodiment of the present invention includes a connector JH1 and a connector JH2 arranged in pairs. The connector JH1 includes, for example, a power pin set, a plurality of first data output pin groups, and a function extension pin set. Connector JH2 includes, for example, a display control signal output pin set, a plurality of second data output pin sets, a multi-path ethernet interface pin set, and preferably also a test key input signal pin and a status light signal pin. The plurality of first data output pin groups and the plurality of second data output pin groups are used for transmitting multiple paths of RGB data signals to drive a display unit such as an LED lamp panel to display pictures. The number of the first data output pin groups is, for example, 3, but may be other positive integers; the number of the second data output pin groups is, for example, 3, but may be other positive integers. Each first data output pin group comprises M groups of data output pins, and each second data output pin group comprises N groups of data output pins, wherein M and N are respectively positive even numbers and M is larger than N. Specifically, each first data output pin group includes, for example, six sets of data output pins, each second data output pin group includes four sets of data output pins, and a third data output pin group including two sets of data output pins is further provided in connector JH2 shown in fig. 2. Each set of data output pins includes, for example, a red data (R) output pin, a green data (G) output pin, and a blue data (B) output pin. In this embodiment, connector JH1 and connector JH2 together may support up to 32 RGB data set outputs.

In the aspect of pin arrangement, the function extension pin group is located between the plurality of first data output pin groups and the power supply pin group in the length direction (vertical direction in fig. 1) of the connector JH1, and the plurality of first data output pin groups and the power supply pin group are spaced apart, so that the distance between the plurality of first data output pin groups and the power supply pin group is increased, and thus, not only can the pin arrangement be more compact, but also the interference of a power supply to an RGB data group can be reduced, and the stability of data transmission is improved. The display control signal output pin group is located between the plurality of second data output pin groups and the multi-path ethernet interface pin group in the length direction (vertical direction in fig. 2) of the connector JH 2. The mode of arranging the pins with the same function together in a centralized manner enables the pin arrangement of the connector JH1 and the pin arrangement of the JH2 to be more compact, and the arrangement of the grounding pins according to a fixed rule is beneficial to reducing the wiring difficulty. In addition, a grounding pin pair, for example, two grounding pins, is arranged between two adjacent first data output pin groups, and a grounding pin pair, for example, two grounding pins, is arranged between two adjacent second data output pin groups, so that the signal transmission reliability and stability of the RGB data set can be improved. Furthermore, a pair of ground pins, for example, two ground pins, is disposed between the functional expansion pin set and the first data output pin groups of the connector JH1, so as to further improve the reliability and stability of signal output of the RGB data set. Furthermore, a vacant connection pin is arranged between the function expansion pin group and the power supply pin group; therefore, the problems of short circuit, misconnection and the like caused by pin dislocation when the connector JH1 is plugged and unplugged can be prevented. The fool-proof design can reduce the failure rate of products and improve the quality of the products. Furthermore, the test key input signal pin and the status light signal pin are positioned between the multipath Ethernet interface pin group and the display control signal output pin group. And a grounding pin pair is also arranged between the test key input signal pin and the state lamp signal pin and between the multipath Ethernet interface pin group. And a grounding pin pair is also arranged between the test key input signal pin, the state lamp signal pin and the display control signal output pin group. Therefore, signal interference between the test key input signal pin and the state lamp signal and the multi-path Ethernet interface pin group and between the test key input signal pin and the state lamp signal and between the test key input signal pin and the multi-path Ethernet interface pin group and between the test key input signal pin and the display control signal output. In this way, the reasonable distribution of interface resources of connectors JH1 and JH2 is achieved.

Typically, the pin count of connectors JH1 and JH2 is no greater than 100, respectively. Specifically, compared with the 120-pin connector in the prior art, the connectors JH1 and JH2 in the embodiment of the present invention are, for example, female sockets or male sockets of 84 pins, respectively, and the definition of the function of each pin is shown in tables 1 and 2. The utility model provides a connector JH1 and JH2 have saved a plurality of unused pins to arrange the mode with more excellent pin and be used for realizing the data transmission and the various function extension demands of display control card.

TABLE 1 definition of respective Pin Functions of connector JH1

TABLE 2 various Pin function definitions for connector JH2

Specifically, as shown in fig. 1 and table 1, 84 pins of connector JH1 sequentially have the following lengths: 2 ground pins (pins 1 and 2), 18 data output pins (pins 3 to 20), 2 ground pins (pins 21 and 22), 18 data output pins (pins 23 to 40), 2 ground pins (pins 41 and 42), 18 data output pins (pins 43 to 60), 2 ground pins (pins 61 and 62), 16 function extension pins (pins 63 to 78), 2 idle connection pins (pins 79 and 80), and 4 power supply pins (pins 81 to 84). In addition, the voltage of each power supply pin is, for example, 5V dc voltage, and the maximum current is, for example, 0.5A, so that 4 power supply pins can supply a maximum current of 2A. In other embodiments of the present invention, the number of pins of the power pin set can be set according to actual requirements, and the present disclosure is not limited thereto. In other embodiments of the present invention, the empty pin between the function extension pin group and the power pin group can be replaced by a power pin, a function extension pin or a ground pin, or even the empty pin can be cancelled.

The pins of the function extension pin group are function extension interfaces and are mainly used for extension of functions such as a lamp panel memory (for example, a FLASH memory), a lamp panel intelligent module, double-receiving card backup and double-power detection. Therefore, the function extension pin group may include, for example, part or all of a lamp panel memory control interface pin, a lamp panel memory serial clock signal pin, a lamp panel memory serial interface chip select signal pin, a lamp panel memory storage data input pin, an intelligent module data transmission signal pin, a lamp panel memory storage data output pin, an intelligent module group data reception signal pin, a shift register data signal pin, a shift register clock signal pin, a power detection signal pin, a dual card connection signal pin, and a dual card identification signal pin.

The utility model discloses function extension pin group in connector JH1 in the embodiment includes 16 pins, and specific pin definition refers to table 3. Specifically, the function extension pin group includes, for example, 5 board memory control interface pins (HUB _ CODE0, HUB _ CODE1, HUB _ CODE2, HUB _ CODE3, and HUB _ CODE4), 1 board memory serial clock signal pin (SPI _ CLK), 1 board memory serial interface chip select signal pin (SPI _ CS), 1 board memory storage DATA input pin (SPI _ MOSI), 1 board memory storage DATA output pin (SPI _ MISO), 1 shift register DATA signal pin (H164_ CSD), 1 shift register clock signal pin (H164_ CLK), 1 two-card connection signal pin (MS _ DATA), 1 two-card identification signal pin (MS _ ID), 2 POWER detection signal pins (POWER _ STA1, POWER _ STA2), and one vacant pin. The empty pin herein may also be defined as other functional extensions, and the embodiments of the present invention are not limited thereto. In addition, in order to further save interface pin resources, the lamp panel memory storage data input pin (SPI _ MOSI) can be multiplexed into an intelligent module data transmission signal pin (UART _ TX), and the lamp panel memory storage data output pin (SPI _ MISO) can be multiplexed into an intelligent module data reception signal pin (UART _ RX), so as to be used for expanding the functions of the intelligent module. Therefore, the number of pins of the connector JH1 is smaller, the pins are more compact, the pin interface resources are saved, and the production cost is reduced. It should be noted that in other embodiments, connector JH1 may not have a function extension pin set, or may be user-defined as another function pin such as a data output pin, or even an air terminal pin. The present embodiment is not limited thereto.

TABLE 3 function extension pin set interface definition

Pin name	Pin signal	Brief description of the drawings
			RFU3	HUB_CODE0	Lamp panel memory control interface 1
RFU4	SPI_CLK	Lamp panel memory serial clock signal
			RFU5	HUB_CODE1	Lamp panel memory control interface 2
RFU6	SPI_CS	Lamp panel memory serial interface chip selection signal
			RFU7	HUB_CODE2	Lamp panel memory control interface 3
RFU8	SPI_MOSI/UART_TX	Lamp panel memory storage data input/intelligent module data transmission signal
			RFU9	HUB_CODE3	Lamp panel memory control interface 4
RFU10	SPI_MISO/UART_RX	Lamp panel memory storage data output/intelligent module data receiving signal
			RFU11	H164_CSD	Shift register data signal
RFU12	/	Vacant
			RFU13	H164_CLK	Shift register clock signal
RFU14	POWER_STA1	Power supply detection signal 1
			RFU15	MS_DATA	Dual card connection signal
RFU16	POWER_STA2	Power supply detection signal 2
			RFU17	MS_ID	Dual card identification signal
RFU18	HUB_CODE4	Lamp panel memory control interfaceMouth 5

It should be noted that in other embodiments of the present invention, the function extension pin set on connector JH1 can also be defined by the user as pins with other functions, such as power pin, ground pin, data output pin, etc., and even as empty or idle pins. The present embodiment is not limited thereto.

As shown in fig. 2 and table 2, 84 pins of connector JH2 sequentially have the following lengths in the longitudinal direction: 2 ground pins (pins 1, 2), 16 ethernet interface pins (pins 3-18), 2 ground pins (pins 19, 20), 1 test key input signal pin (pin 21), 1 status light signal pin (pin 22), 2 ground pins, 10 display control signal output pins (pins 23-34), 2 ground pins (pins 35, 36), 12 data output pins (pins 37-48), 2 ground pins (pins 49, 50), 12 data output pins (pins 51-62), 2 ground pins (pins 63, 64), 12 data output pins (pins 65-76), 2 ground pins (pins 77, 78), and 6 data output pins (pins 76-84).

In addition, as can be seen from fig. 2, 16 ethernet interface pins (pins 3 to 18) are symmetrically distributed on two sides of the connector JH2 in the horizontal direction, 8 ethernet interface pins are distributed on each side, and 8 ethernet interface pins on each side are continuously distributed on the connector JH2, that is, no ground pin is arranged between two adjacent ethernet interface pins. Thus, the 84-pin connector pin arrangement provided by the present embodiment is more compact, less costly, and more convenient to wire than the existing 120-pin connector.

In summary, in the present embodiment, various pin groups in the socket assembly are arranged in a centralized manner, and pins of the same type of functional signals are distributed together, so that the pins of the socket assembly are more compact and convenient to wire, the reasonable distribution of interface resources is realized, and the cost is reduced. In addition, a vacant connection pin is arranged between the function expansion pin group and the power supply pin group. Therefore, the problems of short circuit, misconnection and the like caused by pin dislocation when the connector JH1 is plugged and unplugged can be prevented. The fool-proof design can reduce the failure rate of products and improve the quality of the products. Compared with the existing 120-pin connector, the connector with no more than 100 pins, for example 84 pins, is designed, a plurality of unused pins are omitted, and the data transmission and various function expansion requirements of the display control card are realized in a more optimal pin arrangement mode. Furthermore, the multiple paths of Ethernet interface pin groups are continuously arranged on two sides of the connector JH2, so that the pin arrangement of the connector JH2 is more compact, the cost is lower, and the connection is more convenient.

Second embodiment

As shown in fig. 3a, a display control card 20 provided in the second embodiment of the present invention includes: circuit board 21, programmable logic device 22, microcontroller 23, ethernet physical layer transceivers 24a and 24b, and connector assembly 25. In addition, the display control card 20 further includes auxiliary devices such as a volatile memory 26 and a nonvolatile memory 27. The programmable logic device 22, the microcontroller 23, the ethernet physical layer transceivers 24a and 24b and the connector assembly 25, as well as auxiliary devices such as volatile memory 26 and non-volatile memory 27 are disposed on the circuit board 21.

Where the programmable logic device 22 is typically a Field Programmable Gate Array (FPGA) device, the microcontroller 23 is connected to the programmable logic device 22 and the power pin set of the connector JH1 of the connector assembly 25, and is typically an MCU (e.g., an ARM core based MCU, etc.), and the ethernet physical layer transceivers 24a, 24b are connected to the programmable logic device 22, which is, for example, a two-way gigabit PHY chip. Of course, only one ethernet interface may be provided on the patch panel 31. The connector assembly 25 is, for example, formed of a pair of connector JH1 shown in FIG. 1 and connector JH2 shown in FIG. 2, which may be male connectors. The Ethernet physical layer transceivers 24a and 24b are connected with the multi-path Ethernet interface pin group of the connector JH2 and the power pin group of the connector JH1, and the programmable logic device 22 is connected with the power pin group of the connector JH1, a plurality of first data output pin groups, the function expansion pin group, a plurality of second data output pin groups of the connector JH2 and the display control signal output pin group. Volatile memory 26 connects programmable logic device 22 to a power pin set of connector JH1, such as a DDR memory; the nonvolatile memory 27 is connected to the programmable logic device 22, the microcontroller 23, and the power supply pin group of the connector JH1 so as to be shared by both, and is, for example, a FLASH memory (FLASH memory).

In addition, as shown in fig. 3b, the display control card 20 may further include an interposer 31. The adaptor plate 31 is provided with a connector assembly 32. The connector assembly 32 is, for example, a connector assembly having the same pin definition as the connector assembly 25, such as two female connector receptacles having 84 pins that mate with the male connector receptacles. Of course, the connector may have other pin numbers, and the disclosure is not limited thereto. Further, the patch panel 31 is further provided with a network transformer 33 and ethernet interfaces 34a and 34b for connecting the network transformer. Ethernet interfaces 34a and 34b are, for example, RJ45 interfaces. The Ethernet interfaces 34a and 34b are connected to the multiple Ethernet interface pin sets of the connector assembly 25 via the network transformer 33 and the connector assembly 32. The circuit board 21 and the adapter board 31 are plugged by the matching plug-in module 25 and the plug-in module 32, so that a user can arrange core components on the display control card 20, such as the programmable logic device 22, the microcontroller 23, the ethernet physical layer transceivers 24a and 24b, and the like, on the circuit board 21 to form a core card, thereby facilitating personalized customization of the adapter board 31 and modular design of the core card to better meet market requirements. The core card formed by the circuit board 21 and the electrical components thereon at this time may also be referred to as a receiving card. In addition, the network transformer 33 is arranged on the adapter board instead of the receiving card, so that the size of the core card or the receiving card can be reduced, and the cost and the processing difficulty of the core card or the receiving card can be reduced. The present embodiment configures the connector assembly as described in the first embodiment on the display control card 20, which can facilitate the standardization of the input/output interface of the display control card 20.

The main circuit connections of the main components in this embodiment are shown in fig. 3c-3 e. Specifically, fig. 3c to 3d are partial circuit connection diagrams of the programmable logic device 22, and fig. 3e is a main circuit connection diagram of the microcontroller 23.

Third embodiment

As shown in fig. 4, a display system 50 according to a third embodiment of the present invention includes: a display control card 51 and one or more LED lamp panels 55 (only one is shown in fig. 4 as an example) connected to the display control card 51. The display control card 51 is loaded and lights the LED lamp panel 55 to display a picture. The display control card 51 includes a receiving card 511 and a patch panel 513. The receiving card 511 includes, for example, the circuit board 21 in the second embodiment and the electric components thereon. The interposer 513 may, for example, include the interposer 31 of the second embodiment and the electrical components thereon. The receiving card 511 is provided with a connector assembly 5111, and the adapter plate 513 is provided with a connector assembly 5131 having the same pin definition as the connector assembly 5111.

Typically, the patch panel 513 is also provided with one or more data output interfaces 5132 (only one shown as an example in fig. 4). The data output interface 5132 is, for example, a connector, such as a 16-pin or 26-pin strip socket or a socket, which can be connected to the LED lamp panel 55, for example, via a flexible cable or other connecting device. The data output interface 5132 is connected to the plurality of first data output pin groups, the plurality of second data output pin groups and the display control signal output pin group of the socket assembly 5111 of the receiving card 51 through the socket assembly 5131, so as to obtain the display data (RGB) to be output and the corresponding display control signal (Ctrl) to light the LED lamp panel 55 and perform the image display. It should be noted here that a signal driving circuit (not shown in fig. 4) may be further disposed on the interposer 513. The data output interface 5132 is connected to the connector assembly 5131 via a signal driving circuit. The signal driving circuit is used for performing signal enhancement on the RGB data and the display control signal (Ctrl). The signal driver circuit comprises, for example, a signal driver chip, which may be, for example, of the type 74HC 245. The signal driving circuit may only include one signal driver chip, and may also include a plurality of signal driver chips, and it may be determined according to the actual needs of the circuit, the embodiment of the present invention is not limited to this.

The LED lamp panel 55 includes a lamp panel input interface 551, for example. The lamp panel input interface 551 plugs with the data output interface 5132, for example, to obtain the display data (RGB) and the corresponding display control signal (Ctrl). Here, the LED lamp panel 55 typically further includes an LED driving chip and a row decoding chip. The LED driving chip acquires RGB display data and partial signals such as OE and LAT in display control signals (Ctrl) from the lamp panel input interface, the row decoding chip acquires the other partial signals such as A-E in the display control signals (Ctrl) from the lamp panel input interface 551, and the column driving chip and the row decoding chip are matched with each other to realize picture display. The LED driving chip and the row decoding chip can be commercially available chips, which are not described herein.

In addition, it should be understood that the foregoing embodiments are merely exemplary of the present invention, and the technical solutions of the embodiments can be arbitrarily combined and collocated without conflict between technical features and structures, and not departing from the purpose of the present invention.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform some steps of the method according to various embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims (8)

1. A connector assembly is characterized by comprising a first connector and a second connector which are arranged in pairs, wherein the first connector comprises a power pin group, a function expansion pin group and a plurality of first data output pin groups, and the function expansion pin group is positioned between the plurality of first data output pin groups and the power pin group in the length direction of the first connector; the second connector comprises a display control signal output pin group, a plurality of Ethernet interface pin groups and a plurality of second data output pin groups, and the display control signal output pin group is positioned between the plurality of second data output pin groups and the plurality of Ethernet interface pin groups in the length direction of the second connector;

a grounding pin pair is arranged between two adjacent first data output pin groups, and a grounding pin pair is arranged between two adjacent second data output pin groups; each first data output pin group comprises M groups of data output pins; each second data output pin group comprises N groups of data output pins, wherein M and N are respectively positive even numbers, and M is larger than N; each set of the data output pins includes a red data output pin, a green data output pin, and a blue data output pin.

2. The connector assembly of claim 1, wherein said plurality of ethernet interface pin sets are arranged in series on opposite sides of said second connector, and a pair of ground pins are provided between said plurality of ethernet interface pin sets and said display control signal output pin set.

3. The connector assembly of claim 2, wherein a pair of ground pins are disposed between the set of function expansion pins and the plurality of first data output pins, and a pair of dummy pins are disposed between the set of function expansion pins and the set of power pins.

4. The connector assembly of claim 3,

first connector includes eighty four pins and is in the length direction of first connector is in proper order: the power supply circuit comprises two grounding pins, eighteen data output pins, two grounding pins, sixteen function expansion pins, two idle connection pins and four power supply pins;

the second connector includes eighty-four pins and is in the length direction of second connector is in proper order: two ground pins, sixteen ethernet interface pins, two ground pins, a test key input signal pin, a status light signal pin, two ground pins, ten display control signal output pins, two ground pins, twelve data output pins, two ground pins, and six data output pins.

5. The connector assembly of claim 4, wherein the set of function extension pins includes five lamp panel memory control interface pins, one lamp panel memory serial clock signal pin, one lamp panel memory serial interface chip select signal pin, one shift register data signal pin, one shift register clock signal pin, one lamp panel memory storage data input pin or one smart module data transmit signal pin, one lamp panel memory storage data output pin or one smart module data receive signal pin, one dual card connection signal pin, one dual card identification signal pin, and two power detection signal pins.

6. A display control card, comprising: the device comprises a circuit board, a programmable logic device, a microcontroller, an Ethernet physical layer transceiver and a first plug-in assembly; the connector assembly of any one of claims 1-5; the programmable logic device, the microcontroller, the Ethernet physical layer transceiver and the first socket assembly are arranged on the circuit board; the microcontroller is connected with the programmable logic device and the power pin group of the first connector, the Ethernet physical layer transceiver is connected between the programmable logic device and the multi-path Ethernet interface pin group of the second connector of the first connector assembly, and the programmable logic device is connected with the power pin group of the first connector assembly, the function expansion pin group, the plurality of first data output pin groups and the plurality of second data output pin groups of the second connector of the first connector assembly and the display control signal output pin group.

7. The display control card of claim 6, further comprising an adapter board, wherein a second connector assembly having the same pin definition as the connector assembly is disposed on the adapter board, and the adapter board is connected to the first connector assembly through the second connector assembly; the patch board is also provided with a network transformer and an Ethernet interface connected with the network transformer, and the Ethernet interface is connected with the multi-path Ethernet interface pin group of the first plug assembly through the network transformer and the second plug assembly.

8. A display system, comprising: a display control card and LED light panel according to claim 7; a data output interface is arranged on the adapter plate of the display control card, the data output interface is connected with the second socket assembly, and the data output interface is connected with the plurality of first data output pin groups of the first socket assembly, the plurality of second data output pin groups of the second socket assembly and the display control signal output pin group through the second socket assembly; and the LED lamp panel is provided with a lamp panel input interface, and the LED lamp panel is connected with the data output interface through the lamp panel input interface.

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