CN116662241A

CN116662241A - Computer backboard interface address matching system and method

Info

Publication number: CN116662241A
Application number: CN202310558905.XA
Authority: CN
Inventors: 陈强; 韩娇
Original assignee: Wuxi Advanced Technology Research Institute
Current assignee: Wuxi Advanced Technology Research Institute
Priority date: 2023-05-18
Filing date: 2023-05-18
Publication date: 2023-08-29

Abstract

The application discloses a computer backboard interface address matching system and a method in the technical field of computer hardware connection, which aim to solve the problem that hardware on an interface cannot be identified due to single connection relation between a main board and a backboard and according to non-fixed collocation; according to the application, the voltage signals of different groups are sent to each interface through the main board, the analog-to-digital conversion module corresponding to each interface converts the voltage signals into digital signals, and the address distribution module is matched with the corresponding interface according to the digital signals, so that the identification of the interface on the back board by the main board can be realized no matter the main board is in communication connection with the back board in any connection relation, and the flexibility of the installation of the back board cable is improved; the application can be widely applied to the communication connection between the server main board and each functional back board, and reduces the error rate and the management cost.

Description

Computer backboard interface address matching system and method

Technical Field

The application relates to a computer backboard interface address matching system and method, and belongs to the technical field of computer hardware connection.

Background

Different from a personal computer, the main stream server is usually plugged in the backboard by a hardware interface because of various and numerous hardware types and quantity to be plugged in, and in order to facilitate heat dissipation and disassembly, and then the backboard is in communication connection with the main board; therefore, when the motherboard and the back board are in multi-path communication connection, a plurality of connection relations are generated corresponding to a plurality of interfaces, and in the present stage, the interface address on the back board is fixedly matched with the motherboard, and a plurality of cables of the back board and the motherboard are not connected according to an operation manual, namely, the connection relations between the interfaces of the hardware and the motherboard are changed, so that the hardware on the interfaces cannot be identified due to the error of the interface address, for example, when the hardware is an NVMe (Non-Volatile Memory express, non-volatile memory host controller interface specification) hard disk, the position of the hard disk cannot be identified, and the hot plug and status indication function fail.

The information disclosed in this background section is only for enhancement of understanding of the general background of the application and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The application aims to overcome the defects in the prior art and provides a computer backboard interface address matching system and method for automatically matching an address for an interface on a backboard when the backboard is in communication connection with a main board.

In order to achieve the above purpose, the application is realized by adopting the following technical scheme:

in a first aspect, the present application provides a computer back board interface address matching system, including a motherboard and a back board, where the back board is configured with multiple groups of interfaces for plugging hardware, and each group of interfaces is configured with a corresponding analog-to-digital conversion module and an address allocation module;

the main board is configured to send a group of voltage signals to the analog-to-digital conversion module corresponding to the interface when communication connection is established between the main board and the back board; the voltage signals received by the analog-to-digital conversion modules are different;

the analog-to-digital conversion module is configured to convert different voltage signals into corresponding different digital signals;

the address assignment module is configured to match addresses for corresponding interfaces according to the digital signals.

In combination with the first aspect, the main board is further configured with a voltage dividing module, and the voltage dividing module includes voltage dividing resistors corresponding to each set of interfaces, and the voltage dividing module is used for realizing the output of different voltage signals by adjusting the output resistance of each voltage dividing resistor.

With reference to the first aspect, further, the address allocation module includes a GPIO (General-purpose input/output) extender, where the GPIO extender configures an address for a corresponding interface according to a digital signal output by the analog-to-digital conversion module.

With reference to the first aspect, further, the GPIO expander and the corresponding analog-to-digital conversion module are integrated on the same integrated circuit functional chip, and the integrated circuit functional chip configures addresses for the corresponding interfaces according to different voltage signals.

With reference to the first aspect, further, the main board is in communication connection with the GPIO expander to scan and acquire addresses of the interfaces; the GPIO expander is further configured to convert the hardware control signal sent by the main board into a parallel port GPIO control signal so as to realize control of hardware plugged in each interface.

With reference to the first aspect, further, the main board is connected with the GPIO expander through VPP (Virtual Pin Port) signals, IIC (Inter-Integrated Circuit, integrated circuit bus) signals or SMBUS (System Management Bus ) signals in communication.

With reference to the first aspect, further, the main board and the back board are in communication connection through a high-speed connector.

With reference to the first aspect, further, the high-speed connector and the interface support PCIe (peripheral component interconnect express, peripheral component expansion bus standard);

and the interfaces of the main board and the backboard establish corresponding PCIe communication connection through a plurality of high-speed connectors.

With reference to the first aspect, further, the high-speed connector includes Slimline, oculink or Mini-SAS HD.

With reference to the first aspect, further, the computer backboard interface address matching system according to any one of the above, wherein the backboard interface includes a hard disk interface for plugging an NVMe hard disk.

In a second aspect, the present application further provides a computer backboard interface address matching method:

when the main board and the backboard are in communication connection, a group of voltage signals are sent to the backboard;

and converting the voltage signal into a digital signal, and matching an address for the interface according to the digital signal.

Compared with the prior art, the application sends the voltage signal to the backboard through the main board, the analog-to-digital conversion module corresponding to each interface converts the voltage signal into the digital signal, and the address distribution module also matches the address for the corresponding interface according to the digital signal, so that the identification of the interface on the backboard by the main board can be realized no matter the main board is in communication connection with the backboard through any connection relation, and the flexibility of backboard cable installation is improved; the cost of arranging the divider resistor on the main board is low, different signal voltages are generated by the main board, and the voltage signals are transmitted by the cable between the main board and the backboard, so that the popularization cost is reduced.

Drawings

FIG. 1 is a schematic diagram showing a communication connection between a processor on a motherboard and a backplane via three high-speed connectors according to an embodiment of the present application;

fig. 2 is a schematic diagram of setting a digital pin level value of a GPIO expander by an analog-to-digital conversion ADC chip and connecting the GPIO expander with a processor when the high-speed connector a in fig. 1 is connected with a corresponding back board interface in a communication manner;

fig. 3 is a flowchart of a computer backboard interface address matching method according to a third embodiment of the present application.

Description of the embodiments

The following detailed description of the technical solutions of the present application will be given by way of the accompanying drawings and specific embodiments, and it should be understood that the specific features of the embodiments and embodiments of the present application are detailed descriptions of the technical solutions of the present application, and not limiting the technical solutions of the present application, and that the embodiments and technical features of the embodiments of the present application may be combined with each other without conflict.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Embodiment one:

the embodiment provides a computer backboard interface address matching system which can be applied to a server, so as to solve the problem that hardware on an interface cannot be identified after the connection relation between a mainboard and a backboard is changed in the prior art. As an embodiment of the present application, the motherboard and the back board may be connected by cable communication, and for convenience of description, the present embodiment uses three sets of interfaces for hardware socket connection on the back board as an example to describe the technical solution provided by the present application in detail.

Referring to fig. 1, the present embodiment shows a connection situation between a motherboard and a back board with a hard disk interface, in order to meet the requirement of large bandwidth communication transmission between the motherboard and the back board, the motherboard and the back board are connected by a high-speed connector, and the high-speed connector and the interface on the back board support PCIe commonly used in industry, and PCIe ports of a processor mounted on the motherboard and the back board establish corresponding PCIe communication connection through the high-speed connector; in addition, the user can select different types of high-speed connectors according to the use condition, including Slimline, oculink or Mini-SAS HD. In the embodiment of the application, the PCIe port can be matched with the corresponding backboard interface only by selecting one signal wire of the existing high-speed connector, and the function of defining pins by the original high-speed connector specification is almost reserved.

Referring to fig. 1, three groups of hard disk interfaces on the back plate are respectively configured with an analog-to-digital conversion module and an address allocation module. When the high-speed connector connected with the main board is connected to the back board, when the main board and the back board are in communication connection, the main board sends a group of voltage signals to the analog-to-digital conversion modules corresponding to each group of hard disk interfaces through the high-speed connector, and the voltage signals corresponding to the three groups of hard disk interfaces are different, for example: in this embodiment, the motherboard sets voltage signals with three voltage values of 0.1V/0.2V/0.3V for the side of the motherboard of the A, B, C three high-speed connectors corresponding to the three PCIe ports PCIe0/PCIe1/PCIe2, and the three voltage signals are transmitted to the analog-to-digital conversion modules corresponding to the three groups of hard disk interfaces of the back board through the high-speed connectors. The corresponding analog-digital conversion modules of the three groups of hard disk interfaces carry out digital conversion on the received voltage signals to generate corresponding bit signals; the three groups of hard disk interfaces are correspondingly provided with respective address allocation modules, and receive digital signals output by the corresponding Analog-to-digital conversion modules, and the corresponding digital signals are different due to different voltage signals, so that addresses can be configured for the hard disk interfaces according to different digital signals, and the relationships of the processor PCIe ports, ADC (Analog-to-Digital Converter) input voltages, ADC output bit signals and address allocation module configuration addresses are defined in the embodiment as shown in the following table:

processor PCIe port	ADC input voltage	ADC outputs bit signals	Configuring addresses
				PCIe0	0.1V	000	0x40
PCIe1	0.2V	001	0x42
				PCIe2	0.3V	010	0x44

The analog-digital conversion module converts the input voltage of 0.1V/0.2V/0.3V into digital signals of 000/001/010 respectively, and the address distribution module configures corresponding addresses of 0x40/0x42/0x44 according to the difference of the three groups of digital signals.

The address distribution module can select a GPIO expander, an A0/A1/A2 digital pin of the GPIO expander is in communication connection with an analog-to-digital conversion ADC chip, the analog-to-digital conversion ADC chip sets level values for the A0/A1/A2 digital pin at the same time, the three digital pins are arranged in different numbers, wherein a high level represents 1, a low level represents 0, digital signals are transmitted to the GPIO expander, and the GPIO expander configures addresses for corresponding hard disk interfaces according to the level values of the digital pins; in this embodiment, the corresponding relation among the PCIe port of the processor, the ADC input voltage, the ADC output bit signal, the pin level of the GPIO expander, and the configuration address may refer to the following table;

processor PCIe port	ADC input voltage	ADC outputs bit signals	GPIO expander pin level	Configuring addresses
					PCIe0	0.1V	000	A2=0,A1=0,A0=0	0x40
PCIe1	0.2V	001	A2=0,A1=0,A0=1	0x42
					PCIe2	0.3V	010	A2=0,A1=1,A0=0	0x44

Referring to fig. 2, in order to realize control of the hard disk, the GPIO expander is further in communication connection with the motherboard, and after the GPIO expander completes setting of the address, the processor on the motherboard scans the configuration address of the GPIO expander corresponding to each interface on the backplane, so as to realize obtaining the address of the hard disk on each interface, and the processor determines the position of the hard disk through the address of the hard disk on each interface; after determining the positions of the hard disks on the interfaces, the processor establishes PCIe signal connection with the hard disks through the hard disk interfaces to transmit data, and in addition, the processor also sends hard disk control signals to the GPIO expander, and the GPIO expander converts the hard disk control signals into parallel port GPIO control signals so as to realize control of the hard disks; for example, when the hard disk inserted into the interface is an NVMe hard disk, control of the hot plug signal of the NVMe hard disk and control of the NVMe hard disk status indicator lamp can be realized.

In this embodiment, the processor on the motherboard is connected to the GPIO expander through a serial VPP signal, or may be connected through an IIC signal or an SMBUS signal.

Referring to fig. 2, in this embodiment, the voltage signal may be generated by a voltage dividing module disposed on the motherboard, the voltage dividing module corresponds to voltage dividing resistors R1 and R2 disposed on each set of interfaces, the resistor R1 is connected in series to a line connected to a power supply, the resistor R2 is connected in series to a grounded line, and the output resistor of each voltage dividing resistor is adjusted to realize the output of different voltage signals on the motherboard side of the high-speed connector a.

The corresponding relation among the PCIe port of the processor, the ADC input voltage, the ADC output bit signal, the pin level of the GPIO expander, and the configuration address mentioned in the embodiment is only used to explain the technical solution of the embodiment, and when implementing the present application, a person skilled in the art will generate the corresponding relation among the PCIe port of the processor, the ADC input voltage, the ADC output bit signal, the pin level of the GPIO expander, and the configuration address according to the actual situation.

The connection condition between the main board and the hard disk backboard with three hard disk interfaces demonstrated by the embodiment is only common scene simulation for the operation of the server, and the hard disk interfaces can also be other hardware interfaces including a display card, a sound card and a network card; the number of interfaces can be set according to practical situations, for example, when the hardware interface is an NVMe hard disk interface, the server can be 8-disc, 12-disc or 24-disc; and will not be described in detail in view of the same technical content.

The NVMe hard disk status indicator lamp mentioned in this embodiment may indicate that it includes: bit state, read-write state, failure state.

Meanwhile, the component for PCIe communication connection with the back board may be, besides a processor, other functional components mounted on the motherboard, such as an on-board display card.

In addition, the mainstream server motherboard now uses pcie×8 link-width high-speed connectors, and 1 block of NVMe hard disk uses pcie×4 signals, so referring to fig. 2, one hard disk interface may be connected to 2 blocks of NVMe hard disk in this embodiment.

The processor mentioned in this embodiment may be a memory array card, or may be a chip of other PCIe resources.

The digital signal may be 2 bits, 3 bits, 4 bits or more.

The analog-to-digital conversion ADC chip can also identify the voltage signal by identifying the level value in the cable.

In the prior art, a plurality of paths of ADDR (Address) signals are used for transmitting Address matching information, but in the specification of a high-speed connector, all signal pins have signal definition and use, and the use of a plurality of ADDR signals occupies corresponding signal positions in the high-speed connector, so that the use of other functions is influenced; the computer backboard interface address matching system provided by the application can automatically match addresses for all interfaces on the backboard according to the insertion of the high-speed connector cable when the mainboard is in communication connection with the backboard, solves the problem that the fixing collocation of connectors on the mainboard side and the backboard side of the high-speed connector is limited, solves the functional defect of a server caused by manual assembly errors, improves the universality of the backboard, and simultaneously only needs the transmission of voltage signals by the existing wires in the cable, so that the normal use of other functions is not influenced.

Embodiment two:

the embodiment provides a computer backboard interface address matching system, which is further improved based on the first embodiment, a GPIO expander and a corresponding analog-to-digital conversion module are integrated on the same integrated circuit functional chip, and the integrated circuit functional chip configures addresses for corresponding interfaces according to different voltage signals; the other technical contents are the same as those of the first embodiment, and are not described herein.

According to the computer backboard interface address matching system provided by the embodiment, the GPIO expander and the corresponding analog-to-digital conversion module are integrated on the same integrated circuit functional chip, so that the area of the occupied backboard PCB (Printed Circuit Board ) is reduced, and meanwhile, the GPIO expander and the corresponding analog-to-digital conversion module are integrated on the same chip, so that the wafer area required by photoetching is saved, and the manufacturing cost of the chip is reduced.

Embodiment III:

the present embodiment provides a computer backplane interface address matching method of the computer backplane interface address matching system provided in the first embodiment or the second embodiment, referring to fig. 3, including:

and converting the voltage signal into a digital signal, and matching the address for the interface according to the digital signal.

After the address matching of the interfaces is completed, the processor on the main board registers the addresses of the interfaces, sends corresponding control signals to the interfaces according to the addresses of the interfaces, and establishes communication connection with hardware on the interfaces.

Compared with the traditional technology that multiple paths of ADDR are used for transmitting address matching information, the method for matching the address of the computer back panel interface provided by the embodiment utilizes the voltage signals to transmit the address information between the main board and the back panel, converts the voltage signals into digital signals, and uses the digital signals as the interface matching address, so that occupation of other signal positions is avoided, and influence on other signal transmission is reduced.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The foregoing is merely a preferred embodiment of the present application, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present application, and such modifications and variations should also be regarded as being within the scope of the application.

Claims

1. The computer backboard interface address matching system comprises a main board and a backboard, wherein the backboard is provided with a plurality of groups of interfaces for plugging hardware, and the computer backboard interface address matching system is characterized in that the backboard is provided with a corresponding analog-to-digital conversion module and an address distribution module corresponding to each group of interfaces;

2. The computer backplane interface address matching system of claim 1, wherein: the main board is provided with a voltage dividing module, the voltage dividing module comprises voltage dividing resistors arranged corresponding to each group of interfaces, and different voltage signals are output by adjusting the output resistance of each voltage dividing resistor.

3. The computer backplane interface address matching system of claim 1, wherein: the address distribution module comprises a GPIO expander, and the GPIO expander configures addresses for corresponding interfaces according to the digital signals output by the analog-to-digital conversion module.

4. The computer backplane interface address matching system of claim 3, wherein: the GPIO expander and the corresponding analog-to-digital conversion module are integrated on the same integrated circuit functional chip.

5. The computer backplane interface address matching system of claim 3, wherein: the main board is in communication connection with the GPIO expander so as to scan and acquire the address of each interface; the GPIO expander is further configured to convert the hardware control signal sent by the main board into a parallel port GPIO control signal so as to realize control of hardware plugged in each interface.

6. The computer backplane interface address matching system of claim 5, wherein: the main board is in communication connection with the GPIO expander through a VPP signal, an IIC signal or an SMBUS signal.

7. The computer backplane interface address matching system of claim 1, wherein: the main board is in communication connection with the back board through a high-speed connector.

8. The computer backplane interface address matching system of claim 7, wherein: the high speed connector and the interface support PCIe;

9. The computer backplane interface address matching system of any one of claims 1 to 8, wherein: the interface of the backboard comprises a hard disk interface for plugging an NVMe hard disk.

10. A computer backboard interface address matching method is characterized in that: