CN111416026A - Vertical structure L ED chip with double-sided transparent electrode and preparation method thereof - Google Patents
Vertical structure L ED chip with double-sided transparent electrode and preparation method thereof Download PDFInfo
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- CN111416026A CN111416026A CN202010250436.1A CN202010250436A CN111416026A CN 111416026 A CN111416026 A CN 111416026A CN 202010250436 A CN202010250436 A CN 202010250436A CN 111416026 A CN111416026 A CN 111416026A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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Abstract
The invention discloses a L ED chip with a vertical structure of a double-sided transparent electrode and a preparation method thereof, wherein the structure sequentially comprises a supporting conductive substrate, a bonding metal layer, a protective metal layer, a reflective metal layer, a p-sided transparent electrode, an epitaxial layer, a passivation insulating layer and an n-sided transparent electrode from bottom to top, wherein the passivation insulating layer is arranged on the periphery of the epitaxial layer and forms a first groove with the top of the epitaxial layer, and the bottom of the n-sided transparent electrode is provided with a protrusion matched with the first groove.
Description
Technical Field
The invention relates to the technical field of L ED chip manufacturing, in particular to a L ED chip with a vertical structure and double-sided transparent electrodes and a preparation method thereof.
Background
The light Emitting Diode (L light Emitting Diode, L ED) is a device which converts electric energy into light energy by a PN junction, has the advantages of good controllability, fast start, long service life, high light Emitting efficiency, safety, energy saving, environmental protection and the like, not only drives the deep revolution of the lighting industry, but also leads to the innovation of the field of display screens.
With the development of L ED industry, high-power L ED is more and more favored by people, among high-power L ED, a vertical structure L ED chip is favored by various markets due to its good direction of passing large current and emitting light, and a vertical structure L ED chip technology is also developed by various large L ED chip factories, however, at present, a vertical structure L ED chip is not good for ohmic contact and unstable voltage because a p-surface electrode is a pure Ag electrode and has high reflectivity, and in addition, an n-surface electrode is a local linear metal, so that current expansion is not good, and light absorption and blocking are not good.
Disclosure of Invention
In view of this, the invention provides a vertical structure L ED chip with a double-sided transparent electrode and a method for manufacturing the same, which can solve the technical problems of unstable voltage and poor current spreading of the conventional vertical structure L ED chip.
The technical scheme of the invention is realized as follows:
the utility model provides a vertical structure L ED chip of two-sided transparent electrode, is including supporting conductive substrate, bonded metal layer, protective metal layer, reflection metal layer, p face transparent electrode, epitaxial layer, passivation insulating layer and n face transparent electrode, the bonded metal layer is installed support conductive substrate is last, the protective metal layer is installed on the bonded metal layer, the reflection metal layer is installed on the protective metal layer, p face transparent electrode is installed on the reflection metal layer, the epitaxial layer is installed on the p face transparent electrode, the passivation insulating layer sets up the periphery of epitaxial layer, and with the epitaxial layer top forms first recess, n face transparent electrode bottom be provided with first recess assorted arch.
As a further alternative to the double-sided transparent electrode vertical structure L ED chip, the n-sided transparent electrode is provided with a second groove on top.
As a further alternative to the double-sided transparent electrode vertical structure L ED chip, the passivation insulating layer includes a pillar insulating layer disposed at the periphery of the epitaxial layer and a pillar insulating layer disposed at the top of the epitaxial layer.
As a further alternative of the vertical structure L ED chip of the double-sided transparent electrode, the p-side transparent electrode is made of any one transparent conductive material of graphene, ITO, ZnO and Ga2O3, and the thickness of the p-side transparent electrode is 5nm-10000 nm.
As a further alternative of the vertical structure L ED chip of the double-sided transparent electrode, the n-sided transparent electrode is made of any one transparent conductive material of graphene, ITO, ZnO and Ga2O3, and the thickness of the n-sided transparent electrode is 5nm-10000 nm.
As a further alternative of the vertical structure L ED chip of the double-sided transparent electrode, the protective metal layer is a multi-metal lamination of Ti, TiW, Pt, Ni, Cr and Au, and the thickness of the protective metal layer is 100nm-5000 nm.
As a further alternative of the double-sided transparent electrode vertical structure L ED chip, the bonding metal layer is any one of a stack and eutectic alloy of Ni and Sn, Ag and Sn, Au, and the thickness of the bonding metal layer is 100nm-5000 nm.
As a further alternative of the double-sided transparent electrode vertical structure L ED chip, the passivation insulating layer is made of any one of SiO2, SiN and polyimide, and the thickness of the passivation insulating layer is 50nm-10000 nm.
As a further alternative of the double-sided transparent electrode vertical structure L ED chip, the supporting conductive substrate is made of any one of monocrystalline silicon, monocrystalline germanium, polycrystalline silicon, polycrystalline germanium, Cu, W and Al, and the thickness of the supporting conductive substrate is 50-400 um.
As a further alternative of the double-sided transparent electrode vertical structure L ED chip, the reflective metal layer is any one of a NiAg stack and Al metal, and the epitaxial layer is a light-emitting GaN layer grown on a silicon-based or sapphire or SiC substrate.
A method for preparing a double-sided transparent electrode vertical structure L ED chip, the method comprising the steps of:
step S1, growing an epitaxial layer on the silicon substrate to form a L ED epitaxial wafer;
step S2, growing a p-surface transparent electrode on the L ED epitaxial wafer;
step S3, covering a reflecting metal layer on the p-surface transparent electrode and the epitaxial layer;
step S4, covering a protective metal layer and a bonding metal layer on the whole surface of the reflection metal layer;
step S5, fabricating a bonding metal layer on the supporting conductive substrate;
step S6, bonding the samples obtained in the step S4 and the step S5;
step S7, removing the substrate of the epitaxial layer;
step S8, carrying out rough treatment on the epitaxial layer;
step S9, making a square or rectangular chip pattern from the roughly processed sample, and then making a pattern required by a user;
step S10, forming a passivation insulating material by using CVD or evaporation or photoetching method, and forming a square or rectangle which corresponds to the shape of the chip and is smaller than the step S9 by using photoetching and etching methods, so that the passivation insulating material covers the side section of the chip to form a passivation insulating layer;
step S11, growing an n-face transparent electrode on the epitaxial layer and the passivation insulating layer;
and step S12, cutting and scribing to form a single double-sided transparent electrode L ED chip, and completing preparation.
The LED chip with the double-sided transparent electrode has the beneficial effects that the L ED chip with the double-sided transparent electrode has stable ohmic contact due to the transparent electrode adopted as the p-side electrode, so that the voltage of the product is stable, the light transmittance is good, the problem of unstable voltage of the traditional vertical structure L ED chip is solved, in addition, the transparent electrode also adopted as the n-side electrode can greatly improve current expansion, avoid the problems of light absorption and light blocking of the n-side electrode, further improve the brightness, reduce heat emission under large current, improve the light efficiency and solve the problem of poor current expansion of the traditional vertical structure L ED chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a vertical structure L ED chip with double-sided transparent electrodes according to the present invention;
FIG. 2 is a schematic diagram of the assembly of the passivation insulating layer and the epitaxial layer in the vertical structure L ED chip with double-sided transparent electrodes according to the present invention;
FIG. 3 is a schematic diagram of a passivation insulating layer in a vertical structure L ED chip with double-sided transparent electrodes according to the present invention;
FIG. 4 is a schematic diagram of the composition of an n-side transparent electrode in a double-sided transparent electrode vertical structure L ED chip according to the present invention;
FIG. 5 is a flow chart of a method for manufacturing a vertical structure L ED chip with double-sided transparent electrodes according to the present invention;
description of reference numerals: 1. supporting a conductive substrate; 2. bonding the metal layer; 3. a protective metal layer; 4. a reflective metal layer; 5. a p-side transparent electrode; 6. an epitaxial layer; 7. passivating the insulating layer; 8. an n-face transparent electrode; 9. a first groove; 701. an upright column insulating layer; 702. a cross-pillar insulating layer; 801. a protrusion; 802. a second groove.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-5, a L ED chip with a vertical structure of a double-sided transparent electrode includes a supporting conductive substrate 1, a bonding metal layer 2, a protective metal layer 3, a reflective metal layer 4, a p-sided transparent electrode 5, an epitaxial layer 6, a passivation insulating layer 7, and an n-sided transparent electrode 8, where the bonding metal layer 2 is mounted on the supporting conductive substrate 1, the protective metal layer 3 is mounted on the bonding metal layer 2, the reflective metal layer 4 is mounted on the protective metal layer 3, the p-sided transparent electrode 5 is mounted on the reflective metal layer 4, the epitaxial layer 6 is mounted on the p-sided transparent electrode 5, the passivation insulating layer 7 is disposed on the periphery of the epitaxial layer 6 and forms a first groove 9 with the top of the epitaxial layer 6, and a protrusion 801 matched with the first groove 9 is disposed at the bottom of the n-sided transparent electrode 8.
In addition, because the n-face electrode also adopts the transparent electrode, the current expansion can be greatly improved, the problem of light absorption and light blocking of the n-electrode can be avoided, the brightness is further improved, the heat emission under large current is reduced, the light effect is improved, and the problem of poor current expansion of the traditional vertical structure L ED chip is solved;
preferably, the top of the n-side transparent electrode 8 is provided with a second groove 802.
Preferably, the passivation insulating layer 7 includes a pillar insulating layer 701 disposed on the periphery of the epitaxial layer 6 and a pillar insulating layer 702 disposed on the top of the epitaxial layer 6.
Preferably, the p-surface transparent electrode 5 is made of any one transparent conductive material of graphene, ITO, ZnO and Ga2O3, and the thickness of the p-surface transparent electrode 5 is 5nm-10000 nm; it should be noted that the p-side transparent electrode 5 may also be made of other transparent conductive materials.
Preferably, the n-face transparent electrode 8 is made of any one transparent conductive material of graphene, ITO, ZnO and Ga2O3, and the thickness of the n-face transparent electrode 8 is 5nm-10000 nm; it should be noted that the n-side transparent electrode 8 may also be made of other transparent conductive materials.
Preferably, the protective metal layer 3 is a multi-metal stack of Ti, TiW, Pt, Ni, Cr and Au, and the thickness of the protective metal layer 3 is 100nm to 5000 nm.
Preferably, the bonding metal layer 2 is any one of a stack of Ni and Sn, Ag and Sn, Au, and eutectic alloy, and the thickness of the bonding metal layer 2 is 100nm to 5000 nm.
In this embodiment, the bonding metal layer 2 may use Ni and Sn as a preparation material, Ag and Sn as a preparation material, Au and Sn as a preparation material, a stacked layer of Au as a preparation material, or a eutectic alloy as a preparation material.
Preferably, the passivation insulating layer 7 is made of any one insulating material of SiO2, SiN and polyimide, and the thickness of the passivation insulating layer 7 is 50nm-10000 nm; it should be noted that other insulating materials can also be used as the preparation material for the passivation insulating layer 7.
Preferably, the supporting conductive substrate 1 is made of any one of monocrystalline silicon, monocrystalline germanium, polycrystalline silicon, polycrystalline germanium, Cu, W and Al, and the thickness of the supporting conductive substrate 1 is 50um-400 um; it is to be noted that the single crystal silicon, single crystal germanium, polycrystalline silicon, and polycrystalline germanium must be highly conductive.
Preferably, the reflective metal layer 4 is any one of a NiAg stack layer and an Al metal, and the epitaxial layer 6 is a light-emitting GaN layer grown on a silicon-based or sapphire or SiC substrate; it should be noted that other metals with high reflectivity and good ohmic contact can be used for the reflective metal layer 4.
A method for preparing a double-sided transparent electrode vertical structure L ED chip, the method comprising the steps of:
step S1, growing an epitaxial layer 6 on a substrate of silicon, sapphire, SiC or the like by using MOCVD to form a L ED epitaxial wafer;
step S2, growing a p-surface transparent electrode 5 on the L ED epitaxial wafer by using a CVD or PVD or evaporation or spin coating mode;
step S3, covering a reflecting metal layer 4 on the p-surface transparent electrode 5 and the epitaxial layer 6 in an electron beam evaporation or PVD mode;
step S4, covering the whole surface of the reflecting metal layer 4 with a protective metal layer 3 and a bonding metal layer 2 by using an electron beam evaporation or PVD method;
step S5, manufacturing a bonding metal layer on the supporting conductive substrate 1 by using an electron beam evaporation or PVD method;
step S6, bonding the samples obtained in step S4 and step S5;
step S7, removing the substrate of the epitaxial layer 6 by grinding, chemical etching or plasma etching or laser stripping;
step S8, roughening the epitaxial layer 6 by chemical liquid reduction or acid solution or graphical etching method to facilitate light emergence;
step S9, using photoetching method to make square or rectangle chip pattern, then using hot acid solution or using inductance coupling plasma etching method to make needed pattern;
step S10, forming a passivation insulating material by using CVD or evaporation or photoetching method, and forming a square or rectangle corresponding to the shape of the chip but smaller than (9) by using photoetching and etching method, so that the passivation insulating material covers the side section of the chip to form a passivation insulating layer 7;
step S11, growing an n-face transparent electrode 8 on the epitaxial layer 6 and the passivation insulating layer 7 by CVD or PVD or evaporation or spin coating;
and step S12, testing, cutting and scratching to form a single double-sided transparent electrode L ED chip, and completing preparation.
Example 1 of the preparation method of the vertical structure L ED chip of the double-sided transparent electrode:
(1) growing L ED epitaxial wafers of epitaxial layers of 2um-8um on a Si substrate by using an MOCVD epitaxial technology;
(2) respectively using acetone and isopropanol to carry out organic cleaning for 5min to remove organic dirt;
(3) then using SPM solution to carry out acid cleaning to remove inorganic metal dirt and organic dirt;
(4) flushing and spin-drying, and growing 200nm graphene at 300 ℃ by using CVD equipment;
(5) and (4) evaporating Al metal by electron beam on the whole surface for 200 nm.
(6) Electron beam evaporation of TiPtTiPt (Ti20nm-200nm, Pt20nm-300nm) protective layer and NiSn (Ni100nm-800nm, Sn100nm-2000nm) bonding metal layer
(7) And (3) evaporating a NiSn (Ni100nm-800nm, Sn100nm-2000nm) bonding metal layer on the high-conductivity Si substrate by adopting an electron beam evaporation process.
(8) And (3) bonding the samples manufactured in the steps (10) and (11) by using a bonding machine, and removing the silicon substrate by using grinding and chemical etching methods.
(9) The chip after the silicon substrate is removed is roughened by using hot alkaline solution, the percentage concentration of the KOH aqueous solution is 0.05-10%, and the temperature is 20-100 ℃.
(10) Using photolithography to fabricate L ED patterns (1005 um) with square photoresist covering, and using phosphoric acid to etch the epitaxial layer region without photoresist covering, to form the cutting channels.
(11) Growing SiO2 with the thickness of 600nm by using PECVD equipment;
(12) etching out a hollow pattern 995 um-995 um which is matched with the L ED pattern but is smaller than 10um by using a photoetching technology, etching off SiO2 corresponding to the pattern by using a BOE solution, removing photoresist and drying;
(13) and growing 1000nm graphene by using a CVD (chemical vapor deposition) device.
(14) And cutting a channel by using laser, splitting by using a splitter, expanding a film to form a single L ED chip, and manufacturing the L ED chip of the double-sided transparent electrode by the above process.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (11)
1. The utility model provides a vertical structure L ED chip of two-sided transparent electrode, its characterized in that, is including supporting conductive substrate (1), bonding metal layer (2), protective metal layer (3), reflection metal layer (4), p face transparent electrode (5), epitaxial layer (6), passivation insulating layer (7) and n face transparent electrode (8), bonding metal layer (2) are installed support conductive substrate is last (1), protective metal layer (3) are installed on bonding metal layer (2), reflection metal layer (4) are installed on protective metal layer (3), p face transparent electrode (5) are installed on reflection metal layer (4), epitaxial layer (6) are installed on p face transparent electrode (5), passivation insulating layer (7) set up the periphery of epitaxial layer (6), and with epitaxial layer (6) top forms first recess (9), n face transparent electrode (8) bottom is provided with first recess (9) assorted arch (801).
2. The double-sided transparent electrode vertical structure L ED chip of claim 1, wherein the n-sided transparent electrode (8) is provided with a second groove (802) on top.
3. The double-sided transparent electrode vertical structure L ED chip of claim 2, wherein the passivation insulating layer (7) comprises a pillar insulating layer (701) disposed on the periphery of the epitaxial layer (6) and a pillar insulating layer (702) disposed on top of the epitaxial layer (6).
4. The L ED chip with the double-sided transparent electrode vertical structure is characterized in that the p-sided transparent electrode (5) is made of any one transparent conductive material of graphene, ITO, ZnO and Ga2O3, and the thickness of the p-sided transparent electrode (5) is 5nm-10000 nm.
5. The L ED chip with the double-sided transparent electrode vertical structure is characterized in that the n-sided transparent electrode (8) is made of any one transparent conductive material of graphene, ITO, ZnO and Ga2O3, and the thickness of the n-sided transparent electrode (8) is 5nm-10000 nm.
6. The double-sided transparent electrode vertical structure L ED chip of claim 5, wherein the protection metal layer (3) is a multi-metal stack of Ti, TiW, Pt, Ni, Cr and Au, and the thickness of the protection metal layer (3) is 100nm-5000 nm.
7. The L ED chip with the double-sided transparent electrode structure is characterized in that the bonding metal layer (2) is any one of a stack and eutectic alloy of Ni and Sn, Ag and Sn, Au, and the thickness of the bonding metal layer (2) is 100nm-5000 nm.
8. The double-sided transparent electrode vertical structure L ED chip of claim 7, wherein the passivation insulating layer (7) is made of any one of SiO2, SiN and polyimide, and the thickness of the passivation insulating layer (7) is 50nm-10000 nm.
9. The double-sided transparent electrode vertical structure L ED chip of claim 8, wherein the supporting conductive substrate (1) is made of any one of single crystal silicon, single crystal germanium, polysilicon, poly-crystal germanium, Cu, W and Al, and the thickness of the supporting conductive substrate (1) is 50-400 um.
10. The double sided transparent electrode vertical structure L ED chip according to claim 9, wherein the reflective metal layer (4) is any one of NiAg stack and Al metal, and the epitaxial layer (6) is a light emitting GaN layer grown on a silicon-based or sapphire or SiC substrate.
11. A method for preparing a vertical structure L ED chip of a double-sided transparent electrode is characterized by comprising the following steps:
step S1, growing an epitaxial layer (6) on the silicon substrate to form a L ED epitaxial wafer;
step S2, growing a p-surface transparent electrode (5) on the L ED epitaxial wafer;
step S3, covering a reflective metal layer on the whole surface of the p-surface transparent electrode (5) and the epitaxial layer (6);
step S4, covering the whole surface of the reflective metal layer (4) with a protective metal layer (3) and a bonding metal layer (2);
step S5, manufacturing a bonding metal layer (2) on a supporting conductive substrate (1);
step S6, bonding the samples obtained in the step S4 and the step S5;
step S7, removing the substrate of the epitaxial layer (6);
step S8, carrying out rough treatment on the epitaxial layer (6);
step S9, making a square or rectangular chip pattern from the roughly processed sample, and then making a pattern required by a user;
step S10, forming a passivation insulating material by using CVD or evaporation or photoetching method, and forming a square or rectangle which corresponds to the shape of the chip and is smaller than the step S9 by using photoetching and etching method, so that the passivation insulating material covers the side section of the chip to form a passivation insulating layer (7);
step S11, growing an n-face transparent electrode (8) on the epitaxial layer (6) and the passivation insulating layer (7);
and step S12, cutting and scribing to form a single double-sided transparent electrode L ED chip, and completing preparation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010250436.1A CN111416026A (en) | 2020-04-01 | 2020-04-01 | Vertical structure L ED chip with double-sided transparent electrode and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010250436.1A CN111416026A (en) | 2020-04-01 | 2020-04-01 | Vertical structure L ED chip with double-sided transparent electrode and preparation method thereof |
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Application publication date: 20200714 |