CN111403519A - Self-packaging laminated photoelectric device and preparation method thereof - Google Patents
Self-packaging laminated photoelectric device and preparation method thereof Download PDFInfo
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- H01L31/042—PV modules or arrays of single PV cells
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Abstract
The application relates to the field of laminated photoelectric devices, in particular to a self-packaging laminated photoelectric device which comprises buried gate glass, a perovskite top battery, a silicon-based battery and a packaging layer; the perovskite cell is deposited on the buried gate glass with the top electrode; the perovskite battery is connected with silicon-based batteries with different structures in series and then packaged to form a laminated photoelectric device; the preparation method comprises the steps of respectively manufacturing the perovskite battery and the silicon-based battery; connecting the silicon-based battery with the perovskite battery through a front electrode of the silicon-based battery; compared with the existing laminated photoelectric device, the invention independently prepares two batteries, and the two batteries are connected in series through the metal electrode, thereby avoiding the influence of the top battery, the silicon-based battery interface and the texture appearance, and simplifying the structure and the preparation method.
Description
Technical Field
The application relates to the technical field of laminated photoelectric devices, in particular to a self-packaging laminated photoelectric device and a preparation method thereof.
Background
Solar energy is a renewable energy source with large reserves, cleanness and high efficiency, and a solar power generation technology is one of important technologies for solving the energy problem. The perovskite solar cell is a current research hotspot due to the advantages of low cost, simple preparation, high photoelectric conversion efficiency and the like. The silicon solar cell has made a great research progress due to its characteristics of low temperature of the manufacturing process, simple process flow, high open-circuit voltage, high conversion efficiency, low temperature coefficient, excellent high-temperature/weak light power generation characteristics and low attenuation.
The solar spectrum has a wide energy distribution, and a solar cell device can only absorb a part of energy, while the rest of energy cannot be utilized and is released in the form of heat energy, so that the photoelectric conversion efficiency of a unijunction solar cell is low. Because the perovskite material of the perovskite cell has high forbidden bandwidth and the silicon has narrow forbidden bandwidth, the perovskite cell is used as a first light absorption layer, so that the perovskite cell absorbs short-wave light, such as purple light, and long-wave light penetrates through the perovskite layer and is absorbed by the silicon-based cell at the bottom layer, such as red light, so that solar energy can be converted into electric energy to the maximum extent, and the conversion efficiency of the solar cell is improved.
The scheme of combining the perovskite cell and the silicon-based cell can effectively improve the photoelectric conversion efficiency theoretically. The current laminated photoelectric device adopts a perovskite battery prepared on a silicon-based battery, and because the surface of the silicon-based battery is provided with an uneven suede, if the perovskite battery is directly prepared on the surface of the silicon-based battery, firstly, each layer of the perovskite battery cannot be made very flat, and even a perovskite layer can be damaged, so that the short-circuit current loss is serious, and the photoelectric conversion efficiency of the laminated device is not improved; secondly, short-circuit currents of the perovskite battery and the silicon-based battery are not matched under the same light receiving area, so that the photoelectric conversion efficiency of the laminated device is not high, and the current matching has a difficulty by adjusting the light receiving area, and the maximization of the photoelectric conversion efficiency cannot be realized compared with the light trapping effect of a suede surface which does not exist in the silicon-based battery if the surface of the silicon-based battery is made into a smooth plane, so that the problem of interface contact between the perovskite battery and the silicon-based battery in the laminated device becomes the most difficult problem of the laminated device; thirdly, the conventional perovskite battery is manufactured by depositing a functional layer on glass and stripping part of the functional layer, so that the joint has poor fitting degree, and common cathode and anode are not beneficial to charge collection.
Therefore, the invention provides a self-packaging laminated photoelectric device and a preparation method thereof, and solves the problems.
Disclosure of Invention
An object of the embodiments of the present application is to provide a self-packaged laminated optoelectronic device and a method for manufacturing the same to solve the above problems.
In a first aspect, an embodiment of the present application provides a self-packaged stacked optoelectronic device, including:
from last buried grid glass, perovskite battery, silica-based battery and the encapsulation layer of connecting extremely down, buried grid glass's inslot sets up the top electrode, set up perovskite battery on the top electrode, silica-based battery passes through silica-based battery's leading electrode and connects perovskite battery, silica-based battery's back electrode with top electrode in the buried grid glass forms the current loop, silica-based battery's back electrode bonds with the encapsulation layer.
Preferably, the silicon-based battery comprises a PERC battery or a heterojunction battery or an N-type PERT battery.
Preferably, the perovskite battery comprises a first transparent conducting layer, a hole transport layer, a perovskite light absorption layer, an electron transport layer and a second transparent conducting layer which are arranged from top to bottom, and the second transparent conducting layer is connected with the front electrode of the silicon-based battery.
Preferably, the perovskite battery comprises a first transparent conducting layer, an electron transmission layer, a perovskite light absorption layer, a hole transmission layer and a second transparent conducting layer which are arranged from top to bottom, and the second transparent conducting layer is connected with the front electrode of the silicon-based battery.
Preferably, the top electrode, the front electrode of the silicon-based battery and the back electrode of the silicon-based battery are made of one or more of aluminum, silver, gold, titanium, bismuth, tin, palladium, nickel, chromium and copper, and the thickness of the top electrode, the front electrode of the silicon-based battery and the back electrode of the silicon-based battery is 1-2000 μm.
Preferably, the top electrode comprises n main grid lines and m auxiliary grid lines which are vertically crossed; n is 1-20; the value range of m is 1-100.
Preferably, the depth range of the top electrode is 1-2000 μm, the length of the main grid line and the auxiliary grid line is equal to that of the buried grid glass, the width range of the main grid line is 10-1000 μm, and the width range of the auxiliary grid line is 10-500 μm.
Preferably, the ratio of the light-shielded area of the front electrode of the silicon-based cell to the light-shielded area of the top electrode of the perovskite cell is in the range of 0.5 to 2.
A preparation method of a self-packaging laminated photoelectric device comprises the following steps:
respectively manufacturing a perovskite battery and a silicon-based battery;
connecting a front electrode of the silicon-based battery with the perovskite battery;
and packaging the connected perovskite battery and the silicon-based battery to obtain the laminated photoelectric device.
Preferably, the manufacturing of the perovskite battery comprises the following steps:
preparing a groove on the buried gate glass, wherein the groove comprises a main groove and an auxiliary groove;
preparing a top electrode in the groove, wherein the top electrode comprises a main grid line and an auxiliary grid line;
sequentially preparing a first transparent conducting layer, a hole transport layer, a perovskite light absorption layer, an electron transport layer and a second transparent conducting layer on the buried gate glass with the top electrode or sequentially preparing the first transparent conducting layer, the electron transport layer, the perovskite light absorption layer, the hole transport layer and the second transparent conducting layer to obtain a perovskite battery;
and connecting the front electrode of the silicon-based battery with the second transparent conducting layer of the perovskite battery.
The application has the following technical effects:
1. the separately manufactured perovskite battery and the silicon-based battery are connected through the metal electrode, the perovskite battery is not in direct contact with the silicon-based battery, the damage of the texture of the silicon-based battery to the perovskite battery is avoided, and the photoelectric conversion efficiency is improved; the perovskite battery and the silicon-based battery which are matched in light receiving area can be selected for use to realize current matching due to the fact that the perovskite battery and the silicon-based battery are separately prepared, so that the problems that the photoelectric conversion efficiency of the laminated photoelectric device is influenced and the current matching of the two batteries is influenced due to the fact that the suede surface of the perovskite battery prepared on the silicon-based battery in the prior art are solved, meanwhile, the perovskite battery and the silicon-based battery which are matched in current are directly superposed and connected in series through the metal electrode, and the structure of the laminated photoelectric device is;
2. the top electrode is prepared by slotting the buried gate glass, the perovskite battery functional layer is conveniently prepared on the top electrode, current is led out, the buried gate glass is favorably attached to the perovskite battery functional layer, and the buried gate top electrode is designed by adopting a main grid line and an auxiliary grid line, so that charges are favorably collected on the surface of the whole device.
3. The separately manufactured perovskite battery and the silicon-based battery are connected through the metal electrode, and current carriers are compounded at the metal electrode, so that the heat loss is effectively reduced;
4. because the perovskite battery and the silicon-based battery are prepared independently, the silicon-based battery and the perovskite battery with different structures can be simply and conveniently superposed according to requirements.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a stacked optoelectronic device according to the present application.
Fig. 2 is a schematic structural diagram of the buried gate glass of the present application.
Fig. 3 is a schematic structural diagram of a stacked optoelectronic device of the present application.
Reference numerals:
101-buried gate glass, 102-top electrode, 103-packaging layer, 110-inverted perovskite cell, 120-silicon-based heterojunction cell, 111-first transparent conducting layer, 112-hole transport layer, 113-perovskite light absorption layer, 114-electron transport layer, 115-second transparent conducting layer, 121-front electrode of silicon-based cell, 122-first transparent conducting oxide layer, 123-p-type hydrogenated amorphous silicon layer, 124-first intrinsic type hydrogenated amorphous silicon layer, 125-n-type silicon substrate, 126-n-type hydrogenated amorphous silicon layer, 127-second intrinsic type hydrogenated amorphous silicon layer, 128-second transparent conducting oxide layer, 129-back electrode of silicon-based cell, 210-positive perovskite cell, 220-PERC cell, 222-antireflection layer, 223-n + emitter, 224-p-type silicon substrate, 225-passivation layer, 226-aluminum back field.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Furthermore, it should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In order to solve the problem that the performance of the perovskite battery is influenced by the uneven texture surface of the silicon-based battery when the perovskite battery is prepared on the silicon-based battery in the existing laminated photoelectric device,
a self-encapsulating laminated optoelectronic device comprising: the solar battery comprises buried gate glass 101, a perovskite battery, a silicon-based battery and an encapsulation layer 103 which are connected from top to bottom, wherein a top electrode 102 is arranged in a groove of the buried gate glass 101, the perovskite battery is prepared on the top electrode 102, the perovskite battery is connected with the silicon-based battery through a front electrode 121 of the silicon-based battery, a back electrode 129 of the silicon-based battery and the top electrode 102 in the buried gate glass 101 form a current loop, and the back electrode 129 of the silicon-based battery is bonded with the encapsulation layer 103.
The separately manufactured perovskite battery and the silicon-based battery are connected through the metal electrode, the perovskite battery is not in direct contact with the silicon-based battery, damage to the perovskite battery caused by the suede of the silicon-based battery is avoided, and the photoelectric conversion efficiency is improved.
Example 1
As shown in fig. 1, a self-encapsulating laminated optoelectronic device comprises: the solar battery comprises buried gate glass 101, a perovskite battery, a silicon-based battery and an encapsulation layer 103 which are connected from top to bottom, wherein a top electrode 102 is arranged in a groove of the buried gate glass 101, the perovskite battery is prepared on the top electrode 102, the perovskite battery is connected with the silicon-based battery through a front electrode 121 of the silicon-based battery, a back electrode 129 of the silicon-based battery and the top electrode 102 in the buried gate glass 101 form a current loop, and the back electrode 129 of the silicon-based battery is bonded with the encapsulation layer 103.
The perovskite battery realizes current conduction through the top electrode 102 in the groove of the buried gate glass 101, the perovskite battery is connected with the silicon-based battery through the front electrode 121 of the silicon-based battery, and the back electrode 129 of the silicon-based battery and the top electrode 102 in the buried gate glass 101 form a current loop of the laminated device.
The perovskite battery adopts an inverted perovskite battery 110, the perovskite battery comprises a first transparent conducting layer 111, a hole transport layer 112, a perovskite light absorption layer 113, an electron transport layer 114 and a second transparent conducting layer 115 which are arranged from top to bottom, and the second transparent conducting layer 115 is connected with a front electrode 121 of the silicon-based battery.
The silicon-based cell adopts a heterojunction cell, such as a silicon-based heterojunction cell 120, which comprises a front electrode 121 of the silicon-based cell, a first transparent oxide conducting layer 122, a p-type hydrogenated amorphous silicon layer 123, a first intrinsic type hydrogenated amorphous silicon layer 124, an n-type silicon substrate 125, a second intrinsic type hydrogenated amorphous silicon layer 127, an n-type hydrogenated amorphous silicon layer 126, a second transparent oxide conducting layer 128 and a back electrode 129 of the silicon-based cell.
The second transparent conducting layer 115 is connected with the front electrode 121 of the silicon-based battery, so that the perovskite battery and the silicon-based battery are connected in series; the silicon-based battery is connected with the packaging layer 103 through a back electrode 129 of the silicon-based battery, and the connection comprises adhesion; the electrode is made of one or more of aluminum, silver, gold, titanium, bismuth, tin, palladium, nickel, chromium and copper, and the thickness of the electrode is 1-2000 mu m; silver is selected for this example.
In this embodiment, the silicon-based battery is connected with the second transparent conductive layer 115 of the perovskite battery through the front electrode 121 of the silicon-based battery, so that the structure of the laminated photoelectric device is simpler, the interface defect caused by direct contact between the perovskite battery and the silicon-based battery is avoided, the separately manufactured perovskite battery and the silicon-based battery are connected through the metal electrode, and the current carrier is compounded at the metal electrode, thereby effectively reducing the heat loss, improving the open-circuit voltage and the filling factor of the battery, further reducing the preparation steps and saving the production cost.
Example 2
The silicon-based battery comprises a PERC battery 220, a heterojunction battery or an N-type PERT battery, the implementation is different from that of the embodiment 1, the silicon-based battery is different from the embodiment 1, as shown in FIG. 3, the embodiment adopts the PERC battery 220, the corresponding perovskite battery adopts an upright perovskite battery 210, the perovskite battery comprises a first transparent conductive layer 111, an electron transport layer 114, a perovskite light absorption layer 113, a hole transport layer 112 and a second transparent conductive layer 115 which are arranged from top to bottom, and the second transparent conductive layer 115 is connected with a front electrode of the silicon-based battery;
the silicon-based battery comprises a front electrode 121 of the silicon-based battery, an antireflection layer 222, an n + emitter 223, a p-type silicon substrate 224, a passivation layer 225 and an aluminum back field 226;
the second transparent conducting layer 115 is connected with the front electrode 121 of the silicon-based battery, so that the perovskite battery and the silicon-based battery are connected in series; the silicon-based battery is connected with the packaging layer 103 through the aluminum back surface field 226; the electrode is made of one or more of aluminum, silver, gold, titanium, bismuth, tin, palladium, nickel, chromium and copper, and the thickness of the electrode is 1-2000 mu m; aluminum is selected for this embodiment.
Example 3
As shown in fig. 1, 2 and 3, this embodiment is different from embodiment 1 or 2 in that a buried gate glass 101 and a perovskite cell are connected through a top electrode 102, the buried gate glass 101 is provided with a trench, a top electrode 102 is arranged in the trench, and the top electrode 102 includes n main gate lines and m sub-gate lines which are vertically intersected.
The depth range of the top electrode 102 is 1-2000 μm, the length of the main grid line and the auxiliary grid line is equal to that of the buried grid glass 101, the width range of the main grid line is 100-1000 μm, and the width range of the auxiliary grid line is 50-500 μm; n is 1 to 20; the value range of m is 1-100.
As shown in fig. 2, the number of the main gate lines is 2 and the number of the sub-gate lines is 8 in this embodiment;
in order to overcome the defects that the functional layer is firstly manufactured and then the cathode and the anode are manufactured, the surface of the functional layer needs to be stripped partially and then the cathode and the anode are connected, so that the contact surface is uneven and the materials are wasted, the top electrode 102 is prepared by slotting the buried grid glass 101, the functional layer of the perovskite battery is conveniently prepared on the buried grid top electrode 102, the current is led out, the buried grid glass 101 is favorably attached to the functional layer of the perovskite battery, the buried grid top electrode 102 adopts a main grid line design and an auxiliary grid line design, the charge collection on the surface of the whole device is favorably realized, and the photoelectric conversion efficiency is further improved. On the buried gate glass 101 with the top electrode 102 manufactured, spin coating or spray coating a solution corresponding to the perovskite battery on the buried gate glass 101, wherein the perovskite battery is naturally attached to the top electrode 102; considering the light receiving area, the light receiving area needs to be ensured, so the number of the main grid lines and the auxiliary grid lines needs to be limited.
Example 4
The difference between this embodiment and embodiment 1 or 2 or 3 is that the ratio of the light shielding area of the front electrode 121 of the silicon-based battery to the light shielding area of the top electrode 102 of the perovskite battery is limited in proportion, the short-circuit current of the perovskite battery and the short-circuit current of the silicon-based battery under the same light receiving area are not matched, specifically because of the properties of the perovskite device and the silicon-based device, the short-circuit current of the perovskite device is lower than that of the silicon-based battery when the perovskite device and the silicon-based device are tested under the same area and under the same light irradiation, for example, the current of the perovskite is 24mA/cm2, and that of the silicon-based battery can reach 38mA/cm2, electrically, the two power supplies are connected in series, and the current value depends on a. If the perovskite battery is made into a laminated device, the perovskite battery can absorb some light, the light received by the silicon-based battery is reduced, and the short-circuit current is low; therefore, in order to match the two currents, the light shielding area of the front electrode 121 of the silicon-based battery may be adjusted until the current is consistent with the short-circuit current of the perovskite, for example, the ratio of the light shielding area of the front electrode 121 of the silicon-based battery to the light shielding area of the top electrode 102 of the perovskite battery is 0.5 or 2 or 1.5; the currents of the two batteries can be matched according to the above ratio.
Based on the laminated photoelectric device, the application provides a preparation method of the laminated photoelectric device, which comprises the following steps:
a preparation method of a self-packaging laminated photoelectric device comprises the following steps:
respectively manufacturing a perovskite battery and a silicon-based battery;
connecting the silicon-based battery with the perovskite battery through a front electrode 121 of the silicon-based battery;
and packaging the connected perovskite battery and the silicon-based battery to obtain the laminated photoelectric device.
The perovskite battery manufacturing method comprises the following steps:
preparing a groove on the buried gate glass 101, wherein the groove comprises a main groove and an auxiliary groove;
preparing a top electrode 102 in the trench, wherein the top electrode 102 comprises a main grid line and a secondary grid line;
a first transparent conductive layer 111, a hole transport layer 112, a perovskite light absorbing layer 113, an electron transport layer 114, and a second transparent conductive layer 115 are sequentially prepared on the buried gate glass 101 having the top electrode 102.
The first transparent conductive layer 111 and the second transparent conductive layer 115 are made of one or more materials selected from ITO, IZO, AZO, graphene, and metal nanowires including but not limited to Ag, Au, Cu, or Al, and have a thickness of 0 to 500nm, and the transparent conductive layers are manufactured by magnetron sputtering, Reactive Plasma Deposition (RPD), or chemical vapor deposition (cvd) selected from Plasma Enhanced Chemical Vapor Deposition (PECVD), atomic layer deposition (a L D), low pressure chemical vapor deposition (L PCVD), or Metal Organic Chemical Vapor Deposition (MOCVD).
The perovskite light absorption layer 113 material can adopt FA1-xCSxPb3 (wherein 0.l < x <0.3) or FA1-xMAxPb3 (wherein 0.05 ≦ x ≦ 0.5). The perovskite light absorption layer 113 is prepared by a spin coating method.
The hole transport layer 112 is made of one or more of PTAA, NiOx, P3HT, V2O5, MoOx, PEDOT, PSS, WOx, Sprio-OMeTAD, CuSCN, Cu2O, CuI, Spiro-TTB, m-MTDATA or TAPC, and has a thickness of 0-200 nm. The hole transport layer 112 is prepared by spin coating or sputtering.
The electron transport layer 114 is made of one or more of SnO2, TiO2, ZnO, ZrO2, fullerene and derivatives (C60, C70 and PCBM), TiSnOx or SnZnOx, and has a thickness of 0-500 nm. The electron transport layer 114 is prepared by spin coating or sputtering.
The groove of the buried gate glass 101 is prepared by carborundum grinding, laser etching or chemical corrosion, and the depth is 1-2000 mu m. The pattern of the groove is 1-20 main lines and 1-100 auxiliary lines.
The top electrode 102 is a gate line electrode and the height of the electrode is 2-2000 μm. The length of the main grid electrode is the same as the side length of the buried grid glass 101, the width is 100-. The length of the secondary grid lines is the same as the side length of the buried grid glass 101, the width of the secondary grid lines is 50-500 mu m, and the number of the secondary grid lines is 1-100. The top electrode 102 is positioned in the trench of the buried gate glass 101. The top electrode 102 is deposited in the groove of the buried gate glass 101 through one or more of screen printing, ink-jet printing, steel plate printing and micro-nano metal stamping modes to form the buried gate electrode.
The preparation method of the silicon-based battery comprises the following steps:
depositing a first intrinsic type hydrogenated amorphous silicon layer 124 and a second intrinsic type hydrogenated amorphous silicon layer 127 on both sides of the silicon wafer, respectively;
depositing a p-type hydrogenated amorphous silicon layer 123 on the first intrinsic type hydrogenated amorphous silicon layer 124, and depositing an n-type hydrogenated amorphous silicon layer 126 on the second intrinsic type hydrogenated amorphous silicon layer 127;
depositing a first transparent conductive oxide layer 122 and a second transparent conductive oxide layer 128 on the p-type hydrogenated amorphous silicon layer 123 and the n-type hydrogenated amorphous silicon layer 126, respectively;
depositing a front electrode 121 of a silicon-based cell on the first transparent conductive oxide layer 122 and depositing a back electrode 129 of the silicon-based cell on the second transparent conductive oxide layer 128; there are three methods for preparing the front electrode 121 of the silicon-based battery and the back electrode 129 of the silicon-based battery, which are screen printing, ink-jet printing or electroplating methods, respectively.
The first transparent oxide conductive layer 122 is made of one or more of ITO, IZO and AZO, and has a thickness of 10-200 nm.
The thickness of the p-type hydrogenated amorphous silicon layer 123 and the n-type hydrogenated amorphous silicon layer 126 is 2 to 200 nm;
the first and second intrinsic type hydrogenated amorphous silicon layers 124 and 127126 have a thickness of 2-50 nm.
The thickness of the n-type silicon substrate 125 is 150-250 μm.
The first intrinsic type hydrogenated amorphous silicon layer 124, the second intrinsic type hydrogenated amorphous silicon layer 127, the p type hydrogenated amorphous silicon layer 123, and the n type hydrogenated amorphous silicon layer 126 are fabricated using Plasma Enhanced Chemical Vapor Deposition (PECVD).
The following examples are provided according to the above preparation method, specifically as follows:
example 5
The preparation method of the laminated photoelectric device comprises the following steps:
the preparation of the silicon-based battery comprises the following steps:
step 1: respectively locking an intrinsic hydrogenated amorphous silicon layer on two surfaces of the cleaned and textured n-type silicon wafer through plasma enhanced chemical vapor deposition, wherein the thicknesses of the intrinsic hydrogenated amorphous silicon layers are 10nm and 8nm respectively;
step 2: then depositing an n-type hydrogenated amorphous silicon layer 127 with the thickness of 10nm on the second hydrogenated amorphous silicon layer with the thickness of 8nm, and depositing a p-type hydrogenated amorphous silicon layer 123 with the thickness of 15nm on the hydrogenated intrinsic amorphous silicon layer with the thickness of 10 nm;
and step 3: preparing a first transparent conductive oxide layer 122 and a second transparent conductive oxide layer 128 on the back surface of the n-type hydrogenated amorphous silicon layer 126 and the p-type hydrogenated amorphous silicon layer 123 through magnetron sputtering, wherein the material is Indium Tin Oxide (ITO) and the thickness is 120 nm;
and 4, step 4: preparing a front electrode 121 of a silicon-based battery and a back electrode 129 of the silicon-based battery on the oxidized transparent conductive layer by screen printing, wherein the thickness of the front electrode 121 and the back electrode 129 of the silicon-based battery are 50 micrometers;
the preparation of the perovskite battery comprises the following steps:
step 1: preparing a grid line groove on the cleaned buried grid glass 101 in a laser grooving mode, wherein the grid line groove is provided with two main grid line grooves, the width of the main grid line groove is 100 micrometers, the depth of the main grid line groove is 50 micrometers, and 8 auxiliary grid line grooves, the width of the auxiliary grid line groove is 20 micrometers, and the depth of the auxiliary grid line groove is 50 mm;
step 2; preparing a top electrode 102 in a groove of the buried gate glass 101, wherein the electrode material is Ag, and the preparation method is magnetron sputtering;
and step 3: preparing a transparent conducting layer on a substrate of the buried gate glass 101 with the top electrode 102, wherein the material is Indium Tin Oxide (ITO), the deposition method is physical vapor deposition, and the thickness of the deposited film is 80 nm;
and 4, step 4: preparing a hole transport layer 112 on the prepared transparent conducting layer, wherein the material is spiro-OMeTAD, the preparation method is spin coating, the annealing temperature is 120 ℃, and the thickness is 80 nm;
and 5: preparing a perovskite light absorption layer 113 on the prepared hole transport layer 112, wherein the light absorption layer material is FA0.9MA0.1Pb3, the deposition method is a spin-coating method, the spin-coating raw materials are sulfonated Formamidine (FAI), classical Methylamine (MAI) and PbI2, the annealing temperature is 80 ℃, and the thickness of the perovskite light absorption layer is 400 nm;
step 6: preparing an electron transport layer 114 on the prepared perovskite light absorption layer 113, wherein the material is stannic oxide SnO2, the preparation method is spin coating, the annealing temperature is 100 ℃, and the film thickness is 50 nm;
and 7: preparing a transparent conducting layer on the prepared electron transport layer 114, wherein the material is Indium Tin Oxide (ITO), the deposition method is physical vapor deposition, and the thickness of the deposited film is 80 nm;
connection and packaging of silicon-based batteries and perovskite batteries:
step 1: connecting the front electrode 121 of the silicon-based cell of the silicon-based heterojunction cell 120 with the transparent conductive layer of the perovskite cell to complete the device lamination;
step 2: encapsulating the stacked photovoltaic devices by a bottom encapsulation layer 103; the encapsulation layer 103 is made of glass.
The invention independently prepares two batteries, and the two batteries are connected in series through the metal electrode, thereby avoiding the influence of the top battery and the silicon-based battery interface and the texture appearance, and simplifying the structure and the preparation method.
Example 6
This example differs from example 5 in that: the silicon-based battery of the embodiment adopts the PERC battery 220, and the perovskite battery is of a positive structure. The perovskite cell was therefore identical to the material and preparation method of each layer of example 5, with the functional layer preparation sequence being: the first transparent conductive layer 111, the electron transport layer 114, the perovskite light absorbing layer 113, the hole transport layer 112, and the second transparent conductive layer 115, except that the preparation order is reversed so that light is incident from the electron transport layer 114 side.
The silicon-based cell includes a front electrode 121 of the silicon-based cell, an anti-reflection layer 222, an n + emitter 223, a p-type silicon substrate 224, a passivation layer 225, and an aluminum back field 226.
The thickness of the p-type silicon substrate 224 is 150-250 μm.
The thickness of the anti-reflective layer 222 and the n + emitter 223 is 2-200 nm.
The thickness of the aluminum back field 226 is 2-2000 μm.
The P-type silicon cell can be prepared by methods known to those skilled in the art, and will not be described herein.
To sum up: the invention independently prepares two batteries, and the two batteries are connected in series through the metal electrode, thereby avoiding the influence of the top battery and the silicon-based battery interface and the texture appearance, and simplifying the structure and the preparation method.
In the embodiments provided in the present application, it should be understood that the disclosed structures and methods may be implemented in other ways. The structural embodiments described above are merely illustrative; it should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Moreover, it is noted that, in this document, relational terms such as "first," "second," "third," and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims (10)
1. A self-encapsulating laminated optoelectronic device, comprising: from last buried gate glass (101), perovskite battery, silicon-based battery and encapsulated layer (103) of connecting down, buried gate glass's (101) inslot sets up top electrode (102), set up perovskite battery on top electrode (102), silicon-based battery passes through silicon-based battery's preceding electrode (121) and connects perovskite battery, silicon-based battery's back electrode (129) with top electrode (102) in buried gate glass (101) form the current return circuit, silicon-based battery's back electrode (129) and encapsulated layer (103) bonding.
2. The self-encapsulating laminated optoelectronic device of claim 1, wherein the silicon-based cell comprises a PERC cell (220) or a heterojunction cell or an N-type PERT cell.
3. The self-encapsulated layered photovoltaic device according to claim 1, wherein the perovskite cell comprises a first transparent conductive layer (111), a hole transport layer (112), a perovskite light absorbing layer (113), an electron transport layer (114) and a second transparent conductive layer (115) arranged from top to bottom, the second transparent conductive layer (115) being connected to the front electrode (121) of the silicon-based cell.
4. The self-encapsulated layered photovoltaic device according to claim 1, wherein said perovskite cell comprises, from top to bottom, a first transparent conductive layer (111), an electron transport layer (114), a perovskite light absorbing layer (113), a hole transport layer (112) and a second transparent conductive layer (115), said second transparent conductive layer (115) being connected to the front electrode (121) of said silicon-based cell.
5. The self-encapsulated laminated photovoltaic device as claimed in claim 1, wherein the top electrode (102), the front electrode (124) of the silicon-based cell and the back electrode (129) of the silicon-based cell are made of one or more of aluminum, silver, gold, titanium, bismuth, tin, palladium, nickel, chromium and copper, and have a thickness of 1-2000 μm.
6. The self-encapsulated laminated photovoltaic device of claim 1, wherein the top electrode (102) comprises n main gate lines and m sub-gate lines intersecting perpendicularly; n is 1-20; the value range of m is 1-100.
7. The self-encapsulated laminated photovoltaic device according to claim 6, wherein the top electrode (102) has a depth in the range of 1-2000 μm, the lengths of the main gate line and the sub-gate line are equal to the length of the buried gate glass (101), the width of the main gate line is in the range of 10-1000 μm, and the width of the sub-gate line is in the range of 10-500 μm.
8. A self-encapsulated laminated photovoltaic device according to any of claims 1 to 7, wherein the ratio of the light-blocking area of the front electrode (121) of the silicon-based cell to the light-blocking area of the top electrode (102) of the perovskite cell is in the range of 0.5 to 2.
9. A preparation method of a self-packaging laminated photoelectric device is characterized by comprising the following steps: respectively manufacturing a perovskite battery and a silicon-based battery;
connecting a front electrode (121) of the silicon-based battery to the perovskite battery;
and packaging the connected perovskite battery and the silicon-based battery to obtain the laminated photoelectric device.
10. The method for preparing a self-encapsulated laminated photovoltaic device according to claim 9, wherein the step of manufacturing the perovskite cell comprises the following steps:
preparing a groove on the buried gate glass (101), wherein the groove comprises a main groove and an auxiliary groove;
preparing a top electrode (102) in the groove, wherein the top electrode (102) comprises a main grid line and a secondary grid line;
sequentially preparing a first transparent conductive layer (111), a hole transport layer (112), a perovskite light absorption layer (113), an electron transport layer (114) and a second transparent conductive layer (115) or sequentially preparing the first transparent conductive layer (111), the electron transport layer (114), the perovskite light absorption layer (113), the hole transport layer (112) and the second transparent conductive layer (115) on buried gate glass (101) with a top electrode (102) to obtain a perovskite battery;
the front electrode (121) of the silicon-based cell is connected to the second transparent conductive layer (115) of the perovskite cell.
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| CN115101613A (en) * | 2022-08-29 | 2022-09-23 | 一道新能源科技(衢州)有限公司 | Amorphous silicon laminated solar cell and manufacturing method thereof |
| CN117317041A (en) * | 2023-11-29 | 2023-12-29 | 浙江晶科能源有限公司 | Solar cell and photovoltaic module |
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