CN111384178B - 半导体器件以及用于制造此类半导体器件的方法 - Google Patents

半导体器件以及用于制造此类半导体器件的方法 Download PDF

Info

Publication number
CN111384178B
CN111384178B CN201911391185.2A CN201911391185A CN111384178B CN 111384178 B CN111384178 B CN 111384178B CN 201911391185 A CN201911391185 A CN 201911391185A CN 111384178 B CN111384178 B CN 111384178B
Authority
CN
China
Prior art keywords
layer
dielectric
ferroelectric
semiconductor device
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911391185.2A
Other languages
English (en)
Other versions
CN111384178A (zh
Inventor
S·M·萨拉赫丁
A·斯佩索特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Publication of CN111384178A publication Critical patent/CN111384178A/zh
Application granted granted Critical
Publication of CN111384178B publication Critical patent/CN111384178B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

公开了一种半导体器件，包括：半导体衬底，其包括在源极区与漏极区之间的沟道区；布置成与该沟道区相互作用的栅极结构；以及布置在该沟道区与该栅极结构之间的介电结构。介电结构包括高k介电层或高k铁电层以及与该高k介电层或该高k铁电层直接接触的至少一个二维(2D)h‑BN层。

Description

半导体器件以及用于制造此类半导体器件的方法
技术领域
本公开涉及一种半导体器件以及用于制造此类半导体器件的方法。本公开涉及逻辑和存储器半导体器件两者。
背景技术
在半导体器件(逻辑或存储器器件)的加工期间，热退火步骤例如对于源极和漏极(S/D)注入而言是必需的。然而，这种热退火可能引起金属原子扩散到高k栅极电介质中和/或高k电介质中的氧原子扩散到下面的硅中。这些扩散过程使器件的可靠性以及逻辑和存储器器件两者中的栅极氧化物的耐久性降级。
该问题的可能的解决方案是在栅极电介质堆叠中引入扩散势垒(或通常也被称为界面钝化层)。可在栅堆叠(其包括栅极电介质堆叠以及该栅极电介质堆叠上的栅电极堆叠)中插入势垒层以防止不期望的界面反应。这些势垒层的引入有利于栅堆叠的电气性能。可例如在高k介电层与衬底之间插入势垒层以阻止氧从高k电介质扩散到下面的衬底中，或者可在高k介电层与金属栅电极之间插入势垒层以阻止金属从金属栅电极扩散到高k介电层中。
在Yum等人的文章“外延ALD BeO：用于EOT缩放和可靠性改进的高效氧扩散势垒(Epitaxial ALD BeO:efficient oxygen diffusion barrier for EOT scaling andreliability improvements)”中，薄BeO层通过原子层沉积(ALD)沉积在Si衬底上，作为用作界面钝化层的SiO2的替换物。ALD BeO层允许物理厚度的良好控制，并且导致SI表面的最小氧化。它还抑制了沉积后退火之后的漏电流。
在专利US9831243中，在HfO2与TiN之间插入多复合层势垒层(multi-composition-layer barrier layer)。该势垒层导电，但是阻止金属、硅或介电材料之间的互扩散和反应。例如，可在高k介电层与来自金属栅电极的Al金属之间插入TiN势垒层。
然而，这些扩散势垒层的引入增加了栅极电介质堆叠的等效氧化物厚度(EOT)。
发明内容
本公开的目的是提供一种具有改进的耐久性、可靠性和寿命的半导体器件。本公开的目的是提供一种克服现有技术的缺点(诸如栅极电介质堆叠的增加的等效氧化物厚度(EOT))的替换介电结构。
在第一发明方面，本公开提供了一种半导体器件，包括：半导体衬底，其包括在源极区与漏极区之间的沟道区；布置在该半导体衬底上以与该沟道区相互作用的栅极结构；以及布置在该沟道区与该栅极结构之间的介电结构，该介电结构包括高k介电层或高k铁电层以及与该高k介电层或该高k铁电层直接接触的至少一个二维(2D)h-BN层。
本公开的实施例的优点在于，改进了半导体器件的耐久性和可靠性。这适用于逻辑器件以及存储器器件两者，诸如举例而言铁电器件(FeFET)。
本公开的实施例的优点在于，等效氧化物厚度(EOT)不受栅极电介质堆叠中的势垒层的引入的影响。
本公开的实施例的优点在于，载波移动性未被影响。
本公开的实施例的优点在于，在不损害器件特性的情况下减少了栅堆叠中的层数。
在根据第一发明方面的实施例中，该至少一个2D h-BN层位于沟道区与高k介电层或高k铁电层之间。这具有以下优点：在衬底与高k介电层或高k铁电层之间将基本上不会发生氧扩散。
在根据第一发明方面的实施例中，该至少一个2D h-BN层位于高k介电层或高k铁电层与栅极结构之间。这提供了一种其中在栅极结构与高k介电层或高k铁电层之间将基本上不会发生金属扩散的半导体器件。
在根据第一发明方面的实施例中，可能存在与高k介电层或高k铁电层直接接触的另一2D h-BN层。该另一2D h-BN层存在于该至少一个2D h-BN层所位于的高k介电层或高k铁电层的一侧的相对侧。
这具有以下优点：可阻止衬底与高k层之间的氧扩散以及高k层与栅极结构之间的金属扩散两者。
在根据第一发明方面的实施例中，该至少一个2D h-BN层或该另一2D h-BN层具有小于五个原子层的厚度。更优选地，该层包括1至2个h-BN原子层。薄h-BN层的优点在于，介电结构的EOT与现有技术的结构相比得到了改进。
在根据第一发明方面的实施例中，高k介电层或高k铁电层分别是基于Hf的介电层或基于Hf的铁电层。
在根据第一发明方面的实施例中，栅极结构包括金属栅电极。
在第二发明方面，本公开提供了一种用于制造半导体器件的方法。该方法包括以下步骤：在半导体衬底中在源极区与漏极区之间提供沟道区，至少在该沟道区上提供介电结构。提供介电结构的步骤进一步包括：提供高k介电层或高k铁电层以及提供与该高k介电层或该高k铁电层直接接触的至少一个二维(2D)h-BN层，并在该介电结构上提供栅极结构。
在根据第二发明方面的实施例中，提供该至少一个2D h-BN层包括：在沟道区与高k介电层或高k铁电层之间提供该层，或者在高k介电层或高k铁电层与栅极结构之间提供该层。
在根据第二发明方面的实施例中，提供了与高k介电层或高k铁电层直接接触的处于该至少一个2D h-BN层所位于的高k介电层或高k铁电层的一侧的相对侧的另一2D h-BN层。
在根据第二发明方面的实施例中，该一个或该另一2D h-BN层通过外延生长或通过机械或化学剥离来提供。
在根据第二发明方面的实施例中，提供该一个或该另一2D h-BN层包括提供小于五个原子层的2D h-BN。
在根据第二发明方面的实施例中，提供高k介电层或高k铁电层包括提供基于Hf的介电层或基于Hf的铁电层。
在根据第二发明方面的实施例中，提供栅极结构包括提供金属栅极结构。
附图说明
借助于以下描述和附图将进一步阐明本公开。
图1至3示意性地解说了根据第一发明方面的实施例的半导体器件。
图4至5示意性地解说了根据第二发明方面的实施例的用于制造半导体器件的方法的工艺步骤。
这些附图仅是示意性而非限制性的。在附图中，出于解说性目的，一些元件的大小可被放大并且未按比例绘制。尺度和相对尺度并不必然对应于对本发明实践的实际简化。
权利要求中的任何附图标记不应被解释为限制范围。
在不同的附图中，相同的附图标记指代相同或相似的元件。
各实施例的详细描述
借助于以下对本公开的若干实施例的详细描述以及附图将进一步阐明本公开。
在以下详细描述中，阐述了众多具体细节以便提供对本公开以及在特定实施例中可如何实践本公开的透彻理解。然而，将理解，可在没有这些具体细节的情况下实践本公开。在其他实例中，未详细地描述公知的方法、规程和技术，以免混淆本公开。虽然本公开将针对特定实施例且参考某些附图进行描述，但是本公开不限于此。本文所包括和描述的附图是示意性的，并且不限制本公开的范围。还注意到，在附图中，出于解说的目的，一些元件的大小可被放大并因此未按比例绘制。
权利要求书中所使用的术语“包括”不应被解释为受限于其后列出的装置；它不排除其他元素或步骤。它需要被解释为指定所阐述的如被称为特征、整数、步骤或组件的存在，但不排除一个或多个其他特征、整数、步骤或组件或其分组的存在或添加。因此，表述“一种包括装置A和B的设备”的范围不应当被限定于仅由组件A和B组成的设备。
当在实施例中对术语“堆叠”作出引用的情况下，引用的是层的堆叠。这可仅涉及一层，但也可涉及一层形成在另一层顶部之上的一个以上的层。例如，栅极电介质堆叠可包括仅一个栅极介电层，或者可包括一层形成在另一层顶部之上以一起形成栅极电介质堆叠的一系列/堆不同栅极介电层。
当在实施例中如在“高k电介质”中那样对术语“高k”作出引用的情况下，引用的是具有大于SiO2的介电常数(即，在使用经四舍五入数字时大于3.9或4)的介电常数的介电材料。高k电介质允许较大物理厚度(与SiO2相比)以获得与使用薄得多的SiO2层可获得的有效电容相同的有效电容。高k电介质的示例是例如基于Hf的电介质，诸如HfO2。
在下文中将参考硅(Si)衬底来描述某些实施例，但是应理解，它们同样适用于其他半导体衬底。在各实施例中，“衬底”可包括半导体衬底，诸如举例而言硅、砷化镓(GaAs)、磷化砷化镓(GaAsP)、磷化铟(InP)、锗(Ge)或硅锗(SiGe)衬底。除了半导体衬底部分之外，“衬底”还可包括例如绝缘层，诸如SiO2或Si3N4层。因此，术语衬底还包括玻璃上硅，蓝宝石上硅衬底。因此，术语“衬底”通常被用于定义位于感兴趣的层或部分之下的层的元件。此外，“衬底”可以是在其上形成层(例如玻璃或金属层)的任何其他基底。因此，衬底可以是晶片(诸如毯式晶片)，或者可以是施加到另一基底材料的层(例如，生长在较低层之上的外延层)。
根据本发明的各实施例的半导体器件适用于晶体管型器件，诸如逻辑器件(诸如MOSFET)或存储器器件(诸如铁电存储器器件(FeFET)或NAND闪存器件)。晶体管型器件是指具有至少三个端子的器件，该器件通常包括在源极区与漏极区(源极和漏极端子或触点)之间的沟道区以及在该沟道区上的栅极区(栅极端子或触点)。
根据本发明的各实施例的半导体器件包括至少一个半导体晶体管。MOSFET半导体器件包括至少一个金属氧化物半导体场效应晶体管。CMOS半导体器件包括至少一个PMOS晶体管和至少一个NMOS晶体管。FeFET存储器器件包括至少一个铁电场效应晶体管。
现有技术的铁电(FeFET)存储器器件非常类似于金属氧化物半导体(MOSFET)器件，然而栅极氧化物电介质被FeFET器件的铁电材料替换。通过调制栅电极(在铁电层的顶部)，将在铁电半导体(即，沟道)界面处发生累积或耗尽，并由此导通或关断FeFET。
根据第一发明方面，公开了一种半导体器件，其包括具有源极区/漏极区和沟道区的半导体衬底。半导体器件进一步包括在沟道区与栅极结构之间的介电结构。因此，介电结构存在于半导体衬底的顶部上(在沟道区上)，并且在其上存在栅极结构(其也可被称为栅电极结构或堆叠)。介电结构包括高k介电层或高k铁电层(取决于半导体器件的类型)以及与该高k介电层或该高k铁电层物理或直接接触的至少一个二维h-BN层。该至少一个h-BN层可存在于高k介电层或高k铁电层之上或之下并与其直接接触。根据各实施例，该器件可包括与高k层或高k铁电层物理或直接接触但处于与该至少一个二维h-BN层正接触高k层或高k铁电层的一侧相对的一侧的另一二维h-BN层。因此，介电结构可包括在高k介电层或高k铁电层的两侧之一处的一个2D h-BN层、或者在高k介电层或高k铁电层的相对侧处的两个2Dh-BN层。
栅极结构可包括用于半导体器件的任何合适的栅电极层，诸如举例而言金属栅电极层(例如，TiN、TaN、W、TiC、Ru等)或多晶硅栅电极层。
可使用本领域技术人员已知的沉积技术(诸如基于CVD或基于ALD的技术)来提供栅极结构和介电结构的所有层。为了形成二维h-BN层，进一步解释的其他技术也是可能的。
随着石墨烯的引入，还涉及了其他二维材料，诸如六方氮化硼(h-BN)。h-BN属于六方晶系并具有层状结构，该层状结构具有与石墨烯相似的晶格常数。由于它与石墨烯的相似性和它白色的颜色，它通常被称为“白石墨烯”。H-BN是二维绝缘体，并且被视为仅次于石墨烯的第二强材料。它具有约5.9eV的直接带隙。在升高的温度(高达2000摄氏度)下，h-BN保持稳定。此外，hBN具有良好的工艺稳定性(例如高电阻)，并且无毒且对环境友好。h-BN中硼与氮之间的间隔小于氧和栅极金属原子的大小。因此，薄h-BN原子层是对氧的完美绝缘体和完美的金属扩散势垒。
根据本发明的各实施例，通过将二维h-BN层引入半导体器件的介电结构中，阻止氧扩散到下面的沟道(包括例如硅或锗)中和/或金属扩散到高k介电层或高k铁电层中。优点在于增强了晶体管的耐久性和寿命，尤其是存储器晶体管(诸如FeFET)的耐久性。耐久性增强可以是高达三个数量级。
在高k介电层或高k铁电层之下引入h-BN层的优点在于，阻止氧从高k介电层或高k铁电层向下面的半导体衬底(包括例如Si或Ge)扩散。因此，h-BN层在高k介电层或高k铁电层与半导体衬底之间形成势垒层或界面层。
在高k介电层或高k铁电层之上引入h-BN层的优点在于，阻止金属原子从栅极结构(包括例如栅电极)扩散到下面的高k介电层或高k铁电层中。因此，h-BN层在高k介电层或高k铁电层与金属栅电极层之间形成势垒层或界面层。
根据各实施例，h-BN层具有优选地小于五个原子层、更优选地1至2个原子层的厚度。由于优选地按比例缩小栅堆叠的厚度以便尽可能地保持EOT，因此h-BN层的厚度优选地为约1至2个原子层。这被发现是在具有良好的EOT和最小栅极泄漏的情况下具有减小的栅堆叠厚度的一个良好的折衷方案。
根据各实施例，可使用从现有技术中已知的不同技术(诸如举例而言通过-BN的外延生长)来提供h-BN层。化学气相沉积(CVD)可被用于外延生长h-BN层。外延生长h-BN层的优点在于，原子h-BN层的数目可以得到很好的控制。用于提供h-BN层的另一种可能的技术是通过机械或化学剥离(并转移到半导体衬底)。剥离的优点在于可使用更低的热预算。
图1至3示出了根据本发明的各实施例的半导体器件。
一种类型的半导体器件可以是根据本公开的不同实施例的金属氧化物半导体(MOSFET)器件。MOSFET器件包括半导体衬底100，在该半导体衬底100中，两个区域(源极区102和漏极区103)被限定在第三(中间)区域(沟道区101)的相对侧。在沟道区101上形成栅堆叠(111和112一起)，该栅堆叠包括介电结构(栅极电介质堆叠)111以及该栅极电介质堆叠111的顶部上的栅极结构(栅电极堆叠)112。根据各实施例，栅极电介质堆叠111(用于MOSFET器件)包括高k介电层106以及与该高k介电层物理接触的至少一个2D h-BN层104、105。可在栅极电介质堆叠中的不同位置处引入h-BN层104、105，即，如在图1中的在高k层下方(h-BN 104)或者如在图2中的在高k层上方(h-BN 105)。h-BN层还可存在于两个位置处，即在高k介电层106的下方和上方，如图3所示。
高k介电层可由任何合适的高k材料制成，诸如举例而言基于Hf的介电层(例如HfO2)，并且可使用薄膜沉积技术(诸如举例而言原子层沉积(ALD))来提供。
栅极结构112可包括不同的栅电极层。栅电极堆叠可包括金属栅电极层，诸如举例而言TiN、Ti或WN层。栅电极堆叠可例如包括功函数金属层，以调谐栅堆叠的功函数。功函数金属层可由一个金属层或由一种或多种金属材料的金属层的堆叠形成。功函数金属层可例如由p型功函数金属(诸如TiN、TaN、TiTaN)或由此类材料的层的堆叠形成。功函数金属层还可例如由n型功函数金属(诸如Al、TiAl、TiC、TiAlC)或由此类材料的层的堆叠形成。栅电极层可通过任何常规沉积工艺(例如通过ALD、CVD或PVD)来沉积。栅电极堆叠可包括栅极填充层，诸如举例而言W层。栅电极堆叠还可包括基于多晶硅的栅电极层。
另一种类型的半导体器件可以是根据本公开的各实施例的铁电(FeFET)存储器器件。FeFET存储器器件是利用铁电层(诸如举例而言高k铁电层)来存储数据的存储器器件。
在衬底100的表面上提供了源极区102和漏极区103。源极区102和漏极区103被沟道区101分隔开。在沟道区101上方提供了介电结构111。介电结构111包括具有铁电层106的铁电存储器区域。铁电层106优选地包括基于高k的铁电材料，诸如举例而言基于Hf的铁电材料或基于Zr的铁电材料。铁电层106设置在半导体衬底的沟道区的顶部上。这可与沟道区直接电接触。使用铁电层106作为栅极介电层(相当于MOSFET器件的高k介电层)抑制去极化场并提供良好的保持。可使用本领域技术人员已知的沉积技术(诸如举例而言基于CVD或基于ALD的沉积技术)来提供铁电层106。
在铁电层106的顶部上和/或下方，存在与铁电层106物理接触的至少一个二维h-BN层104、105。类似于MOSFET结构的实施例，同样在存储器器件(更具体地FeFET)中，可在电介质堆叠中的不同位置处引入h-BN层104、105，即在基于高k的铁电层106下方(h-BN 104)或者在基于高k的铁电层106上方(h-BN 105)。h-BN层还可存在于两个位置处，即在基于高k的铁电层106的下方和上方。
在介电结构111上提供了栅极结构112，这相当于MOSFET器件的栅极结构112。栅极结构112可包括不同的栅电极层。栅电极堆叠可包括金属栅电极层，诸如举例而言TiN、Ti或WN层。
根据本发明的各实施例，公开了一种用于制造半导体器件的方法。
图4-5示出了用于制造半导体器件的方法的不同步骤。根据各实施例，可提供层的堆叠包括：提供衬底；在该衬底上提供介电结构，该介电结构包括高k介电层或高k铁电层以及与该高k介电层或该高k铁电层物理接触的至少一个二维(2D)h-BN层；以及在该介电结构上提供栅极结构。如图4所示，可使用诸如以上已经提及的常规沉积技术来提供各层。在提供不同的层之后，可执行常规的光刻图案化和蚀刻以提供图5的图案化结构。此后，进一步的退火步骤或注入步骤可被提供以使用本领域技术人员已知的方法来形成源极区和漏极区。
在先前的示例中，公开了所谓的先栅极半导体器件。然而，所谓的替换金属栅极(RMG)器件(或也被称为后栅极器件)也可以是本公开的一部分。在RMG工艺流程中，多晶硅和SiO2首先被用作虚栅堆叠(dummy gate stack)。在掺杂剂激活(其需要高温)之后，虚栅堆叠被去除并且被最终栅堆叠(包括高k电介质和金属栅极)替换。通过这种方法避免了在高温工艺步骤期间高k介电层的结晶以及金属栅极与高k介电层之间的化学反应(金属扩散)。因此，RMG方案正被考虑，以便避免高k/金属栅堆叠的早期激进热预算。
根据各实施例，不同的RMG工艺方案是可能的，诸如举例而言在工艺开始处沉积h-BN层和高k层，并且在去除虚栅极期间通过蚀刻停止层来保护该栅极电介质堆叠，或者在工艺结束处，即在去除虚栅极之后并在沉积最终金属栅极之前沉积h-BN层和高k层。
根据各实施例的优点在于改进了RMG半导体器件的电气特性。

Claims (11)

1.一种半导体器件(1)，包括：
半导体衬底，所述半导体衬底包括在源极区(102)与漏极区(103)之间的沟道区(101)；
布置在所述半导体衬底上以与所述沟道区(101)相互作用的栅极结构(112)；
布置在所述沟道区(101)与所述栅极结构(112)之间的介电结构(111)，所述介电结构(111)包括
高k介电层或高k铁电层(106)以及与所述高k介电层或所述高k铁电层(106)直接接触的至少一个二维(2D)h-BN层，所述至少一个2D h-BN层位于所述高k介电层或所述高k铁电层(106)与所述栅极结构(112)之间。
2.根据权利要求1所述的半导体器件(1)，其特征在于，所述介电结构进一步包括与所述高k介电层或所述高k铁电层(106)直接接触的处于所述至少一个2D h-BN层所位于的高k介电层或高k铁电层(106)的一侧的相对侧的另一2D h-BN层。
3.根据权利要求2所述的半导体器件(1)，其特征在于，所述至少一个2D h-BN层或所述另一2D h-BN层具有小于五个原子层的厚度。
4.根据权利要求1或2所述的半导体器件(1)，其特征在于，所述高k介电层或所述高k铁电层(106)分别是基于Hf的介电层或基于Hf的铁电层。
5.根据权利要求1或2所述的半导体器件(1)，其特征在于，所述栅极结构(112)包括金属栅电极。
6.一种用于制造半导体器件的方法，包括：
在半导体衬底(100)中在源极区(102)与漏极区(103)之间提供沟道区(101)；
至少在所述沟道区(101)上提供介电结构(111)，所述提供介电结构的步骤进一步包括：
提供高k介电层或高k铁电层(106)，以及
在所述高k介电层或所述高k铁电层(106)与所述栅极结构(112)之间提供与所述高k介电层或所述高k铁电层(106)直接接触的至少一个二维(2D)h-BN层；
在所述介电结构(111)上提供栅极结构(112)。
7.根据权利要求6所述的用于制造半导体器件的方法，其特征在于，进一步包括提供与所述高k介电层或所述高k铁电层(106)直接接触的处于所述至少一个2D h-BN层所位于的高k介电层或高k铁电层(106)的一侧的相对侧的另一2D h-BN层。
8.根据权利要求7所述的用于制造半导体器件的方法，其特征在于，提供所述一个2Dh-BN层或所述另一2D h-BN层是通过外延生长或通过机械或化学剥离来完成的。
9.根据权利要求7所述的用于制造半导体器件的方法，其特征在于，提供所述一个2Dh-BN层或所述另一2D h-BN层包括提供小于五个原子层的2D h-BN。
10.根据权利要求6或7所述的用于制造半导体器件的方法，其特征在于，提供高k介电层或高k铁电层(106)包括提供基于Hf的介电层或基于Hf的铁电层(106)。
11.根据权利要求6或7所述的用于制造半导体器件的方法，其特征在于，提供所述栅极结构(112)包括提供金属栅极结构。
CN201911391185.2A 2018-12-28 2019-12-30 半导体器件以及用于制造此类半导体器件的方法 Active CN111384178B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP18248304 2018-12-28
EP18248304.0 2018-12-28

Publications (2)

Publication Number Publication Date
CN111384178A CN111384178A (zh) 2020-07-07
CN111384178B true CN111384178B (zh) 2024-05-28

Family

ID=65013513

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911391185.2A Active CN111384178B (zh) 2018-12-28 2019-12-30 半导体器件以及用于制造此类半导体器件的方法

Country Status (2)

Country Link
US (1) US11251036B2 (zh)
CN (1) CN111384178B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11776607B2 (en) * 2019-01-28 2023-10-03 Institute of Microelectronics, Chinese Academy of Sciences Fusion memory
DE102019120692A1 (de) * 2019-07-31 2021-02-04 Infineon Technologies Ag Leistungshalbleitervorrichtung und Verfahren
US11087843B1 (en) * 2020-02-10 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Memory with FRAM and SRAM of IC and method for accessing memory
KR20230055281A (ko) * 2021-10-18 2023-04-25 삼성전자주식회사 이차원 물질을 포함하는 박막 구조체 및 전자 소자
CN117525003A (zh) * 2024-01-05 2024-02-06 华中科技大学 一种氮化硼钝化增强的砷化镓基半导体器件及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531470A (zh) * 2012-07-02 2014-01-22 中芯国际集成电路制造(上海)有限公司 一种半导体器件以及制作半导体器件的方法
JP2017041503A (ja) * 2015-08-18 2017-02-23 富士電機株式会社 半導体装置、および、その製造方法
CN107204371A (zh) * 2017-05-15 2017-09-26 北京大学 一种铁电场效应晶体管及其制备方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2441260B2 (de) 1974-08-28 1976-12-02 Laboratoire Suisse de Recherches Horlogeres, Neuenburg (Schweiz); Gutehoffnungshütte Sterkrade AG, 4200 Oberhausen Verfahren zur herstellung einer als trennmittel und diffusionsbarriere wirkenden schicht
US4104096A (en) 1974-08-28 1978-08-01 Laboratoire Suisse De Recherches Horlogeries Diffusion barrier and separation substance for metal parts adjoining each other in an oxygen free atmosphere
US6225169B1 (en) 2000-02-24 2001-05-01 Novellus Systems, Inc. High density plasma nitridation as diffusion barrier and interface defect densities reduction for gate dielectric
US6974779B2 (en) 2003-09-16 2005-12-13 Tokyo Electron Limited Interfacial oxidation process for high-k gate dielectric process integration
US8318565B2 (en) 2010-03-11 2012-11-27 International Business Machines Corporation High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof
US8847333B2 (en) 2011-09-01 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Techniques providing metal gate devices with multiple barrier layers
US8623717B2 (en) * 2012-06-12 2014-01-07 International Business Machines Corporation Side-gate defined tunable nanoconstriction in double-gated graphene multilayers
CN103208425B (zh) 2013-03-22 2015-08-26 中国科学院上海微系统与信息技术研究所 一种石墨烯调制的高K金属栅Ge基MOS器件的制作方法
CN104282749A (zh) 2013-07-09 2015-01-14 中国科学院微电子研究所 一种半导体结构及其制造方法
US10217819B2 (en) 2015-05-20 2019-02-26 Samsung Electronics Co., Ltd. Semiconductor device including metal-2 dimensional material-semiconductor contact
KR102434699B1 (ko) 2015-07-31 2022-08-22 삼성전자주식회사 확산방지층을 포함하는 다층구조체 및 이를 구비하는 소자
US10297441B2 (en) * 2016-08-08 2019-05-21 Applied Materials, Inc. Low-temperature atomic layer deposition of boron nitride and BN structures
CN107482064B (zh) 2017-08-28 2019-10-25 武汉华星光电半导体显示技术有限公司 薄膜晶体管及其制作方法以及阵列基板
US10658470B2 (en) * 2017-11-14 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Device with doped phosphorene and method for doping phosphorene
KR102637107B1 (ko) * 2018-09-18 2024-02-15 삼성전자주식회사 전자 소자 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531470A (zh) * 2012-07-02 2014-01-22 中芯国际集成电路制造(上海)有限公司 一种半导体器件以及制作半导体器件的方法
JP2017041503A (ja) * 2015-08-18 2017-02-23 富士電機株式会社 半導体装置、および、その製造方法
CN107204371A (zh) * 2017-05-15 2017-09-26 北京大学 一种铁电场效应晶体管及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
High carrier mobility in Si-MOSFETs with a hexagonal boron nitride buffer layer;Xiaochi Liu等;Solid State Communications;第209卷;论文1-4页，图2 *

Also Published As

Publication number Publication date
US11251036B2 (en) 2022-02-15
CN111384178A (zh) 2020-07-07
US20200211839A1 (en) 2020-07-02

Similar Documents

Publication Publication Date Title
CN111384178B (zh) 半导体器件以及用于制造此类半导体器件的方法
US10103264B2 (en) Channel strain control for nonplanar compound semiconductor devices
CN102610637B (zh) 制造应变的源极/漏极结构的方法
KR101166437B1 (ko) 반도체 전계효과 트랜지스터와 그 제조
TWI523149B (zh) 半導體製造製程及形成半導體器件之方法
CN111480238B (zh) 垂直晶体管的自对准底部间隔物的形成
CN102549755B (zh) 具有氧扩散阻挡层的半导体器件及其制造方法
US8329566B2 (en) Method of manufacturing a high-performance semiconductor device
JP4796771B2 (ja) 半導体デバイス
US10818790B2 (en) Semiconductor device
US10692859B2 (en) Large area diode co-integrated with vertical field-effect-transistors
US20080076216A1 (en) Method to fabricate high-k/metal gate transistors using a double capping layer process
US8026539B2 (en) Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same
US20110263092A1 (en) Method for fabricating a semiconductor device
KR20140112358A (ko) 소스 및 드레인 영역의 에피텍셜 형성 메커니즘에 대한 비대칭 순환 증착 및 에칭 공정
JP2011171706A (ja) トランジスタ及びその製造方法
CN103137488A (zh) 半导体器件及其制造方法
KR20110050599A (ko) 듀얼 일함수 금속 게이트 집적 동안 이온 주입을 사용하여 유효 일함수를 변화시키는 기법
US20090194816A1 (en) Semiconductor device and method of fabricating the same
US7989896B2 (en) Semiconductor device and method of fabricating the same
US9105663B1 (en) FinFET with silicon germanium stressor and method of forming
US10593600B2 (en) Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap
CN108701711A (zh) 用于宽带隙半导体功率器件的原位掺杂的半导体栅电极的系统和方法
US10224418B2 (en) Integrated circuit fabrication with boron etch-stop layer
US8729639B2 (en) Semiconductor device and method for producing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant