CN111384164B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN111384164B CN111384164B CN201811644421.2A CN201811644421A CN111384164B CN 111384164 B CN111384164 B CN 111384164B CN 201811644421 A CN201811644421 A CN 201811644421A CN 111384164 B CN111384164 B CN 111384164B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The embodiment of the invention discloses a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a substrate; the multilayer semiconductor layer is positioned on one side of the substrate and comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate; the source electrode, the grid electrode and the drain electrode are positioned on one side of the multilayer semiconductor layer, which is far away from the substrate, and the grid electrode is positioned between the source electrode and the drain electrode; the lower surface of the P-type material layer extends to the surface of one side, close to the channel layer, of the buffer layer or extends to the inside of the buffer layer, and the P-type material layer is electrically connected with the drain electrode. Through setting up P type bed of material and drain electrode electricity and connecting, P type bed of material injects the hole to the buffer layer under forward bias, and the electron that causes the trap to restrain in the buffer layer because of lattice defect or doping improves the speed that electron breaks away from the buffer layer, promotes semiconductor device's saturation current, reduces semiconductor device's dynamic on-resistance, promotes semiconductor device's performance.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
In recent years, GaN-based High Electron Mobility Transistors (HEMTs) have been developed rapidly, and AlGaN/GaN HEMTs having a wurtzite structure have been developed with the best prospects. The HEMT may also be referred to as a modulation doped field effect transistor (MODFET) or a Heterojunction Field Effect Transistor (HFET). The on-resistance and parasitic capacitance are small, the switching speed is fast, the thermal stability is good, and the high-temperature, high-frequency and high-power device is developed vigorously at present.
At present, GaN-based HEMT devices have already moved to the practical stage and play a critical role, but still have many reliability problems, which seriously restricts the popularization and further development of the devices. Because the existing gallium nitride growth and doping technology is not mature enough, the gallium nitride buffer layer has more defects which become traps for binding electrons. The bound electrons cannot be released quickly, so that the saturation current is reduced, the dynamic on-resistance is increased, and the initial state can be recovered at room temperature only by long recovery time.
Disclosure of Invention
In view of this, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, so as to solve the technical problems of the prior art that the dynamic on-resistance of the semiconductor device is large and the saturation current is small due to the electron bound by the defect in the buffer layer.
In a first aspect, an embodiment of the present invention provides a semiconductor device, including:
a substrate;
the multilayer semiconductor layer is positioned on one side of the substrate and comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate;
the source electrode, the grid electrode and the drain electrode are positioned on one side, far away from the substrate, of the multilayer semiconductor layer, and the grid electrode is positioned between the source electrode and the drain electrode;
the buffer layer is located on the surface of one side of the channel layer or the lower surface of the P-type material layer extends to the inside of the buffer layer, and the P-type material layer is electrically connected with the drain electrode.
Optionally, the extension length of the P-type material layer along the direction from the gate to the drain is L1, where L1 is greater than or equal to 1 μm.
Optionally, the extension height of the P-type material layer in the direction perpendicular to the substrate is L2, wherein L2 is more than or equal to 5 μm.
Optionally, the P-type material layer has the same extension length as that of the drain electrode in a direction parallel to the plane of the substrate and perpendicular to the direction in which the gate electrode points to the drain electrode.
Optionally, the upper surface of the P-type material layer is higher than the lower surface of the drain electrode; or the upper surface of the P-type material layer is lower than the lower surface of the drain electrode; or the upper surface of the P-type material layer is flush with the lower surface of the drain electrode.
Optionally, the semiconductor device further includes a P-type layer ohmic contact metal layer located on a side of the P-type material layer away from the substrate, and the P-type layer ohmic contact metal layer forms ohmic contact with the P-type material layer;
the P-type layer ohmic contact metal layer is electrically connected with the drain electrode.
Optionally, in a direction in which the gate points to the drain, a contact length between the P-type ohmic contact metal layer and the P-type material layer is L3, wherein L3 is greater than or equal to 1 μm;
and in the plane of the upper surface of the P-type material layer, the contact area of the P-type ohmic contact metal layer and the P-type material layer is S, wherein S is more than or equal to 1 mu m and 10 mu m.
Optionally, the preparation material of the P-type material layer includes at least one of GaN, AlN, AlGaN, InGaN, and GaNAs;
the doping element of the P-type material layer comprises at least one of Mg and Zn.
Optionally, the doping concentration of the P-type material layer is C, wherein 1 × 1016≤C≤5*1018。
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, including:
providing a substrate;
preparing a multilayer semiconductor layer on one side of the substrate, wherein the multilayer semiconductor layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate; a source electrode preparation area, a grid electrode preparation area and a drain electrode preparation area are formed on the multilayer semiconductor layer, and the grid electrode preparation area is positioned between the source electrode preparation area and the drain electrode preparation area;
preparing a P-type material layer in the multilayer semiconductor layer at one side of the drain electrode preparation area far away from the grid electrode preparation area, wherein the lower surface of the P-type material layer extends to the surface of one side of the buffer layer close to the channel layer or the lower surface of the P-type material layer extends to the inside of the buffer layer;
and preparing a source electrode in the source electrode preparation area, preparing a grid electrode in the grid electrode preparation area, and preparing a drain electrode in the drain electrode preparation area, wherein the drain electrode is electrically connected with the P-type material layer.
Optionally, preparing a P-type material layer in the multilayer semiconductor layer and on a side of the drain preparation region away from the gate preparation region, includes:
sequentially etching the barrier layer and the channel layer on one side of the drain electrode preparation area, which is far away from the grid electrode preparation area, to the upper surface of the buffer layer or the inside of the buffer layer to obtain an etched part;
and growing a P-type material on the etching part to obtain a P-type material layer.
Optionally, preparing a P-type material layer in the multilayer semiconductor layer and on a side of the drain preparation region away from the gate preparation region, includes:
and carrying out ion implantation on the multilayer semiconductor layer at one side of the drain electrode preparation area, which is far away from the grid electrode preparation area, so as to obtain a P-type material layer.
Optionally, after preparing a P-type material layer in the multilayer semiconductor layer and on a side of the drain preparation region away from the gate preparation region, the method further includes:
preparing a P-type layer ohmic contact metal layer on one side of the P-type material layer, which is far away from the substrate, wherein the P-type layer ohmic contact metal layer and the P-type material layer form ohmic contact;
the drain electrode is electrically connected with the P-type material layer and comprises:
and the drain electrode is electrically connected with the P-type layer ohmic contact metal layer.
According to the semiconductor device and the preparation method thereof provided by the embodiment of the invention, the P-type material layer is formed in the multilayer semiconductor layer at the side of the drain electrode far away from the grid electrode, the lower surface of the P-type material layer extends to the surface of the buffer layer close to the channel layer or the lower surface of the P-type material layer extends into the buffer layer, the P-type material layer is electrically connected with the drain electrode, a hole is injected into the buffer layer by the P-type material layer under forward bias, electrons bound by a trap caused by lattice defects or doping in the buffer layer are neutralized, the speed of separating the electrons from the buffer layer is increased, the saturation current of the semiconductor device is increased, the dynamic on-resistance of the semiconductor device is reduced, and the performance of the semiconductor device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments. It should be clear that the described figures are only views of some of the embodiments of the invention to be described, not all, and that for a person skilled in the art, other figures can be derived from these figures without inventive effort.
Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of the semiconductor device provided in FIG. 1 along section line A-A';
fig. 3 is a schematic top view of another semiconductor device according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of the semiconductor device provided in FIG. 3 along section line B-B';
fig. 5 is a schematic top view of a semiconductor device according to another embodiment of the present invention;
fig. 6 is a schematic cross-sectional view of the semiconductor device provided in fig. 5 along the sectional line C-C;
fig. 7 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 8-11 are schematic structural views of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 12 is a schematic flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 13 is a schematic structural view of etching the barrier layer and the channel layer on the side of the drain preparation region away from the gate preparation region up to the upper surface of the buffer layer or the inside of the buffer layer, according to an embodiment of the present invention;
FIG. 14 is a schematic structural diagram of a P-type material layer obtained by growing a P-type material according to an embodiment of the present invention;
fig. 15 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention;
FIG. 16 is a schematic view of a multi-layer semiconductor layer being ion implanted on a side of a drain preparation region away from a gate preparation region according to an embodiment of the present invention;
fig. 17 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to still another embodiment of the present invention;
fig. 18 is a schematic structural diagram of a P-type ohmic contact metal layer according to an embodiment of the present invention;
fig. 19 is a schematic structural diagram of the source, gate and drain electrodes and the drain electrode electrically connected to the P-type ohmic contact metal layer according to the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described by the detailed description with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
The embodiment of the invention provides a semiconductor device, which comprises a substrate; the multilayer semiconductor layer is positioned on one side of the substrate and comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate; the source electrode, the grid electrode and the drain electrode are positioned on one side of the multilayer semiconductor layer, which is far away from the substrate, and the grid electrode is positioned between the source electrode and the drain electrode; the lower surface of the P-type material layer extends to the surface of one side, close to the channel layer, of the buffer layer or the lower surface of the P-type material layer extends to the inside of the buffer layer, and the P-type material layer is electrically connected with the drain electrode. By adopting the technical scheme, the P-type material layer is electrically connected with the drain electrode, holes are injected into the buffer layer by the P-type material layer under forward bias, electrons bound by traps caused by lattice defects or doping in the buffer layer are neutralized, the speed of separating the electrons from the buffer layer is increased, the saturation current of the semiconductor device is increased, the dynamic on-resistance of the semiconductor device is reduced, and the performance of the semiconductor device is improved.
The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a cross section of the semiconductor device provided in fig. 1 along a section line a-a'; as shown in fig. 1 and 2, a semiconductor device provided by an embodiment of the present invention may include:
a substrate 10;
a multilayer semiconductor layer 20 on a side of a substrate 10, the multilayer semiconductor layer 20 including a buffer layer 202, a channel layer 203, and a barrier layer 204 in this order on the side of the substrate 10;
a source electrode 31, a gate electrode 32 and a drain electrode 33 positioned on a side of the multilayered semiconductor device 20 away from the substrate 10, the gate electrode 32 being positioned between the source electrode 31 and the drain electrode 33;
and the P-type material layer 40 is positioned in the multilayer semiconductor layer 20 and positioned on the side of the drain electrode 33 far away from the gate electrode 32, the lower surface of the P-type material layer 40 extends to the surface of the buffer layer 202 on the side close to the channel layer 203 or the lower surface of the P-type material layer 40 extends to the inside of the buffer layer 202, and the P-type material layer is electrically connected with the drain electrode 33.
Illustratively, the material of the substrate 10 may be one or a combination of sapphire, silicon carbide, silicon, gallium arsenide, gallium nitride, or aluminum nitride, and may also be other materials suitable for growing gallium nitride, which is not limited in this embodiment of the present invention.
The multilayer semiconductor layer 20 includes a buffer layer 202, a channel layer 203, and a barrier layer 204 in this order on one side of the substrate 10. The material of the buffer layer 202 may be nitride, specifically, GaN or AlN or other nitride, and the buffer layer 202 may be used for the epitaxial channel layer 203. The thickness of the buffer layer 202 is between 1 μm and 5 μm in a direction perpendicular to the substrate 10. The doping type of the buffer layer 202 may be n-type or p-type, and the doping in the buffer layer 202 may be unintentional doping or undoped. The material of the channel layer 203 may be GaN or other semiconductor material, such as InAlN. The doping type of the channel layer 203 is unintentional doping, and the thickness of the channel layer 203 is between 100nm and 500nm in a direction perpendicular to the substrate 10. The barrier layer 204 is located above the channel layer 203, and the material of the barrier layer 204 can be any semiconductor material capable of forming a heterojunction structure with the channel layer 203, including gallium-based compound semiconductor materials or nitride-based compound semiconductor materials, such as InxAlyGazN1-x-y-z, wherein x is greater than or equal to 0 and less than or equal to 1, y is greater than or equal to 0 and less than or equal to 1, and z is greater than or equal to 0 and less than or equal to 1. When the barrier layer 204 is an AlGaN layer, the Al content of the AlGaN layer is usually between 10% and 30%, and the thickness of the AlGaN layer is usually between 10nm and 30 nm. Alternatively, the channel layer 203 and the barrier layer 204 constitute a semiconductor heterojunction structure, and a high-concentration two-dimensional electron gas is formed at the interface of the channel layer 203 and the barrier layer 204.
The source electrode 31, the gate electrode 32, and the drain electrode 33 are located on the multilayer semiconductor layer 20 on a side away from the substrate 10, and the gate electrode 32 is located between the source electrode 31 and the drain electrode 33, as shown in fig. 1 and 2. Alternatively, the source electrode 31 and the drain electrode 33 form ohmic contact with the multilayer semiconductor layer 20, and the gate electrode 32 forms schottky contact with the multilayer semiconductor layer 20. Alternatively, the source electrode 31 and the drain electrode 33 may be made of one or a combination of Ni, Ti, Al, Au, and the like, and the gate electrode 32 may be made of one or a combination of Ni, Pt, Pb, Au, and the like. The gate 32 may be a single-layer metal gate, or may be a stacked or multi-layer metal gate structure. Alternatively, the gate 32 may be rectangular in shape (not shown); it may be T-shaped as shown in fig. 2, which ensures good schottky contact between the gate electrode 32 and the multilayer semiconductor layer 20.
The P-type material layer 40 is located in the multilayer semiconductor layer 20 and on a side of the drain electrode 33 away from the gate electrode 32, a lower surface of the P-type material layer 40 extends to a surface of the buffer layer 202 on a side close to the channel layer 203 or a lower surface of the P-type material layer 40 extends to an inside of the buffer layer 202, and the P-type material layer 40 is electrically connected to the drain electrode 33. Therefore, when positive voltage is applied to the drain electrode 33, the P-type material layer 40 electrically connected with the drain electrode 33 can inject holes into the buffer layer 202, electrons bound by traps caused by lattice defects or doping in the buffer layer 202 are neutralized by the holes, the speed of separating the electrons from the buffer layer 202 is increased, the saturation current of a semiconductor device can be increased, the dynamic on-resistance of the semiconductor device is reduced, and the performance of the semiconductor device is improved. Meanwhile, the P-type material layer 40 is located on the side of the drain 33 away from the gate 32, and the channel region under the drain 33 is close to the potential of the P-type material layer 40 when the drain 33 is applied with positive voltage, so that depletion or turn-on cannot be caused.
It should be noted that how the P-type material layer 40 and the drain electrode 33 are electrically connected is not limited in the embodiment of the present invention, and for example, the electrical connection may be implemented by other conductive layers or conductive lines, which is not described herein again.
It is to be understood that the lower surface of the P-type material layer 40 mentioned in the embodiment of the present invention is a surface of the P-type material layer 40 on a side close to the substrate 10.
In summary, the semiconductor device provided in the embodiment of the present invention has the advantages that the P-type material layer is electrically connected to the drain electrode, and the P-type material layer injects holes into the buffer layer under a forward bias, neutralizes electrons bound by traps caused by lattice defects or doping in the buffer layer, increases a speed of electron detachment from the buffer layer, increases a saturation current of the semiconductor device, reduces a dynamic on-resistance of the semiconductor device, and improves performance of the semiconductor device.
Optionally, with continued reference to fig. 2, in the semiconductor device provided in the embodiment of the present invention, the multilayer semiconductor layer 20 may further include a nucleation layer 201 between the substrate 10 and the buffer layer 202, and a cap layer 205 on a side of the barrier layer 204 away from the channel layer 203. The material of the nucleation layer 201 may be a nitride, and in particular may be GaN or AlN or other nitride, and the nucleation layer 201 may be used to match the material of the substrate 10. The cap layer 205 is located on the side of the barrier layer 204 away from the channel layer 203, and the cap layer 205 may be a passivation layer for passivating the surface of the barrier layer 204, reducing gate leakage current, and facilitating metal/semiconductor ohmic contact. The thickness of the cap layer 205 in a direction perpendicular to the substrate 10 may be between 1nm and 10nm, and the material for forming the cap layer 205 may include at least one of GaN, AlN, AlGaN, or other semiconductor materials.
It should be noted that, in the schematic top view structure shown in fig. 1, the cap layer 205, the source electrode 31, the gate electrode 32, the drain electrode 33 and the P-type material layer 40 are only exemplarily shown due to the overlapping of the film layers.
Alternatively, with continued reference to FIGS. 1 and 2, the P-type material layer 40 has an extension L1 along the direction from the gate 32 toward the drain 33, i.e., the X direction shown in the figure, where L1 ≧ 1 μm.
Illustratively, the extension length of the P-type material layer 40 in the X direction is reasonably set, so that the P-type material layer 40 can be ensured to contain a sufficient number of holes, the sufficient number of holes can be ensured to be injected into the buffer layer 202, electrons bound by traps caused by lattice defects or doping in the buffer layer 202 can be sufficiently neutralized, the speed of separating the electrons from the buffer layer is increased, the saturation current of the semiconductor device is sufficiently increased, and the dynamic on-resistance of the semiconductor device is reduced.
Alternatively, with continued reference to FIG. 2, the P-type material layer 40 extends to a height L2, where L2 ≧ 5 μm, in the direction perpendicular to the substrate 10, i.e., the Y-direction as depicted in the figure.
Illustratively, the extension length of the P-type material layer 40 in the Y direction is reasonably set, so that the P-type material layer 40 can be ensured to contain a sufficient number of holes, the sufficient number of holes can be ensured to be injected into the buffer layer 202, electrons bound by traps caused by lattice defects or doping in the buffer layer 202 can be sufficiently neutralized, the speed of separating the electrons from the buffer layer is increased, the saturation current of the semiconductor device is sufficiently increased, and the dynamic on-resistance of the semiconductor device is reduced.
Alternatively, as shown in fig. 2, the upper surface of the P-type material layer 40 is higher than the lower surface of the drain electrode 33 along the direction perpendicular to the substrate 10, i.e., the Y direction in the figure; alternatively, the upper surface of the P-type material layer 40 is lower than the lower surface of the drain electrode 33; alternatively, the upper surface of the P-type material layer 40 is flush with the lower surface of the drain electrode 33. The embodiment of the present invention defines the relative position relationship between the upper surface of the P-type material layer 40 and the lower surface of the drain electrode 33, and fig. 2 illustrates only the case where the upper surface of the P-type material layer 40 is lower than the lower surface of the drain electrode 33. The embodiment of the invention only needs to ensure the electrical connection relationship between the P-type material layer 40 and the drain 33, and ensure that the extension height of the P-type material layer 40 is greater than or equal to 5 μm in the direction perpendicular to the substrate 10, so as to ensure that a sufficient number of holes can be injected into the buffer layer 202, and fully neutralize the electrons bound by the traps caused by lattice defects or doping in the buffer layer 202.
Alternatively, as shown with continued reference to fig. 2, the upper surface of the P-type material layer 40 is flush with or lower than the upper surface of the cap layer 205 in a direction perpendicular to the substrate 10, i.e., in the Y direction as shown in the figure. The relative position relationship between the upper surface of the P-type material layer 40 and the upper surface of the cap layer 205 is not limited in the embodiment of the present invention, and fig. 2 only illustrates that the upper surface of the P-type material layer 40 is lower than the upper surface of the cap layer 205. The embodiment of the invention only needs to ensure that the extension height of the P-type material layer 40 is greater than or equal to 5 μm in the direction vertical to the substrate 10, so as to ensure that a sufficient number of holes can be injected into the buffer layer 202, and electrons bound by traps caused by lattice defects or doping in the buffer layer 202 are fully neutralized.
Alternatively, the source electrode 31, the gate electrode 32 and the drain electrode 33 may be located on the surface of the cap layer 205 or inside the cap layer 205; or the source electrode 31, the gate electrode 32 and the drain electrode 33 penetrate through the cap layer 205 and are positioned on the surface of the barrier layer 204 or positioned inside the barrier layer 204; or the source electrode 31, the gate electrode 32 and the drain electrode 33 penetrate through the cap layer 205 and the barrier layer 204 and are located on the surface of the channel layer 203 or located inside the channel layer 203, the relative position relationship between the source electrode 31, the gate electrode 32 and the drain electrode 33 and the cap layer 205 and the barrier layer 204 and the expected channel layer 203 is not limited in the embodiment of the invention, fig. 2 only illustrates the case where the source electrode 31, the gate electrode 32 and the drain electrode 33 penetrate through the cap layer 205, the source electrode 31 and the drain electrode are located on the surface of the barrier layer 204, the gate electrode 32 is a T-shaped gate, and a part of the source electrode 31, the gate electrode 32 and the drain electrode are located inside the barrier layer 204.
Alternatively, with continued reference to fig. 1, the P-type material layer 40 extends along the same direction parallel to the plane of the substrate 10 and perpendicular to the direction in which the gate 32 points toward the drain 33, i.e., along the Z-direction shown in the figure, as the extension of the drain 33.
Illustratively, in the Z direction shown in fig. 1, the P-type material layer 40 is arranged to have the same extension length as that of the drain electrode 33, so as to ensure that the P-type material layer 40 at any position can inject holes into the buffer layer 202 under the forward bias provided by the drain electrode 33, neutralize the electrons trapped by the traps caused by lattice defects or doping in the buffer layer, and improve the speed of releasing the electrons from the buffer layer.
Alternatively, the P-type material layer 40 may be made of a material selected from the group consisting of GaN, AlN, AlGaN, InGaN, and GaNAsOne kind of the compound is used; the doping element of the P-type material layer 40 may include at least one of Mg and Zn; the P-type material layer 40 has a doping concentration C, of which 1 x 1016≤C≤5*1018(ii) a Wherein the ion concentration of the upper surface of the buffer layer 202 in contact with the P-type material layer 40 is greater than or equal to 1 x 1016。
Illustratively, the peak doping concentration of the P-type material layer 40 is located at a portion of the P-type material layer 40 corresponding to the channel layer 203 or the buffer layer 202, and the ion concentration of the upper surface of the buffer layer 202 is greater than or equal to 1 × 1016The sufficient number of holes can be injected into the buffer layer 202, electrons bound by traps caused by lattice defects or doping in the buffer layer 202 are sufficiently neutralized, the speed of separating the electrons from the buffer layer is increased, the saturation current of the semiconductor device is sufficiently increased, and the dynamic on-resistance of the semiconductor device is reduced.
With continued reference to fig. 2, the cross-sectional shape of the P-type material layer 40 may include a rectangle, a trapezoid or an inverted trapezoid, the cross-sectional shape of the P-type material layer 40 is not limited by the embodiment of the present invention, and fig. 2 only illustrates the rectangle of the cross-sectional shape of the P-type material layer 40 as an example.
Fig. 3 is a schematic top view of another semiconductor device provided in an embodiment of the present invention, and fig. 4 is a schematic cross-sectional view of the semiconductor device provided in fig. 3 along a sectional line B-B', as shown in fig. 3 and fig. 4, the semiconductor device provided in an embodiment of the present invention may further include a P-type ohmic contact metal layer 50 located on a side of the P-type material layer 40 away from the substrate 10, where the P-type ohmic contact metal layer 50 forms an ohmic contact with the P-type material layer 40; the P-type ohmic contact metal layer 50 is electrically connected to the drain electrode 33.
Illustratively, the P-type ohmic contact metal layer 50 is located on the side of the P-type material layer 40 away from the substrate 10, and forms ohmic contact with the P-type material layer 40; meanwhile, the P-type ohmic contact metal layer 50 is electrically connected with the drain electrode 33, so that the P-type material layer 40 and the drain electrode 33 are ensured to form an electrical connection relationship, the P-type material layer 40 is ensured to inject holes into the buffer layer 202 under the action of forward voltage provided by the drain electrode 33, electrons bound by traps caused by lattice defects or doping in the buffer layer are neutralized, and the speed of separating the electrons from the buffer layer is improved.
Optionally, with continued reference to fig. 3 and 4, the contact length of the P-type ohmic contact metal layer 50 and the P-type material layer 40 along the direction from the gate 32 to the drain 33, that is, along the X direction shown in fig. 3 and 4, along the direction from the gate 32 to the drain 33 is L3, wherein L3 ≧ 1 μm; in the plane of the upper surface of the P-type material layer 40, the contact area between the P-type ohmic contact metal layer 50 and the P-type material layer 40 is S, wherein S is greater than or equal to 1 μm by 10 μm.
Illustratively, because the P-type ohmic contact metal layer 50 is electrically connected with the drain 33, and the contact length and the contact area between the P-type ohmic contact metal layer 50 and the P-type material layer 40 are reasonably set, the P-type ohmic contact metal layer 50 and the P-type material layer 40 can be ensured to be in full contact, a sufficient number of holes in the P-type material layer 40 can be ensured to be fully injected into the buffer layer 202, electrons bound by traps caused by lattice defects or doping in the buffer layer 202 are fully neutralized, the speed of separating the electrons from the buffer layer is increased, the saturation current of the semiconductor device is fully increased, and the dynamic on-resistance of the semiconductor device is reduced.
Optionally, the P-type ohmic contact metal layer 50 may completely cover the P-type material layer 40, or partially cover the P-type material layer 40 at the side of the P-type material layer 40 away from the drain 33, and fig. 3 and 4 only illustrate an example that the P-type ohmic contact metal layer 50 partially covers the P-type material layer 40 at the side of the P-type material layer 40 away from the drain 33.
Optionally, the material of the P-type layer ohmic contact metal layer 50 may include one or a combination of more of Ni, Ti, Al, Au, and the like, and the material of the drain 33 may also include one or a combination of more of Ni, Ti, Al, Au, and the like, but the material of the P-type layer ohmic contact metal layer 50 is different from the material of the drain 33, which may be embodied that when both the P-type layer ohmic contact metal layer 50 and the drain 33 include only one metal, the metal types are different; when the P-type layer ohmic contact metal layer 50 and the drain electrode 33 each include a plurality of metals, the percentage content of each metal is different. This is because the P-type ohmic contact metal layer 50 forms ohmic contact with the P-type material layer 40, and the drain electrode 33 forms ohmic contact with the multilayer semiconductor layer 20, and because the P-type material layer 40 and the multilayer semiconductor layer 20 are made of different materials, the material of the P-type ohmic contact metal layer 50 and the material of the drain electrode 33 are made of different materials in order to ensure that the P-type ohmic contact metal layer 50 and the P-type material layer 40 have good ohmic contact performance, and the drain electrode 33 and the multilayer semiconductor layer 20 have good ohmic contact performance.
Fig. 5 is a schematic top view diagram of another semiconductor device according to an embodiment of the present invention, and fig. 6 is a schematic cross-sectional view taken along a sectional line C-C' of the schematic top view diagram provided in fig. 5, as shown in fig. 5 and fig. 6, in the semiconductor device according to an embodiment of the present invention, when the upper surface of the P-type material layer 40 is flush or approximately flush with the lower surface of the gate 33, the drain 33 may further extend to a predetermined distance L4 toward the side of the P-type material layer 40 along the direction from the gate 32 toward the drain 33, where L4/L1 is 20% or less.
For example, as shown in fig. 5 and 6, when the upper surface of the P-type material layer 40 is flush or approximately flush with the lower surface of the drain electrode 33, the drain electrode 33 may further extend to a predetermined distance toward the P-type material layer 40 along the direction from the gate electrode 32 toward the drain electrode 33, and the drain electrode 33 forms a schottky contact with the P-type material layer 40. However, it is required to ensure that L4/L1 is less than or equal to 20%, prevent the P-type material layer 40 from being exhausted by the schottky junction, ensure that a sufficient number of holes in the P-type material layer 40 can be fully injected into the buffer layer 202, fully neutralize electrons bound by traps caused by lattice defects or doping in the buffer layer 202, improve the speed of separating the electrons from the buffer layer, fully improve the saturation current of the semiconductor device, and reduce the dynamic on-resistance of the semiconductor device.
It should be understood that the embodiment of the invention improves the problems of low saturation current and high dynamic on-resistance of the semiconductor device from the viewpoint of the structure of the semiconductor device. The semiconductor device includes, but is not limited to: a High power gallium nitride High Electron Mobility Transistor (HEMT) operating in a High voltage and High current environment, a Silicon-On-Insulator (SOI) structure Transistor, a gallium arsenide (GaAs) based Transistor, a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), a Metal-Insulator-Semiconductor Field Effect Transistor (Metal-Insulator-Semiconductor Transistor, MISFET), a Double Heterojunction Field Effect Transistor (dhjunction), a Junction-Field-Effect Transistor (JFET), a Metal-Semiconductor Field Effect Transistor (Metal-Semiconductor-Insulator-Semiconductor Field Effect Transistor, JFET), a Metal-Semiconductor Field Effect Transistor (Metal-Semiconductor-Insulator-Semiconductor Field Effect Transistor, Metal-Semiconductor Field Effect Transistor, Heterojunction Field Effect Transistor, JFET), MISHFET for short) or other field effect transistors.
Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, fig. 7 is a schematic flow chart of the method for manufacturing the semiconductor device according to the embodiment of the present invention, and fig. 8 to 11 are schematic structural diagrams of steps of the method for manufacturing the semiconductor device according to the embodiment of the present invention, as shown in fig. 7 to 11, the method for manufacturing the semiconductor device according to the embodiment of the present invention may include:
and S110, providing a substrate.
Fig. 8 is a schematic structural diagram of a prepared substrate 10 according to an embodiment of the present invention, and as shown in fig. 8, the material of the substrate 10 may be one or a combination of sapphire, silicon carbide, silicon, gallium arsenide, gallium nitride, or aluminum nitride, and may also be other materials suitable for growing gallium nitride. The substrate 10 may be fabricated by atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal organic vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical chemical vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.
S120, preparing a multilayer semiconductor layer on one side of the substrate, wherein the multilayer semiconductor layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate; a source electrode preparation area, a grid electrode preparation area and a drain electrode preparation area are formed on the multilayer semiconductor layer, and the grid electrode preparation area is located between the source electrode preparation area and the drain electrode preparation area.
Illustratively, a multilayer semiconductor layer is located on the substrate side, and the multilayer semiconductor layer may be specifically a semiconductor material of a III-V compound.
As shown in fig. 9, preparing the multilayer semiconductor layer 20 on the substrate 10 side may include:
preparing a nucleation layer 201 on one side of the substrate 10;
preparing a buffer layer 202 on the side of the nucleation layer 201 far away from the substrate 10;
preparing a channel layer 203 on a side of the buffer layer 202 away from the nucleation layer 201;
preparing a barrier layer 204 on the side of the channel layer 203 far away from the buffer layer 202, and forming two-dimensional electron gas between the barrier layer 204 and the channel layer 203;
a cap layer 205 is fabricated on the side of the barrier layer 204 remote from the channel 203 layer.
With continued reference to fig. 9, a source preparation region 206, a gate preparation region 207, and a drain preparation region 208 are formed on the multilayered semiconductor layer 20, the gate preparation region 207 being located between the source preparation region 206 and the drain preparation region 208.
S130, preparing a P-type material layer in the multilayer semiconductor layer and on one side, far away from the grid electrode preparation area, of the drain electrode preparation area, wherein the lower surface of the P-type material layer extends to the surface of one side, close to the channel layer, of the buffer layer or the lower surface of the P-type material layer extends to the inside of the buffer layer.
As shown in fig. 10, the P-type material layer 40 is located in the multi-layer semiconductor layer 20 and on the side of the drain electrode 33 away from the gate electrode 32, and the lower surface of the P-type material layer 40 extends to the surface of the buffer layer 202 on the side close to the channel layer 203 or the lower surface of the P-type material layer 40 extends to the inside of the buffer layer 202.
S140, preparing a source electrode in the source electrode preparation area, preparing a grid electrode in the grid electrode preparation area, and preparing a drain electrode in the drain electrode preparation area, wherein the drain electrode is electrically connected with the P-type material layer.
As shown in fig. 11, the source electrode 31 is formed in the source preparation region 206, the gate electrode 32 is formed in the gate preparation region 207, and the drain electrode 33 is formed in the drain preparation region 208, with the gate electrode 32 being located between the source electrode 31 and the drain electrode 33.
The P-type material layer 40 is electrically connected to the drain 33 (not shown in the figure), so that when a positive voltage is applied to the drain 33, the P-type material layer 40 electrically connected to the drain 33 can inject holes into the buffer layer 202, and the electrons bound by traps caused by lattice defects or doping in the buffer layer 202 are neutralized by the holes, so that the speed of separating the electrons from the buffer layer 202 is increased, the saturation current of the semiconductor device can be increased, the dynamic on-resistance of the semiconductor device is reduced, and the performance of the semiconductor device is improved.
To sum up, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the P-type material layer is manufactured in the multilayer semiconductor layer and on the side of the drain electrode manufacturing region away from the gate electrode manufacturing region, the lower surface of the P-type material layer extends to the surface of the buffer layer close to the channel layer or the lower surface of the P-type material layer extends to the inside of the buffer layer, and the P-type material layer is electrically connected to the drain electrode, so that a hole is injected into the buffer layer by the P-type material layer under forward bias, electrons trapped by traps caused by lattice defects or doping in the buffer layer are neutralized, the speed of separating electrons from the buffer layer is increased, the saturation current of the semiconductor device is increased, the dynamic on-resistance of the semiconductor device is reduced, and the performance of the semiconductor device is improved.
Fig. 12 is a schematic flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention, and as shown in fig. 12, the method for manufacturing a semiconductor device according to an embodiment of the present invention may include:
s210, providing a substrate.
Illustratively, the process of preparing the substrate 10 is continued with reference to FIG. 8.
S220, preparing a multilayer semiconductor layer on one side of the substrate, wherein the multilayer semiconductor layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate; a source electrode preparation area, a grid electrode preparation area and a drain electrode preparation area are formed on the multilayer semiconductor layer, and the grid electrode preparation area is located between the source electrode preparation area and the drain electrode preparation area.
Illustratively, the process of preparing the multi-layer semiconductor layer 20 is continued with reference to fig. 9.
And S230, sequentially etching the barrier layer and the channel layer on one side of the drain electrode preparation area, which is far away from the grid electrode preparation area, to the upper surface of the buffer layer or the inside of the buffer layer to obtain an etched part.
Fig. 13 is a schematic structural diagram of etching the barrier layer and the channel layer on the side of the drain preparation region away from the gate preparation region to the upper surface of the buffer layer or the inside of the buffer layer according to the embodiment of the present invention, and fig. 13 illustrates an example of etching to the upper surface of the buffer layer. For example, during the etching process, a photoresist may be used to perform a coverage protection on a portion that does not need to be etched, and a portion that is not covered with the photoresist may be etched, and the photoresist may be removed after the etching is finished.
S240, growing a P-type material on the etched part to obtain a P-type material layer.
Fig. 14 is a schematic structural diagram of a P-type material layer obtained by growing a P-type material according to an embodiment of the present invention, and as shown in fig. 14, a lower surface of the P-type material layer 40 extends to a surface of the buffer layer 202 on a side close to the channel layer 203. The P-type material layer 40 may be GaN, or a material having a relatively close lattice constant, such as AlN or AlGaN. The growth height of the P-type material 40 layer is not higher than the surface height of the cap layer 205 and is not lower than 5 μm to ensure the concentration of injected holes. The doping type of the P-type material layer 40 is P-type, the doping elements can be Mg, Zn, etc., and the doping concentration is C, wherein 1 x 1016≤C≤5*1018. In the actual preparation process, before growing the P-type material, the other areas can be covered with SiN or SiO2 as a mask, and after the growth is completed, the mask is removed.
S250, preparing a source electrode in the source electrode preparation area, preparing a grid electrode in the grid electrode preparation area, and preparing a drain electrode in the drain electrode preparation area, wherein the drain electrode is electrically connected with the P-type material layer.
For an exemplary process of making the source 31, gate 32 and drain 33 electrodes and the drain 33 electrode electrically connected to the P-type material layer 40, please continue with fig. 11.
To sum up, according to the method for manufacturing a semiconductor device provided by the embodiment of the present invention, the P-type material layer is manufactured in the multilayer semiconductor layer at the side of the drain electrode away from the gate electrode through the etching process, the lower surface of the P-type material layer extends to the surface of the buffer layer at the side close to the channel layer or extends into the buffer layer, and the P-type material layer is electrically connected to the drain electrode, so that a hole can be injected into the buffer layer under the action of forward bias of the drain electrode, electrons bound by traps due to lattice defects or doping in the buffer layer are neutralized, the speed of separating the electrons from the buffer layer is increased, the saturation current of the semiconductor device is increased, the dynamic on-resistance of the semiconductor device is reduced, and the performance of the semiconductor device is improved.
Fig. 15 is a schematic flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present invention, and as shown in fig. 15, the method for manufacturing a semiconductor device according to the embodiment of the present invention may include:
s310, providing a substrate.
Illustratively, the process of preparing the substrate 10 is continued with reference to FIG. 8.
S320, preparing a multilayer semiconductor layer on one side of the substrate, wherein the multilayer semiconductor layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate; a source electrode preparation area, a grid electrode preparation area and a drain electrode preparation area are formed on the multilayer semiconductor layer, and the grid electrode preparation area is located between the source electrode preparation area and the drain electrode preparation area.
Illustratively, the process of preparing the multi-layer semiconductor layer 20 is continued with reference to fig. 9.
S330, performing ion implantation on the multilayer semiconductor layer at one side of the drain electrode preparation area, which is far away from the grid electrode preparation area, to obtain a P-type material layer.
Fig. 16 is a schematic structural diagram of ion implantation of the multi-layer semiconductor layer at the side of the drain preparation region far from the gate preparation region, where the implanted ions may be Mg, Zn, etc. to ensure that the ion concentration peak after implantation is at the channel layer 203 portion or the buffer layer 202 portion, and the ion implantation region has a doping concentration higher than that at the surface of the buffer layer 2021*1016. For example, during the ion implantation process, a photoresist may be used to perform a coverage protection on a portion that does not need the ion implantation, perform the ion implantation on a portion that is not covered by the photoresist, and remove the photoresist after the ion implantation is finished.
S340, preparing a source electrode in the source electrode preparation area, preparing a grid electrode in the grid electrode preparation area, and preparing a drain electrode in the drain electrode preparation area, wherein the drain electrode is electrically connected with the P-type material layer.
For an exemplary process of making the source 31, gate 32 and drain 33 electrodes and the drain 33 electrode electrically connected to the P-type material layer 40, please continue with fig. 11.
In summary, according to the method for manufacturing a semiconductor device provided by the embodiment of the present invention, the P-type material layer is manufactured in the multilayer semiconductor layer at the side of the drain electrode away from the gate electrode through an ion implantation process, the lower surface of the P-type material layer extends to the surface of the buffer layer at the side close to the channel layer or extends into the buffer layer, and the P-type material layer is electrically connected to the drain electrode, so that a hole can be injected into the buffer layer under the action of forward bias of the drain electrode, electrons bound by traps caused by lattice defects or doping in the buffer layer are neutralized, the speed of separating the electrons from the buffer layer is increased, the saturation current of the semiconductor device is increased, the dynamic on-resistance of the semiconductor device is reduced, and the performance of the semiconductor device is improved.
Fig. 17 is a schematic flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present invention, and as shown in fig. 17, the method for manufacturing a semiconductor device according to the embodiment of the present invention may include:
s410, providing a substrate.
Illustratively, the process of preparing the substrate 10 is continued with reference to FIG. 8.
S420, preparing a multilayer semiconductor layer on one side of the substrate, wherein the multilayer semiconductor layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate; a source electrode preparation area, a grid electrode preparation area and a drain electrode preparation area are formed on the multilayer semiconductor layer, and the grid electrode preparation area is located between the source electrode preparation area and the drain electrode preparation area.
Illustratively, the process of preparing the multi-layer semiconductor layer 20 is continued with reference to fig. 9.
S430, preparing a P-type material layer on one side, away from the grid electrode preparation area, of the drain electrode preparation area in the multilayer semiconductor layer, wherein the lower surface of the P-type material layer extends to the surface of one side, close to the channel layer, of the buffer layer or the lower surface of the P-type material layer extends to the inside of the buffer layer.
Exemplary, the process of preparing the P-type material layer 40 is illustrated with continued reference to fig. 10.
S440, preparing a P-type layer ohmic contact metal layer on one side, far away from the substrate, of the P-type material layer, wherein the P-type layer ohmic contact metal layer and the P-type material layer form ohmic contact.
Fig. 18 is a schematic structural diagram of the P-type ohmic contact metal layer prepared according to the embodiment of the present invention, and as shown in fig. 18, a P-type ohmic contact metal layer 50 is prepared on a side of the P-type material layer 40 away from the substrate 10, and the P-type ohmic contact metal layer 50 and the P-type material layer 40 form ohmic contact. The P-type ohmic contact metal layer 50 can completely cover the P-type material layer 40, or can partially cover the P-type material layer 40 at the side far away from the drain electrode 33, and the contact length of the P-type ohmic contact metal layer 50 and the P-type material layer 40 is greater than or equal to 1 μm; in the plane of the upper surface of the P-type material layer 40, the contact area between the P-type ohmic contact metal layer 50 and the P-type material layer 40 is greater than or equal to 1 μm by 10 μm.
S450, preparing a source electrode in the source electrode preparation area, preparing a grid electrode in the grid electrode preparation area, and preparing a drain electrode in the drain electrode preparation area, wherein the drain electrode is electrically connected with the P-type ohmic contact metal layer.
Fig. 19 is a schematic structural diagram of the embodiment of the invention for preparing the source, the gate, the drain and the drain electrically connected to the P-type ohmic contact metal layer, as shown in fig. 19, the P-type ohmic contact metal layer 50 is electrically connected to the drain 33, so as to ensure that the P-type material layer 40 and the drain 33 form an electrical connection relationship, and ensure that the P-type material layer 40 can inject holes into the buffer layer 202 under the action of the forward voltage provided by the drain 33, neutralize the electrons trapped by the traps caused by lattice defects or doping in the buffer layer, and improve the speed of the electrons escaping from the buffer layer.
In summary, according to the method for manufacturing the semiconductor device provided by the embodiment of the invention, the P-type material layer and the P-type ohmic contact metal layer are manufactured on the side, away from the gate, of the drain in the multilayer semiconductor layer, the P-type ohmic contact metal layer is electrically connected with the drain, and the lower surface of the P-type material layer extends to the surface of the buffer layer, close to the channel layer, or extends into the buffer layer, so that a hole can be injected into the buffer layer under the action of forward bias of the drain, electrons bound by traps caused by lattice defects or doping in the buffer layer are neutralized, the speed of separating the electrons from the buffer layer is increased, the saturation current of the semiconductor device is increased, the dynamic on-resistance of the semiconductor device is reduced, and the performance of the semiconductor device is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (13)
1. A semiconductor device, comprising:
a substrate;
the multilayer semiconductor layer is positioned on one side of the substrate and comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate;
the source electrode, the grid electrode and the drain electrode are positioned on one side, far away from the substrate, of the multilayer semiconductor layer, and the grid electrode is positioned between the source electrode and the drain electrode;
the P-type material layer is positioned in the multilayer semiconductor layer and positioned on one side, far away from the grid, of the drain electrode, the lower surface of the P-type material layer extends to the surface, close to one side of the channel layer, of the buffer layer or the lower surface of the P-type material layer extends to the inside of the buffer layer, the P-type material layer is electrically connected with the drain electrode, and under the forward bias, the P-type material layer injects holes into the buffer layer.
2. The semiconductor device of claim 1, wherein the P-type material layer has an extension length L1 along the direction from the gate to the drain, wherein L1 ≧ 1 μm.
3. The semiconductor device of claim 1, wherein the P-type material layer has an extension height of L2 in a direction perpendicular to the substrate, wherein L2 ≧ 5 μm.
4. The semiconductor device according to claim 1, wherein the P-type material layer has the same extension as that of the drain electrode in a direction parallel to a plane of the substrate and perpendicular to a direction in which the gate electrode is directed to the drain electrode.
5. The semiconductor device according to claim 1, wherein an upper surface of the P-type material layer is higher than a lower surface of the drain electrode; or the upper surface of the P-type material layer is lower than the lower surface of the drain electrode; or the upper surface of the P-type material layer is flush with the lower surface of the drain electrode.
6. The semiconductor device according to claim 1, further comprising a P-type layer ohmic contact metal layer on a side of the P-type material layer remote from the substrate, the P-type layer ohmic contact metal layer forming ohmic contact with the P-type material layer;
the P-type layer ohmic contact metal layer is electrically connected with the drain electrode.
7. The semiconductor device as claimed in claim 6, wherein the contact length of the P-type ohmic contact metal layer and the P-type material layer in the direction from the gate to the drain is L3, wherein L3 ≧ 1 μm;
and in the plane of the upper surface of the P-type material layer, the contact area of the P-type ohmic contact metal layer and the P-type material layer is S, wherein S is more than or equal to 1 mu m and 10 mu m.
8. The semiconductor device according to claim 1, wherein the material of the P-type material layer comprises at least one of GaN, AlN, AlGaN, InGaN, and GaNAs;
the doping element of the P-type material layer comprises at least one of Mg and Zn.
9. The semiconductor device of claim 8, wherein the P-type material layer has a doping concentration of C, 1 x 1016≤C≤5*1018。
10. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
preparing a multilayer semiconductor layer on one side of the substrate, wherein the multilayer semiconductor layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially positioned on one side of the substrate; a source electrode preparation area, a grid electrode preparation area and a drain electrode preparation area are formed on the multilayer semiconductor layer, and the grid electrode preparation area is positioned between the source electrode preparation area and the drain electrode preparation area;
preparing a P-type material layer in the multilayer semiconductor layer at one side of the drain electrode preparation area far away from the grid electrode preparation area, wherein the lower surface of the P-type material layer extends to the surface of one side of the buffer layer close to the channel layer or the lower surface of the P-type material layer extends to the inside of the buffer layer;
preparing a source electrode in the source electrode preparation area, preparing a grid electrode in the grid electrode preparation area, preparing a drain electrode in the drain electrode preparation area, electrically connecting the drain electrode with the P-type material layer, and injecting holes into the buffer layer by the P-type material layer under forward bias.
11. The method of manufacturing a semiconductor device according to claim 10, wherein the preparing a P-type material layer in the multilayer semiconductor layer on a side of the drain preparation region remote from the gate preparation region comprises:
sequentially etching the barrier layer and the channel layer on one side of the drain electrode preparation area, which is far away from the grid electrode preparation area, to the upper surface of the buffer layer or the inside of the buffer layer to obtain an etched part;
and growing a P-type material on the etching part to obtain a P-type material layer.
12. The method of manufacturing a semiconductor device according to claim 10, wherein the preparing a P-type material layer in the multilayer semiconductor layer on a side of the drain preparation region remote from the gate preparation region comprises:
and carrying out ion implantation on the multilayer semiconductor layer at one side of the drain electrode preparation area, which is far away from the grid electrode preparation area, so as to obtain a P-type material layer.
13. The method of claim 10, further comprising, after preparing a P-type material layer in the multilayer semiconductor layer on a side of the drain preparation region away from the gate preparation region:
preparing a P-type layer ohmic contact metal layer on one side of the P-type material layer, which is far away from the substrate, wherein the P-type layer ohmic contact metal layer and the P-type material layer form ohmic contact;
the drain electrode is electrically connected with the P-type material layer and comprises:
and the drain electrode is electrically connected with the P-type layer ohmic contact metal layer.
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| CN102194866A (en) * | 2010-03-02 | 2011-09-21 | 松下电器产业株式会社 | Field effect transistor |
| CN207664048U (en) * | 2016-11-17 | 2018-07-27 | 半导体元件工业有限责任公司 | Semiconductor devices |
| JP2018125500A (en) * | 2017-02-03 | 2018-08-09 | サンケン電気株式会社 | Semiconductor device and method for manufacturing the same |
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| CN102194866A (en) * | 2010-03-02 | 2011-09-21 | 松下电器产业株式会社 | Field effect transistor |
| CN207664048U (en) * | 2016-11-17 | 2018-07-27 | 半导体元件工业有限责任公司 | Semiconductor devices |
| JP2018125500A (en) * | 2017-02-03 | 2018-08-09 | サンケン電気株式会社 | Semiconductor device and method for manufacturing the same |
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