JP2009124002A - Gan-based semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a GaN-based semiconductor device that is reducible in element size by decreasing bonding pads and improved in resistance by preventing avalanche destruction, and to provide a method of manufacturing the same. <P>SOLUTION: The GaN-based semiconductor device 20 has a source electrode 31 and a drain electrode 32 configured such that a current flows between the two electrodes through an active layer 25 in an on-state, a gate electrode 33, and a reverse-surface electrode 34. A groove 27 which is deep enough to reach a silicon substrate 21 from the top surface side of the active layer 25 is formed in a portion of the active layer 25 which forms the source electrode 31. In the groove 27, the source electrode 31 which electrically connects the top surface of the active layer 25 to the silicon substrate 21 and an insulating layer 70 which insulates a portion of the source electrode 31 in the groove 27 from the active layer 25 are formed. The source electrode 31 and insulating layer 70 are thus formed in the groove 27, so it becomes easier to form the groove 27 and insulating film 70. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a GaN-based semiconductor device such as a GaN-based heterojunction field effect transistor and a method for manufacturing the same.

  In general, a lateral FET element requires three bonding pads, which increases the size of the element. Therefore, conventionally, in the GaAs-FET, there is a technique of digging a hole (via hole) from the back surface of the substrate and electrically connecting the back electrode and the source electrode to reduce one bonding pad (for example, FIG. 2).

  However, in such a conventional GaAs-FET, the withstand voltage drops, and there is a technique of covering the via hole portion with an insulating film as a countermeasure (see, for example, FIG. 1 of Patent Document 1). This semiconductor device has a source electrode (first conductor) on the surface of a semiconductor substrate such as GaAs, a back electrode (second conductor) on the back surface of the semiconductor substrate, and the source electrode in the semiconductor substrate. And a via hole connecting the back electrode, the via hole is filled with a third conductor, and an insulating film is provided between the third conductor in the via hole and the semiconductor substrate.

  In addition, GaN-based semiconductor devices have a larger band gap energy than GaAs-based materials, and have high heat resistance and excellent high-temperature operation. Therefore, the field effect using these materials, particularly GaN / AlGaN-based semiconductors. Development of transistors (Field Effect Transistors: FETs) is underway.

Conventionally, a GaN-based HEMT (High Electron Mobility Transistor) composed of a gallium nitride-based compound semiconductor is known as a GaN-based semiconductor device (see, for example, Patent Document 2).
JP-A-5-21474 JP 2006-173582 A

  Incidentally, when the conventional technique disclosed in Patent Document 1 is applied to a GaN-based semiconductor device as it is, there are the following problems.

  (1) In an epitaxial wafer in which an active layer made of a GaN-based semiconductor is formed on a silicon (Si) substrate, since the strain is large, a substrate thickness of 500 μm or more is necessary to suppress warpage and cracks. It is very difficult to dig a hole.

  (2) Even if a via hole is dug from the back surface of the substrate, the depth of the via hole is 500 μm or more with respect to 10 μm, and the insulating film formed between the conductor in the via hole and the semiconductor substrate It is difficult to form a film deep into the via hole.

  The present invention has been made in view of the above-described conventional problems. The object of the present invention is to reduce the number of bonding pads, reduce the element size, and suppress the avalanche breakdown, thereby improving reliability. An object of the present invention is to provide an improved GaN-based semiconductor device and a method for manufacturing the same.

  In order to solve the above-described problem, a GaN-based semiconductor device according to the first aspect of the present invention includes a P-type silicon (Si) substrate, an active layer made of a GaN-based semiconductor formed on the substrate, A first electrode and a second electrode through which an electric current flows through the active layer in a state, and a back electrode formed on the back surface of the substrate, wherein the active layer has a surface from the surface side of the active layer. A groove having a depth reaching the silicon substrate is formed, and in the groove, the first electrode that electrically connects the surface of the active layer and the silicon substrate, the first electrode, and the active layer, And an insulating layer that electrically insulates.

  According to this, since the first electrode electrically connects the surface of the active layer and the silicon substrate, the first electrode is electrically connected to the back electrode via the silicon substrate, and the entire back electrode is the first electrode. It becomes a bonding pad for an electrode. This eliminates the need for the bonding pads for the first electrode and reduces the number of bonding pads, thereby reducing the element size (chip area). In addition, since the portion of the first electrode in the groove is not electrically in contact with the active layer by the insulating layer, avalanche breakdown due to injection of electrons from the first electrode in the groove to the active layer is suppressed. Is done.

  In addition, a groove having a depth reaching the silicon substrate from the surface side of the active layer is formed in the portion of the active layer where the first electrode is formed, and the surface of the active layer and the silicon substrate are electrically connected in this groove. Since the first electrode and the insulating layer that insulates the portion in the groove of the first electrode from the active layer are formed, the groove and the insulating film can be easily formed.

  Therefore, it is possible to obtain a GaN-based semiconductor device in which the bonding pad is reduced, the element size can be reduced, and the avalanche breakdown is suppressed to improve the reliability.

  The GaN-based semiconductor device according to a second aspect of the present invention is characterized in that a metal that is in ohmic contact with both the silicon substrate and the active layer is used for the first electrode.

  Thereby, a low on-resistance can be obtained, and the reliability can be improved while maintaining the advantage of the low on-resistance of the GaN-based semiconductor element.

  According to a third aspect of the present invention, in the GaN-based semiconductor device, the second electrode is formed on at least a part of the upper surface of the interlayer insulating film formed on the active layer and inside the through hole of the interlayer insulating film. It is electrically connected to the extending pad electrode.

  According to this, since the current density of the electrode portion is reduced, the occurrence of electromigration can be suppressed, and the reliability is further improved.

  According to a fourth aspect of the present invention, the GaN-based semiconductor device further includes a p-GaN layer and an n-GaN layer between the silicon substrate and the active layer.

  Although the avalanche breakdown due to the injection of electrons from the first electrode in the groove to the active layer can be suppressed by the insulating layer, since a high voltage is applied in the vertical direction of the epitaxial wafer, it is necessary to improve the vertical breakdown voltage of the epitaxial wafer. is there. According to this, since the p-GaN layer and the n-GaN layer are provided between the silicon substrate and the active layer, the depletion layer extends and the breakdown voltage in the vertical direction of the epitaxial wafer is improved.

  A GaN-based semiconductor device according to a fifth aspect of the present invention is a field effect transistor including a source electrode as the first electrode, a drain electrode as the second electrode, and a gate electrode. .

  According to this, a highly reliable GaN-based field effect transistor can be realized while maintaining the advantage of the low on-resistance of the GaN-based semiconductor device.

  According to a sixth aspect of the present invention, in the GaN-based semiconductor device, the field effect transistor includes a first GaN-based semiconductor layer in which the active layer serves as a carrier traveling layer and a second GaN-based semiconductor layer in which the carrier supply layer functions. A heterojunction field effect transistor having a telojunction structure, wherein the groove is formed in a portion of the active layer where the source electrode is formed.

  According to this, a highly reliable GaN-based heterojunction field effect transistor (GaN-based HEMT, also known as GaN-based HFET) can be realized while maintaining the advantage of low on-resistance of the GaN-based semiconductor device.

  The GaN-based semiconductor device according to claim 7, wherein the field effect transistor includes a gate oxide film formed on the active layer, and the gate electrode is formed on the gate oxide film. In the field effect transistor, the groove is formed in a portion of the active layer where the source electrode is formed.

  According to this, a highly reliable GaN-based MOS field effect transistor (GaN-based MOSFET) can be realized while maintaining the advantage of the low on-resistance of the GaN-based semiconductor element.

  A GaN-based semiconductor device according to claim 8 is a cathode electrode as the first electrode that is in ohmic contact with the active layer, and an anode electrode as the second electrode that is in Schottky junction with the active layer, The groove is formed in a portion of the active layer where the cathode electrode is to be formed.

  According to this, a highly reliable GaN-based Schottky diode (GaN-based SBD) can be realized while maintaining the advantage of the low on-resistance of the GaN-based semiconductor element.

  A method of manufacturing a GaN-based semiconductor device according to claim 9 includes a P-type silicon (Si) substrate, an active layer made of a GaN-based semiconductor formed on the substrate, and two electrodes in an on state. A method for manufacturing a GaN-based semiconductor device, comprising: at least two electrodes, a first electrode and a second electrode, through which an electric current flows between the active layers, and a back electrode formed on the back surface of the substrate, Forming a groove having a depth reaching the silicon substrate from the surface side of the active layer in a portion of the active layer where one of the two electrodes is to be formed; and after forming the groove, an insulating film is formed Forming the insulating layer on the entire surface by etching the entire surface of the insulating film by reactive ion etching (RIE), leaving the insulating film only on the inner wall surface of the groove; and On the inside, And forming the one electrode so as to be electrically connected to the surface of the moving layer and the silicon substrate, in that it comprises the features.

  A method for manufacturing a GaN-based semiconductor device according to a tenth aspect of the present invention includes a P-type silicon (Si) substrate, an active layer made of a GaN-based semiconductor formed on the substrate, and two electrodes in an on state. A method for manufacturing a GaN-based semiconductor device, comprising: at least two electrodes, a first electrode and a second electrode, through which an electric current flows between the active layers, and a back electrode formed on the back surface of the substrate, Forming a high-resistance ion-implanted layer by selectively implanting ions in a portion of the active layer where one of the two electrodes is to be formed, and leaving the ion-implanted layer only on the inner wall surface of the groove; Etching the ion implantation layer to a depth reaching the silicon substrate so as to form an insulating layer, and electrically connecting the surface of the active layer and the silicon substrate to the inner surface of the insulating layer. In Serial forming one of the electrodes, characterized in that it comprises a.

  According to the present invention, it is possible to realize a GaN-based semiconductor device in which the bonding pad is reduced, the element size can be reduced, and the reliability is improved by suppressing avalanche breakdown.

  Next, embodiments embodying the present invention will be described with reference to the drawings. In the description of each embodiment, the same parts are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
A GaN-based semiconductor device 20 according to the first embodiment will be described with reference to FIG.

  The GaN-based semiconductor device 20 is configured as a GaN-based heterojunction field effect transistor (GaN-based HEMT, also known as GaN-based HFET).

  The GaN-based semiconductor device 20 includes a P-type silicon (Si) substrate 21 to which a P-type impurity is added, a buffer layer 22 formed on the substrate, and an undoped GaN layer formed on the buffer layer 22. A channel layer (carrier traveling layer) 23 and a carrier supply layer 24 made of undoped AlGaN formed on the channel layer 23 are provided. In FIG. 1, the channel layer 23 and the carrier supply layer 24 are indicated by AlGaN / GaN (24, 23), but the channel layer 23 and the carrier supply layer 24 are the channel layers of the GaN-based semiconductor device 20A shown in FIG. 23 and the carrier supply layer 24. The buffer layer 22 has a laminated structure of AlN and GaN. The buffer layer 22, the channel layer (carrier traveling layer) 23 that is the first GaN semiconductor layer, and the carrier supply layer 24 that is the second GaN semiconductor layer constitute an active layer 25 made of a GaN-based semiconductor.

  In addition, the GaN-based semiconductor device 20 includes a source electrode (S) 31 as a first electrode and a drain electrode 32 (D) as a second electrode through which an electric current flows between the two electrodes via the active layer 25 in an on state. The gate electrode (G) 33 and the back electrode 34 formed on the back surface of the silicon substrate 21 are provided.

  In this GaN-based semiconductor device 20, since the carrier supply layer 24 (undoped AlGaN layer) is heterojunction with the surface of the channel layer (undoped GaN layer) 23, two-dimensional electrons are present at the interface of the bonded portion. A gas (see the two-dimensional electron gas 26 in FIG. 4) is generated. Therefore, the two-dimensional electron gas 26 becomes a carrier and the channel layer 23 becomes conductive.

  Further, in the GaN-based semiconductor device 20, a groove (trench) 27 having a depth reaching the silicon substrate 21 from the surface side of the active layer 25 is formed in a portion of the active layer 25 where the source electrode 31 is formed. The wall surface of the groove 27 is substantially vertical.

  In the groove 27, there are a source electrode 31 that electrically connects the surface of the active layer 25 and the silicon substrate 21, and an insulating layer 70 that insulates a portion of the source electrode 31 in the groove 27 from the active layer 25. Is formed.

  The source electrode 31 is described later on the inner wall surface of the groove 27 having a depth reaching the silicon substrate 21 from the surface of the active layer 25 (the surface of the carrier supply layer 24) to a position where the source electrode 31 contacts the silicon substrate 21 from the surface side. It has a predetermined thickness.

  The source electrode 31 is made of a metal that makes ohmic contact with both the silicon substrate 21 and the active layer 25. For example, the source electrode 31 is a laminated body including a Ti layer that is in contact with the active layer 25 and the silicon substrate 21 and a layer made of an alloy of Al and Si laminated on the Ti layer. The drain electrode 32 is also a laminate including a Ti layer that contacts the carrier supply layer 24 and an alloy of Al and Si laminated on the Ti layer. The gate electrode 33 is, for example, a stacked body of Ni and Au.

  A passivation film 28 is formed between the source electrode 31, the gate electrode 33, and the drain electrode 32 on the surface of the carrier supply layer 24. On this passivation film 28, an interlayer insulating film 29 made of Si nitride (SiN) is formed so as to fill the groove in the source electrode 31. The drain electrode 32 is electrically connected to a pad electrode (drain pad) 30 d formed on a part of the upper surface of the interlayer insulating film 29 formed on the active layer 25 and extending into the through hole 29 a of the interlayer insulating film 29. Yes.

  FIG. 2 shows the upper surface of the GaN-based semiconductor device 20. As shown in FIG. 2, a drain pad 30 d and a gate pad 33 a are formed on the upper surface of the interlayer insulating film 29. The pad electrode 30d is electrically connected to the plurality of combs 32a of the comb-shaped drain electrode 32 through a conductor portion extending inside the through hole 29a. As described above, the pad electrode 30d relaxes the current density by electrically connecting the comb 32a and the comb 32a of the comb-shaped drain electrode 32. On the other hand, the source electrode 31 (a plurality of combs of comb-shaped source electrodes) 31 shown in FIGS. 1 and 2 is electrically connected to a back electrode 34 formed on the back surface of the P-type silicon (Si) substrate 21. Yes. The gate pad 33a is electrically connected to the gate electrode 33 shown in FIG.

The thickness of the Ti layer of the source electrode 31 needs to be between 15 nm and 40 nm in order to obtain a good ohmic contact with the channel layer 23 of the active layer 25. If the thickness of the Ti layer is smaller than 15 nm, the contact resistance (Rc) between the source electrode 31 and the P-type silicon substrate 21 becomes larger than, for example, 10 ⁻⁴ Ωcm ² , which is not preferable. When the thickness of the Ti layer is larger than 40 nm, the contact resistance (Rc) becomes larger than, for example, 10 ⁻⁴ Ωcm ² , which is not preferable.

The P-type impurity concentration of the P-type silicon substrate 21 is 5 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less. If the P-type impurity concentration of the P-type silicon substrate 21 is smaller than 5 × 10 ¹⁹ cm ⁻³ , the contact resistance (Rc) increases, which is not preferable. If the P-type impurity concentration is higher than 1 × 10 ²¹ cm ⁻³ , the crystallinity of the buffer layer 22, the channel layer 23 and the carrier supply layer 24 (active layer 25) is deteriorated, which is not preferable.

  The GaN-based semiconductor device 20 having the above configuration can be manufactured as follows, for example. Here, a method for manufacturing the GaN-based semiconductor device 20 in the case where the insulating layer 70 is formed of an insulating film will be described with reference to FIGS. As the growth apparatus, an MOCVD (Metal Organic Chemical Vapor Deposition) apparatus was used.

(1) First, a P-type silicon substrate 21 is introduced into the MOCVD apparatus, and after evacuating the MOCVD apparatus with a turbo pump until the vacuum degree becomes 1 × 10 ⁻⁶ hPa or less, the vacuum degree is set to 100 hPa. The substrate 21 was heated to 600 ° C. When the temperature is stabilized, the silicon substrate 21 is rotated at 900 rpm, and trimethylaluminum (TMA) as a raw material is introduced into the surface of the silicon substrate 21 at a flow rate of 100 cm ³ / min and ammonia at a flow rate of 12 liter / min. A buffer layer 22 having a laminated structure was grown. The growth time is 4 min and the thickness of the buffer layer 22 is about 50 nm.

(2) Next, the temperature was raised while flowing ammonia at a flow rate of 12 liters / min, and maintained at 1050 ° C., then trimethylgallium (TMG) was 300 cm ³ / min and ammonia was flowed at a flow rate of 12 liters / min. A channel layer (carrier traveling layer) 23 made of a GaN layer was grown by introducing the GaN layer 22. The growth time was 2000 sec and the thickness of the channel layer 23 was 3000 nm.

(3) Next, trimethylaluminum (TMA) to 50 cm ³ / min, trimethyl gallium (TMG) 100 cm ³ / min, the ammonia was introduced at a flow rate 12 liter / min, the carrier supply consisting of Al _0.25 Ga _0.75 N layer Layer 24 was grown. The growth time is 40 sec, and the thickness of the carrier supply layer 24 is 20 nm. In this way, the layer structure shown in FIG. 1 is completed.

  (4) Next, element isolation is performed using chlorine gas or the like.

  (5) Next, a photoresist is applied and patterning is performed to open a portion where the drain electrode 32 is to be formed. Using this patterned photoresist as a mask, a drain electrode 32 made of an alloy film of Ti and Al and Si is formed by a lift-off method.

(6) Next, the photoresist is removed, a SiO ₂ insulating film is formed, and this insulating film is patterned to open a portion where the source electrode 31 is to be formed. Thereafter, in the opening, the active layer 25 is removed by etching to a depth reaching the silicon substrate 21 from the surface side to form a groove 27 having a substantially vertical wall surface (see FIG. 3A).

(7) After the trench 27 is formed, the SiO ₂ insulating film is removed. Thereafter, an insulating film (SiO ₂ ) 71 is formed on the entire surface (see FIG. 3A).

  (8) Next, the entire surface of the insulating film 71 is etched by the reactive ion etching (RIE) method (whole surface anisotropic etching) to leave the insulating film only on the inner wall surface of the groove 27 (FIG. 3). (See (B)). As a result, an insulating layer 70 made of an insulating film is formed on the inner wall surface of the groove 27.

  (9) Next, a photoresist is applied and patterning is performed to open a portion where the source electrode 31 is to be formed. Using this patterned photoresist as a mask, a source electrode 31 made of an alloy film of Ti and Al and Si is formed on the inner surface of the insulating layer 70 and the surface of the active layer 25 by a lift-off method (see FIG. 3C). ). Here, Ti and an alloy film of Al and Si are sequentially deposited, and a source electrode made of a laminate including a Ti layer in contact with the silicon substrate 21 and the active layer 25 and a layer made of an alloy of Al and Si. 31 is formed on the entire inner surface of the insulating layer 70 to the depth reaching the silicon substrate 21 with the above-described predetermined thickness. As a result, the surface of the active layer 25 and the silicon substrate 21 are electrically connected, but the portion in the groove 27 is insulated by the insulating layer 70 and is not in electrical contact with the active layer 25. Is formed in the groove 27.

  (10) Next, the photoresist is removed, and a passivation film 28 is formed on the surface of the carrier supply layer 24.

  (11) Next, the gate electrode 33 forming portion of the passivation film 28 is opened, and Ni and Au are deposited to form the gate electrode 33.

  (12) Next, an interlayer insulating film 29 made of Si nitride (SiN) is deposited on the passivation film 28 so as to fill the groove 27 of the source electrode 31.

  (13) Next, a through hole 29 a is opened at a location corresponding to the drain electrode 32 in the interlayer insulating film 29. Thereafter, a drain pad (pad) 30 d that is electrically connected to the drain electrode 32 is formed on a part of the upper surface of the interlayer insulating film 29 and inside the through hole 29 a.

  (14) Finally, the back electrode 34 is formed on the back surface of the silicon substrate 21.

  Thereby, the GaN-based semiconductor device (GaN-based HEMT) 20 shown in FIG. 1 is completed.

  In this GaN-based semiconductor device 20, in the ON state, a current flows from the drain electrode to the source electrode 31 through the channel layer (carrier traveling layer) 23 of the active layer 25 and further flows in the vertical direction through the source electrode 31. Flows to the back electrode 34 through the silicon substrate 21.

According to 1st Embodiment comprised as mentioned above, there exist the following effects.
Since the source electrode 31 electrically connects the surface of the active layer 25 and the silicon substrate 21, the source electrode 31 is electrically connected to the back electrode 34 through the silicon substrate 21, and the entire back electrode 34 is the source It becomes a bonding pad for the electrode 31. Thereby, the bonding pad of the source electrode 31 becomes unnecessary, and the number of bonding pads is reduced, so that the element size (chip area) can be reduced.

  The portion of the source electrode 31 in the groove 27 has a structure that is not electrically in contact with the active layer 25 due to the insulating layer 70, so that electrons are injected into the active layer 25 from the source electrode 31 in the groove 27. Avalanche destruction is suppressed.

  A groove 27 having a depth reaching the silicon substrate 21 from the surface side of the active layer 25 is formed in a portion of the active layer 25 where the source electrode 31 is formed, and the surface of the active layer 25 and the silicon substrate 21 are formed in the groove 27. And an insulating layer 70 that insulates the portion in the groove 27 of the source electrode 31 from the active layer 25. For this reason, formation of the groove 27 and the insulating film 70 is facilitated.

  A GaN-based semiconductor device can be obtained in which the bonding pad is reduced, the element size can be reduced, and the avalanche breakdown is suppressed to improve the reliability.

  Next, in the GaN-based semiconductor device 20 having the above configuration, instead of the insulating layer 70 formed of an insulating film, the insulating layer 70A is configured by an ion implantation layer in which the active layer 25 is increased in resistance by ion implantation. Also good.

  A method for manufacturing the GaN-based semiconductor device 20 in which the insulating layer 70 </ b> A is configured by an ion implantation layer will be described with reference to FIGS.

  After the step (5), the following steps (6 ′) to (8 ′) are performed instead of the steps (6) to (9).

  (6 ′) An ion-implanted layer 73 that is selectively ion-implanted to increase the resistance is formed in the opening where the source electrode 31 is to be formed (see FIG. 4A).

  (7 ′) Next, the ion implantation layer 73 is formed on the silicon substrate 21 so that the insulating layer is formed leaving the ion implantation layer 73 only on the inner wall surface (the boundary surface between the ion implantation layer 73 and the active layer 25) of the groove 27A. Etching is performed to a depth that reaches (see FIG. 4B). As a result, the ion implantation layer 73 remains only on the inner wall surface of the groove 27A, and the insulating layer 70A made of the ion implantation layer having a high resistance is formed. Thus, the inner wall surface of the groove 27A here corresponds to the boundary surface between the ion implantation layer 73 and the active layer 25 formed in the step (6 ′).

  (8 ') Next, a photoresist is applied and patterning is performed to open a portion where the source electrode 31A is to be formed. Using this patterned photoresist as a mask, a source electrode 31A made of an alloy film of Ti and Al and Si is formed on the inner surface of the insulating layer 70A and the surface of the active layer 25 by a lift-off method (see FIG. 4C). ).

  Here, Ti and an alloy film of Al and Si are sequentially deposited, and a source electrode made of a laminate including a Ti layer in contact with the silicon substrate 21 and the active layer 25 and a layer made of an alloy of Al and Si. 31 is formed on the entire inner surface of the insulating layer 70 </ b> A to the depth reaching the silicon substrate 21 with the predetermined thickness described above. As a result, the surface of the active layer 25 and the silicon substrate 21 are electrically connected, but the portion in the groove 27A is insulated by the insulating layer 70A and is not in electrical contact with the active layer 25. Is formed in the groove 27A.

  Thereafter, by performing the above steps (10) to (14), the GaN-based semiconductor device 20 in which the insulating layer 70A is configured by an ion implantation layer is completed.

(Second Embodiment)
Next, a GaN-based semiconductor device 20A according to the second embodiment will be described with reference to FIG.

  In the GaN-based semiconductor device 20A, the groove 27 of the GaN-based semiconductor device 20 according to the first embodiment is changed to a groove 27B having an inverted trapezoidal cross section with an inner wall surface being an inclined surface.

In the GaN-based semiconductor device 20A, a groove (trench) 27B having a depth reaching the silicon substrate 21 from the surface side of the active layer 25 is formed in a portion of the active layer 25 where the source electrode 31A is formed. In the groove 27B, a source electrode 31A that electrically connects the surface of the active layer 25 and the silicon substrate 21, and an insulating layer 70 that insulates a portion of the source electrode 31A in the groove 27B from the active layer 25 are provided. Is formed. Other configurations are the same as those in the first embodiment.
According to the second embodiment having such a configuration, the same operational effects as those of the first embodiment can be obtained.

(Third embodiment)
Next, a GaN-based semiconductor device 20C according to the third embodiment will be described with reference to FIG.

  The GaN-based semiconductor device 20C is configured as a GaN-based MOS field effect transistor (GaN-based MOSFET).

  The GaN-based semiconductor device 20C includes a P-type silicon substrate 21, an epitaxial layer (active layer) 41 made of a GaN-based semiconductor formed on the substrate, a source electrode 42, a gate electrode 43, a drain electrode 44, The MOS field effect transistor includes a gate oxide film 45 formed on the epitaxial layer 41 and a gate electrode 43 formed on the gate oxide film 45.

  In the GaN-based semiconductor device 20C, a groove (trench) 27C having a depth reaching the silicon substrate 21 from the surface side of the epitaxial layer 41 is formed in a portion where the source electrode 42 is formed in the epitaxial layer 41 as an active layer. . In this groove 27D, a source electrode 42 that electrically connects the surface of the epitaxial layer 41 and the silicon substrate 21, and an insulating layer 70 that insulates a portion of the source electrode 42 in the groove 27D from the epitaxial layer 41, Is formed.

  The GaN-based semiconductor device 20C includes an impurity layer under the ohmic electrodes (source electrode 42 and drain electrode 44) formed on the surface of the epitaxial layer 41 using a regrowth technique or an ion implantation technique. The GaN-based semiconductor device 20B includes, as impurity layers, ohmic contact layers 46a and 46b formed in regions below the source electrode 42 (on the left and right upper end portions 42a and 42b) on the surface of the epitaxial layer 41, An ohmic contact layer 47 formed in a region under the drain electrode 44 and a RESURF layer 48 for reducing electric field concentration are provided.

  The epitaxial layer 41 is a p-GaN layer obtained by epitaxially growing, for example, GaN doped (doped) with a predetermined amount of Mg on the P-type silicon substrate 21 by MOCVD.

  The ohmic contact layers 46a, 46b and 47 are n + layers formed by growing a GaN-based semiconductor to which silicon (Si) or the like is added to a desired concentration and growing it by MOCVD.

  The RESURF layer 48 is formed by growing a GaN-based semiconductor to which silicon (Si) or the like is added to a desired concentration lower than that of the ohmic contact layers 46a, 46b and 47 by the MOCVD method. . In FIG. 6, reference numeral 29B denotes an interlayer insulating film.

  According to the third embodiment configured as described above, the same effect as the first embodiment is obtained, and the GaN-based semiconductor device having high reliability while maintaining the advantage of the low on-resistance of the GaN-based semiconductor device. A MOSFET can be realized.

(Fourth embodiment)
Next, a GaN-based semiconductor element 20D according to the fourth embodiment will be described with reference to FIG.

  The GaN-based semiconductor device 20D is configured as a GaN-based Schottky diode (GaN-based SBD).

  The GaN-based semiconductor device 20D includes a P-type silicon substrate 21, an active layer 55 made of a GaN-based semiconductor formed on the substrate, a cathode electrode 61 as a first electrode that is in ohmic contact with the active layer 55, and an active layer. And an anode electrode 62 as a second electrode that is in Schottky junction with the layer 55.

  The active layer 55 is formed on, for example, a buffer layer 52 made of a GaN-based semiconductor formed on the silicon substrate 21, a carrier running layer 53 made of undoped GaN formed on the buffer layer 52, and the carrier running layer 53. And a carrier supply layer 54 made of undoped AlGaN.

  In the GaN-based semiconductor device 20D, a groove (trench) 27D having a depth reaching the silicon substrate 21 from the surface side of the active layer 55 is formed in a portion of the active layer 55 where the cathode electrode 61 is formed. In the groove 27E, a cathode electrode 61 that electrically connects the surface of the active layer 55 and the silicon substrate 21, and an insulating layer 70 that insulates a portion of the cathode electrode 61 in the groove 27E from the active layer 55, Is formed.

  A passivation film 28 </ b> D is formed between the cathode electrode 61 and the anode electrode 62 on the surface of the carrier supply layer 54. On this passivation film 28D, an interlayer insulating film 29D made of Si nitride (SiN) is formed so as to fill a groove having an inverted trapezoidal cross section of the cathode electrode 61.

  According to the fourth embodiment configured as described above, the same effect as the first embodiment is achieved, and the GaN-based semiconductor device having high reliability while maintaining the advantage of the low on-resistance of the GaN-based semiconductor device. A Schottky diode can be realized.

(Fifth embodiment)
Next, a GaN-based semiconductor element 20E according to the sixth embodiment will be described with reference to FIG.

  This GaN-based semiconductor device 20E includes a silicon substrate 21 and an active layer 25 (channel layer 23) in order to improve the longitudinal breakdown voltage of the epitaxial wafer in the GaN-based semiconductor device 20A according to the second embodiment shown in FIG. In between, a p-GaN layer 81 and an n-GaN layer 82 are provided.

  In the GaN-based semiconductor device 20E, as in the GaN-based semiconductor device 20A shown in FIG. 5, a groove 27B (see FIG. 5) is formed in a portion of the active layer 25 where the source electrode 31A is formed.

  According to 5th Embodiment comprised as mentioned above, in addition to the effect which the said 1st Embodiment show | plays, there exist the following effects.

  In the GaN-based semiconductor device 20A shown in FIG. 5, the insulating layer 70 can suppress avalanche breakdown due to the injection of electrons from the source electrode 31A in the groove 27B into the active layer 25 (buffer layer 22). Since a high voltage is applied in the direction, it is necessary to improve the longitudinal breakdown voltage of the epitaxial wafer. According to this, since the p-GaN layer 81 and the n-GaN layer 82 are provided between the silicon substrate 21 and the active layer 25, the depletion layer extends and the breakdown voltage in the vertical direction of the epitaxial wafer is improved.

In addition, this invention can also be changed and embodied as follows.
In the GaN-based semiconductor device 20C according to the third embodiment shown in FIG. 6, the source electrode 42 is formed in the groove 27B formed by digging a portion where the source electrode 42 in the epitaxial layer 41 is formed to a depth reaching the silicon substrate 21. Although formed so as to be in electrical contact with both the silicon substrate 21 and the epitaxial layer 41, the present invention is not limited to this. The drain electrode 44 is formed so as to be in electrical contact with both the silicon substrate 21 and the epitaxial layer 41 in a groove 27B in which a portion of the epitaxial layer 41 where the drain source electrode 44 is formed is dug to a depth reaching the silicon substrate 21. The present invention can also be applied to such a configuration.

  The present invention can be applied not only to the GaN-based semiconductor devices described in the above embodiments, but also to GaN-based semiconductor devices such as MOSFETs, diodes, and bipolar transistors using GaN-based semiconductors.

1 is a cross-sectional view showing a GaN-based semiconductor device according to a first embodiment of the present invention. The top view which shows the upper surface of a GaN-type semiconductor device. (A)-(C) are process explanatory drawings which show the manufacturing method of the GaN-type semiconductor device which concerns on 1st Embodiment. (A)-(C) are process explanatory drawings which show another production method of the GaN-type semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows the GaN-type semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the GaN-type semiconductor device which concerns on 3rd Embodiment of this invention. Sectional drawing which shows the GaN-type semiconductor device which concerns on 4th Embodiment of this invention. The schematic diagram which shows schematic structure of the GaN-type semiconductor device which concerns on 5th Embodiment of this invention.

Explanation of symbols

20, 20A, 20C, 20D, 20E: GaN-based semiconductor device 21: P-type silicon (Si) substrate 22: Buffer layer 23: Channel layer (carrier travel layer)
24: Carrier supply layer 25, 55: Active layer 31, 31B: Source electrode 32, 32B: Drain electrode 33: Gate electrode 27, 27A, 27B, 27C, 27D, 27E: Groove 28, 28D: Passivation films 29, 29B, 29D: Interlayer insulating film 29a: Through hole 30d, 30s: Pad electrode 41: Epitaxial layer (active layer)
42: Source electrode 43: Gate electrode 44: Drain electrode 45: Gate oxide film 52: Buffer layer 53: Carrier traveling layer 54: Carrier supply layer 61: Cathode electrode 62: Anode electrode 81: p-GaN layer 82: n-GaN layer

Claims (10)

A P-type silicon (Si) substrate, an active layer made of a GaN-based semiconductor formed on the substrate, a first electrode and a second electrode through which an electric current flows between the active layers through the active layer, A back electrode formed on the back surface of the substrate,
A groove having a depth reaching the silicon substrate from the surface side of the active layer is formed in the active layer, and the surface of the active layer and the silicon substrate are electrically connected in the groove. 1. A GaN-based semiconductor device, comprising: one electrode; and an insulating layer that electrically insulates the first electrode from the active layer.   2. The GaN-based semiconductor device according to claim 1, wherein the first electrode uses a metal that is in ohmic contact with both the silicon substrate and the active layer.   The second electrode is formed on at least a part of an upper surface of an interlayer insulating film formed on the active layer, and is electrically connected to a pad electrode extending into a through hole of the interlayer insulating film. The GaN-based semiconductor device according to claim 1 or 2.   4. The GaN-based semiconductor device according to claim 1, further comprising a p-GaN layer and an n-GaN layer between the silicon substrate and the active layer. 5.   5. The GaN-based transistor according to claim 1, wherein the GaN-based transistor is a field effect transistor including a source electrode as the first electrode, a drain electrode as the second electrode, and a gate electrode. Semiconductor device. The field effect transistor is a heterojunction field effect transistor in which the active layer has a heterojunction structure of a first GaN semiconductor layer serving as a carrier traveling layer and a second GaN semiconductor layer serving as a carrier supply layer,
6. The GaN-based semiconductor device according to claim 5, wherein the groove is formed in a portion of the active layer where the source electrode is formed. The field effect transistor includes a gate oxide film formed on the active layer, and is a MOS field effect transistor in which the gate electrode is formed on the gate oxide film,
6. The GaN-based semiconductor device according to claim 5, wherein the groove is formed in a portion of the active layer where the source electrode is formed. A Schottky diode comprising: a cathode electrode as the first electrode in ohmic contact with the active layer; and an anode electrode as the second electrode in Schottky junction with the active layer;
The GaN-based semiconductor device according to claim 1, wherein the groove is formed in a portion of the active layer where the cathode electrode is formed. A P-type silicon (Si) substrate; an active layer made of a GaN-based semiconductor formed on the substrate; and a first electrode and a second electrode through which an electric current flows between the two electrodes in an on state via the active layer A method for manufacturing a GaN-based semiconductor device comprising at least two electrodes and a back electrode formed on the back surface of the substrate,
Forming a groove having a depth reaching the silicon substrate from the surface side of the active layer in a portion of the active layer where one of the two electrodes is formed;
Forming an insulating film on the entire surface after forming the groove;
Forming the insulating layer by leaving the insulating film only on the inner wall surface of the groove by etching the entire surface of the insulating film by a reactive ion etching (RIE) method;
Forming the one electrode on the inner surface of the insulating layer so as to electrically connect the surface of the active layer and the silicon substrate. A method for manufacturing a GaN-based semiconductor device, comprising: A P-type silicon (Si) substrate; an active layer made of a GaN-based semiconductor formed on the substrate; and a first electrode and a second electrode through which an electric current flows between the two electrodes in an on state via the active layer A method for manufacturing a GaN-based semiconductor device comprising at least two electrodes and a back electrode formed on the back surface of the substrate,
Forming an ion-implanted layer having a high resistance by selectively ion-implanting into a portion of the active layer where one of the two electrodes is formed;
Etching the ion implantation layer to a depth reaching the silicon substrate so as to form an insulating layer leaving the ion implantation layer only on the inner wall surface of the groove;
Forming the one electrode on the inner surface of the insulating layer so as to electrically connect the surface of the active layer and the silicon substrate. A method for manufacturing a GaN-based semiconductor device, comprising:

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