CN111341748A - 选择性图案镀层的引线框 - Google Patents

选择性图案镀层的引线框 Download PDF

Info

Publication number
CN111341748A
CN111341748A CN201811558851.2A CN201811558851A CN111341748A CN 111341748 A CN111341748 A CN 111341748A CN 201811558851 A CN201811558851 A CN 201811558851A CN 111341748 A CN111341748 A CN 111341748A
Authority
CN
China
Prior art keywords
die
lead
receiving area
die pad
metal plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811558851.2A
Other languages
English (en)
Inventor
宋美江
阿伦·马菲尔·德斯卡丁
小马里兰奥·L·京
张立栋
李军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Priority to CN201811558851.2A priority Critical patent/CN111341748A/zh
Priority to US16/368,573 priority patent/US10847449B2/en
Publication of CN111341748A publication Critical patent/CN111341748A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

一种用于装配半导体器件的铜基引线框，包括：多个布置在管芯垫层周围的引线指，所述引线指在管芯垫层外延伸，每个引线指具有接近管芯垫层的近端和远离管芯垫层的远端。金属镀层形成在引线指上，其中第一引线指具有镀在近端的金属镀层，第二引线指具有镀在远端的金属镀层。第一引线指和第二引线指交替的配置在管芯垫层周围。

Description

选择性图案镀层的引线框
技术领域
本发明涉及半导体器件封装，尤其涉及用于半导体设备封装的引线框。
背景技术
铜基引线框被用于多种半导体器件，例如QFN,QFP,LQFP,SOIC等。在铜基引线框中，将银或其它金属镀在引线指上，使得键合引线安全地附着在引线端，然而，复合模和银之类的镀层金属的粘附力不如复合模和铜的粘附力那么好，因此，在可靠性压力测试时，复合模和镀层金属容易产生分层，导致键合引线破裂，从而引发电路故障。
虽然已知可以用表面粗糙化来改进复合模分层，然而粗糙化并不改进引线可焊性，并且增加了成本。因此在集成电路器件压力测试或温度周期变化的过程中，不增加成本或影响引线可焊性的情况下，避免分层是有利的。
发明内容
在一个实施例中，本发明提供了一种用于装配半导体器件的引线框，该引线框是由铜形成，包括：管芯衬垫和多个布置在管芯衬垫周围的引线指，所述引线指在管芯衬垫外延伸，每个引线指具有接近管芯衬垫的近端和远离管芯衬垫的远端。金属镀层交替地添加在引线指上的近端和远端。
在另一个实施例中，本发明提供了一种封装的半导体器件，其特征在于，包括：多个具有交替电镀的引线端的引线框，配置在管芯垫层内的集成电路管芯；将各个引线指连接到管芯表面的焊盘的电连接器，其中电连接器接触第一引线指和第二引线指的金属镀层；以及覆盖管芯、电连接器和引线指的封装材料。
附图说明
通过示例的方式根据以下附图描述本发明的实施例，其中：
图1示出了传统的半导体器件的引线框的俯视图；
图2示出了根据本发明的一个实施例的半导体器件引线框的俯视图；
图3示出了根据本发明的一个实施例的半导体器件的侧面截面图。
具体实施方式
本发明的详细说明性的实施例在本文中公开。然而，这里公开的具体结构和功能细节仅仅是起到代表性的描述本发明的目的。本发明可以体现为许多替代形式，不应该被限定为这里阐述的实施例。此外，本文所使用的术语仅用于描述特定实施例的目的，不旨在限制本发明的示范性实施例。
如本文所使用的，除非上下文另有明确说明，单数形式“一”，“一个”和“该”也旨在包括复数形式。进一步可以理解的是，术语“包括”和/或“包含”表示所陈述的特征，步骤，或部件的存在，但不排除存在或添加一个或多个其它特征，步骤，或组件。还应当注意，在一些替代实施方式中，所提到的功能/动作可以不按照附图中所示的顺序发生。例如，取决于所涉及的功能/动作，连续示出的两个图实际上可以基本上同时执行或者有时可以以相反的顺序执行。
参见图1，示出了传统的半导体器件的引线框100的俯视图。引线框100包括管芯垫层101和多个引线指102。引线指大致垂直于管芯衬底101并且在管芯垫层101外延伸。每个引线指102有接近管芯垫层101的近端103和远离管芯垫层101的远端104。管芯垫层101和引线指102典型地可以是铜，例如是用铜片冲压或刻蚀。为了确保安全的引线键合，引线指102的近端103上镀有银，因为键合的引线(图中未示出)附加在引线指102的近端103。管芯垫层101的外端也可能镀有银，以允许下键合(例如接地线)。镀层用105表示，然而如前所讨论的，传统的镀有银的引线框在引线键合时会造成与其上覆盖的封装材料的分层。
图2示出了根据本发明的一个实施例的半导体器件引线框200的俯视图。引线框200包括管芯接收区域201，该管芯接收区域201被多个引线指202环绕。如实施例所示，管芯接收区域201包括管芯垫层，管芯接收区域201是平面的铜箔或者铜片。然而，在其他实施例中，例如外露管芯封装中，在装配过程时，管芯接收区域201可能是空的或者是引线框背面的一片胶带。引线指202基本与管芯接收区域201垂直并且在管芯接收区域201外延伸。每个引线指202具有接近管芯接收区域201的近端203和远离管芯接收区域201的远端204。
管芯接收区域201，可以包括管芯，和铜制成的引线指202，例如通过铜片冲压、切割或刻蚀。
金属镀层205形成在引线指202上，当存在管芯垫层的时候，金属镀层205也可以形成在管芯垫层上。然而，与传统的引线框100不同，镀层形成在替代的引线指202的近端203以及远端204，镀层形成在近端203的引线指与形成在远端的204的引线指相邻。因此，引线指202包括在近端203形成镀层205的第一组引线指和在远端204形成镀层205的第二组引线指，第一组引线指和第二组引线指交替地围绕在管芯垫层周围。通过替代镀层的位置，加强了复合模与引线框之间的粘附力。
当管芯接收区域201包括管芯垫层的时候，替代现有的在管芯垫层的整个外围镀层，而是在外围镀有由间隙206分开的镀层205。镀层205中的间隙206也改善了复合模的粘附力。优选的，间隙206彼此均匀分布。在一个实施例中，金属镀层205包括银。
图3示出了根据本发明的一个实施例的半导体器件300的侧面截面图。封装半导体器件300使用了图2所述的引线框200来封装。引线框200多个环绕在管芯接收区域201周围的引线指202。引线指202基本与管芯接收区域201垂直并且在管芯接收区域201外延伸。每个引线指202具有接近管芯接收区域201的近端203和远离管芯接收区域201的远端204。
金属镀层205形成在替代的引线指的不同位置上，即第一引线指具有镀在近端的金属镀层205，第二引线指具有镀在远端的金属镀层205，并且第一引线指和第二引线指交替地围绕在管芯垫层201周围。集成电路管芯210配置在管芯接收区域内。并且更具体地，用管芯粘合剂或者胶带附着在管芯垫层201的上表面(图中未显示)。管芯210可能包含任意一种管芯，例如定制逻辑电路、系统或者芯片，或者微控制器。电连接器212，在实施例中是以键合引线的形式显示，连接管芯210上表面的焊盘与各自的引线指205。当然电连接器212接触第一引线指和第二引线指的金属镀层205。封装材料214覆盖管芯210、电连接器212和引线指202。注意对于QFP来说，例如，关于镀层的“远端”并非指延伸到由塑封材料214形成的封装主体的引线端，“远端”是指在复合模内的一个位置，并且与相邻的引线指的“近端”相偏移。其中键合引线212连接到引线指202。
管芯垫层201的上表面的四周包括镀层和非镀层部分，如图2所示。
在一个优选的实施例中，引线框200是由铜箔或者铜片形成。引线的特征，例如管芯垫层和引线指(还有结合条和尾条)可以通过铜片冲压、切割或刻蚀形成。上述的镀层区域包括银镀层。然而，引线框的气体区域可能包含相同或另外的镀层。比如，延伸在封装材料外的引线的外露端可能被镀层以防止腐蚀。可以使用其他的镀层材料或合金。
本发明实现了“锁定效应”，因为它阻止了分层传播，并且增强了与金属镀层引线框装配的设备的分层性能。
虽然本发明已经在具有单一管芯和单一电连接器(如键合引线)的IC封装的情况下进行了描述，但是应当理解，本发明可以用于具有任何合适数量的管芯和合适数量的电连接其的IC封装。
也为了本说明书的目的，术语“连接”是指本领域中已知的或稍后发展的允许能量在两个或更多个元件之间传递的任何方式，并且中间可以插入一个或多个附加元件，但不是必需的。相反，术语“直接耦合”，“直接连接”等等，意味着不存在这种附加元件。
使用附图标号和/或附图标号旨在标识一个或多个实施例，以便于对权利要求的解释。这样的使用不应被解释为必然地将那些权利要求的范围限制在相应附图中所示的实施例。
除非另有明确说明，否则每个数值和范围应当被解释为近似的，如同词语“约”或“大约”。
应该理解的是，在细节，材料，和其中已被描述和说明是为了解释本发明实施例的部件的布置的各种变化，可以由本领域的技术人员作出不脱离本发明的实施方式。
应当理解，本文阐述的示例性方法的步骤不一定需要以所描述的顺序执行，并且这些方法的步骤的顺序应当被理解为仅仅是示例性的。同样，在与本发明的各种实施例一致的方法中，可以在这些方法中包括附加步骤，并且可以省略或组合某些步骤。
虽然在下面的方法权利要求中的元素，如果有的话，被记载在一个特定的序列与对应的标签中，除权利要求陈述，否则意味着用于实施部分或所有这些要素的特定顺序，这些元素不一定被限定于以该特定顺序实现。
本文对“实施例”的引用意味着特定特征、结构或特性可以包括在本发明的至少一个实施例中。在说明书中的各个位置出现的短语“在一个实施例中”不一定都指代相同的实施例，单独的或替代的实施例也不是必然与其他实施例相互排斥。这同样适用于术语“实现”。

Claims (9)

1.一种用于装配半导体器件的引线框，包括：
多个布置在管芯接收区域周围的引线指，所述引线指在管芯接收区域外延伸，每个引线指具有接近管芯接收区域的近端和远离管芯接收区域的远端，所述引线指包括铜，并且
金属镀层形成在引线指上，其中第一引线指具有镀在近端的金属镀层，第二引线指具有镀在远端的金属镀层。
2.根据权利要求1所述的引线框，其特征在于，进一步包括配置在管芯接收区域内的管芯垫层，其中管芯垫层包括铜。
3.根据权利要求2所述的引线框，其特征在于，所述第一引线指和第二引线指交替的配置在管芯垫层周围。
4.根据权利要求2所述的引线框，其特征在于，所述管芯垫层包括金属镀层。
5.根据权利要求4所述的引线框，其特征在于，所述管芯垫层的金属镀层在管芯垫层的上表面的四周延伸。
6.根据权利要求5所述的引线框，其特征在于，所述管芯垫层的金属镀层中具有多个空隙。
7.根据权利要求6所述的引线框，其特征在于，所述空隙彼此间均匀地间隔。
8.一种封装的半导体器件，其特征在于，包括：
多个布置在管芯接收区域周围的引线指，所述引线指在管芯接收区域外延伸，每个引线指具有接近管芯接收区域的近端和远离管芯接收区域的远端，所述引线指包括铜，并且
金属镀层形成在引线指上，其中第一引线指具有镀在近端的金属镀层，第二引线指具有镀在远端的金属镀层；
配置在管芯接收区域内的集成电路管芯；
将各个引线指连接到管芯表面的焊盘的电连接器，其中电连接器接触第一引线指和第二引线指的金属镀层；以及
覆盖管芯、电连接器和引线指的封装材料。
9.根据权利要求8所述的封装的半导体器件，其特征在于，进一步包括：
配置在管芯接收区域的管芯垫层，
所述管芯垫层包括铜，并且管芯附着在管芯垫层的上表面，
所述管芯垫层包括延伸在管芯垫层四周的金属镀层，
所述管芯垫层的金属镀层中具有多个空隙。
CN201811558851.2A 2018-12-19 2018-12-19 选择性图案镀层的引线框 Pending CN111341748A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201811558851.2A CN111341748A (zh) 2018-12-19 2018-12-19 选择性图案镀层的引线框
US16/368,573 US10847449B2 (en) 2018-12-19 2019-03-28 Lead frame with selective patterned plating

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811558851.2A CN111341748A (zh) 2018-12-19 2018-12-19 选择性图案镀层的引线框

Publications (1)

Publication Number Publication Date
CN111341748A true CN111341748A (zh) 2020-06-26

Family

ID=71097740

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811558851.2A Pending CN111341748A (zh) 2018-12-19 2018-12-19 选择性图案镀层的引线框

Country Status (2)

Country Link
US (1) US10847449B2 (zh)
CN (1) CN111341748A (zh)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07312403A (ja) * 1994-05-17 1995-11-28 Fujitsu Ltd 半導体装置及びその製造方法及び実装基板
JPH0883875A (ja) * 1994-09-13 1996-03-26 Kyodo Printing Co Ltd リードフレームの乾式めっき法
JPH09219486A (ja) * 1996-02-08 1997-08-19 Toppan Printing Co Ltd リードフレーム
US20070222040A1 (en) * 2006-03-24 2007-09-27 Chipmos Technologies (Bermuda) Ltd. Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same
US20100181658A1 (en) * 2009-01-19 2010-07-22 Nec Electronics Corporation Semiconductor device which exposes die pad without covered by interposer and its manufacturing method
US20110140253A1 (en) * 2009-12-14 2011-06-16 National Semiconductor Corporation Dap ground bond enhancement
US8184453B1 (en) * 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US20140319663A1 (en) * 2013-04-18 2014-10-30 Dai Nippon Printing Co., Ltd. Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing semiconductor device
DE102016117892A1 (de) * 2015-09-25 2017-03-30 Infineon Technologies Ag Direkte selektive Haftvermittlerplattierung

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4033844A (en) 1975-11-03 1977-07-05 National Semiconductor Corporation Apparatus for selectively plating lead frames
US4289922A (en) 1979-09-04 1981-09-15 Plessey Incorporated Integrated circuit package and lead frame
KR920000127A (ko) 1990-02-26 1992-01-10 미다 가쓰시게 반도체 패키지와 그것을 위한 리드프레임
US5403465A (en) 1990-05-30 1995-04-04 Gould Inc. Electrodeposited copper foil and process for making same using electrolyte solutions having controlled additions of chloride ions and organic additives
US5339518A (en) 1993-07-06 1994-08-23 Motorola, Inc. Method for making a quad leadframe for a semiconductor device
US5329159A (en) 1993-08-03 1994-07-12 Motorola, Inc. Semiconductor device employing an aluminum clad leadframe
US5429992A (en) 1994-05-25 1995-07-04 Texas Instruments Incorporated Lead frame structure for IC devices with strengthened encapsulation adhesion

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07312403A (ja) * 1994-05-17 1995-11-28 Fujitsu Ltd 半導体装置及びその製造方法及び実装基板
JPH0883875A (ja) * 1994-09-13 1996-03-26 Kyodo Printing Co Ltd リードフレームの乾式めっき法
JPH09219486A (ja) * 1996-02-08 1997-08-19 Toppan Printing Co Ltd リードフレーム
US20070222040A1 (en) * 2006-03-24 2007-09-27 Chipmos Technologies (Bermuda) Ltd. Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same
US8184453B1 (en) * 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US20100181658A1 (en) * 2009-01-19 2010-07-22 Nec Electronics Corporation Semiconductor device which exposes die pad without covered by interposer and its manufacturing method
US20110140253A1 (en) * 2009-12-14 2011-06-16 National Semiconductor Corporation Dap ground bond enhancement
US20140319663A1 (en) * 2013-04-18 2014-10-30 Dai Nippon Printing Co., Ltd. Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing semiconductor device
DE102016117892A1 (de) * 2015-09-25 2017-03-30 Infineon Technologies Ag Direkte selektive Haftvermittlerplattierung

Also Published As

Publication number Publication date
US20200203258A1 (en) 2020-06-25
US10847449B2 (en) 2020-11-24

Similar Documents

Publication Publication Date Title
US8362598B2 (en) Semiconductor device with electromagnetic interference shielding
US9136247B2 (en) Resin-encapsulated semiconductor device and method of manufacturing the same
TWI295846B (en) Semiconductor device having post-mold nickel/palladium/gold plated leads
US20070215990A1 (en) Method for making QFN package with power and ground rings
US9275972B2 (en) Resin-encapsulated semiconductor device and method of manufacturing the same
US8039317B2 (en) Aluminum leadframes for semiconductor QFN/SON devices
US7413934B2 (en) Leadframes for improved moisture reliability and enhanced solderability of semiconductor devices
US7309909B2 (en) Leadframes for improved moisture reliability of semiconductor devices
CN104934404B (zh) 半导体装置及其制造方法
TW200818458A (en) Stackable packages for three-dimensional packaging of semiconductor dice
US8643158B2 (en) Semiconductor package and lead frame therefor
WO2009010716A1 (en) Semiconductor chip package with bent outer leads
US20100314728A1 (en) Ic package having an inductor etched into a leadframe thereof
WO2008005911A2 (en) Exposed top side copper leadframe manufacturing
US8866278B1 (en) Semiconductor device with increased I/O configuration
US8785253B2 (en) Leadframe for IC package and method of manufacture
US20130020689A1 (en) Semiconductor device and method of packaging same
CN111341748A (zh) 选择性图案镀层的引线框
JP6500299B2 (ja) リードフレームおよびそれを用いた半導体装置の製造方法
EP2846355A1 (en) Electrical substrate and process of manufacturing the same
JP4305310B2 (ja) 半導体装置
CN220358084U (zh) 电子器件和引线框
JP2972679B2 (ja) リードフレーム並びに樹脂封止型半導体装置及びその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination