CN111338427B

CN111338427B - Method for realizing SystemC semi-physical simulation time synchronization

Info

Publication number: CN111338427B
Application number: CN202010124966.1A
Authority: CN
Inventors: 陶永超; 郑宏运; 吴翔虎
Original assignee: Shenzhen Academy of Aerospace Technology
Current assignee: Shenzhen Academy of Aerospace Technology
Priority date: 2020-02-27
Filing date: 2020-02-27
Publication date: 2021-06-15
Anticipated expiration: 2040-02-27
Also published as: CN111338427A

Abstract

The invention provides a method for realizing SystemC semi-physical simulation time synchronization, which comprises the following steps: step 1: connecting a clock source generator between the PC and the actual hardware, wherein the clock source generator can generate a corresponding clock source according to a specified numerical value, and the clock source is used as a clock input source of the actual hardware in the semi-physical simulation; step 2: writing a clock synchronization module in the SystemC program of the PC, wherein the clock synchronization module generates a clock output to drive actual hardware on one hand, and communicates with the PC through a USB bus to synchronize the operation of the SystemC program on the other hand. The invention has the beneficial effects that: the method for realizing SystemC semi-physical simulation time synchronization ensures the time sequence synchronization of the logic clock of the software and the actual hardware, and meets the basic requirements of software and hardware collaborative simulation development.

Description

Method for realizing SystemC semi-physical simulation time synchronization

Technical Field

The invention relates to the field of semiconductors, in particular to a method for realizing SystemC semi-physical simulation time synchronization.

Background

Due to the rapid expansion of the modern semiconductor industry, the integration scale of semiconductors is increasingly complex and large; for example, the latest intel cpu, in which 1000000 semiconductor devices are integrated; with the current prosperous industry, the speed of semiconductor development verification testing is critical to the development of semiconductor enterprises. Therefore, the basic model in the current semiconductor development is simulation and verification while developing, wherein SystemC is a development and test framework capable of full life cycle support. Migration adaptation from early digital circuit logic verification, to late architectural analysis, algorithmic analysis, and upper-level application software, such as an operating system, can be supported. Therefore, the system C is widely applied at present, and in the aspect of the current 5G technology, Fastmodels and semi-physical simulation schemes are adopted to accelerate the research and development progress. Wherein the derived interface standard of FastModels is the SystemC standard.

SystemC is a class library developed using the C + + programming language and provides an event-driven simulation framework to schedule the execution order of various events. The scheduling algorithm idea of SystemC is to divide continuous simulation time into a plurality of discrete simulation moments, divide one simulation moment into a plurality of delta-cycles, and update the channel value after one delta-cycle or a plurality of delta-cycles, so that the parallelism behavior of hardware can be simulated in the delta-cycles by using a sequentially executed programming language. So that the designer of the simulation system can simulate the parallel process by using the syntax rule of C + +. Therefore, not only is the development convenience increased, but also the threshold of a software engineer for hardware development and test is reduced.

Currently, SystemC becomes a standard of the simulation industry, and products of all large EDA manufacturers are compatible with the SystemC standard. SystemC is pure software, and can completely simulate the existing hardware behavior, but the current semiconductor development has not started from scratch, and many EDA companies or research and development teams have mature modules at present, and the modules pass many times of strict tests; for example, communication baseband, which is a very mature module, it is often more desirable to co-simulate the module with software rather than rewriting a similarly complex analog module with software. At this time, the need for semi-physical simulation arises. And similarly, the complexity of some modules in the whole system is not too high, the design is not complex, and at this time, the modules can be written and implemented by using pure software or even TLM, on one hand, mature modules can be integrated, and on the other hand, the whole test verification progress cannot be influenced by some modules which are not very critical. As shown in background fig. 1, background fig. 1 is an example of a semi-physical simulation: where the left box represents the real hardware and the right box represents the simulation running on the PC. They communicate with each other by connecting them in some way.

In the field of semi-physical simulation, a crucial problem is that of time synchronization. What is called time synchronization? Because the software simulates real hardware, the logic of the software is also time-conceptualized, and the time is not the time in the world which is displayed by the software but the virtual logic time. If the software simulation requires 1 minute of logic time, if the arithmetic logic is complex and your computer is of a normal performance, then the software may need to run for 10 minutes before finishing. Then the software runs for 1 minute in the simulated world, but takes 10 minutes in the real world. If your computer is powerful enough, it is likely that this software will end up running for only 1 second, and the logic will still run for 1 minute. Therefore, the problem is that the simulation speed of software is difficult to be uniform under different computer performances in different simulation environments. In the actual work of soft and hard collaborative semi-physical simulation, the problem is definitely solved first. Because of your mature peripheral module, his performance is fixed; for example, a mature baseband module hardware, whose performance is fixed, and whose time it takes to decode a piece of radio information is substantially exactly equal. Then our problem is to ensure synchronization of the two modules because one is a fixed time and the other is an unfixed time, as described in the background of fig. 2.

Disclosure of Invention

The invention provides a method for realizing SystemC semi-physical simulation time synchronization, which comprises the following steps: step 1: connecting a clock source generator between the PC and the actual hardware, wherein the clock source generator can generate a corresponding clock source according to a specified numerical value, and the clock source is used as a clock input source of the actual hardware in the semi-physical simulation; step 2: writing a clock synchronization module in the SystemC program of the PC, wherein the clock synchronization module generates a clock output to drive actual hardware on one hand, and communicates with the PC through a USB bus to synchronize the operation of the SystemC program on the other hand.

As a further improvement of the present invention, in step 1, the clock source generator is a logic chip, which generates a clock output to the actual hardware to be tested on the one hand and communicates with the PC through a USB bus on the other hand.

As a further improvement of the present invention, in step 1, the virtual emulation software of the PC accesses the logic chip through the USB driver, and sends different control commands to the logic chip to generate different clocks.

As a further improvement of the invention, in the step 1, the virtual simulation software of the PC also counts the clock times and is used as a basis for the synchronous clock period of the PC.

As a further improvement of the present invention, in the step 2, the clock synchronization module is implemented as follows:

creating a read in the SystemC, designing a clock cycle by the read, wherein the clock cycle of the logic corresponds to the clock cycle of the real hardware to be synchronized, and then keeping the two clock cycles synchronized.

As a further improvement of the invention, a first USB port is arranged on the logic chip, a second USB port is arranged on the PC, and the logic chip and the PC transmit a synchronous clock protocol through the first USB port and the second USB port.

As a further improvement of the present invention, a third USB port is provided on the actual hardware, a fourth USB port is provided on the PC, and the actual hardware and the PC transmit other data communications through the third USB port and the fourth USB port.

As a further improvement of the invention, the PC is a windows or Linux system.

The invention has the beneficial effects that: the method for realizing SystemC semi-physical simulation time synchronization ensures the time sequence synchronization of the logic clock of the software and the actual hardware, and meets the basic requirements of software and hardware collaborative simulation development.

Drawings

FIGS. 1-2 are background diagrams of the method of the present invention;

fig. 3 is a schematic block diagram of the method of the present invention.

Detailed Description

As shown in fig. 3, the present invention discloses a method for realizing SystemC semi-physical simulation time synchronization, which comprises the following steps:

step 1: the method of the invention is that a clock oscillation source part is specially processed to be a clock source generator, the clock source generator is connected between a PC and actual hardware, the clock source generator can generate a corresponding clock source according to a designated numerical value, and the clock source is used as a clock input source of the actual hardware in semi-physical simulation;

step 2: writing a clock synchronization module in the SystemC program of the PC, wherein the clock synchronization module generates a clock output to drive actual hardware on one hand, and communicates with the PC through a USB bus to synchronize the operation of the SystemC program on the other hand.

In the step 1, the clock source generator is a logic chip, and the logic chip generates a clock output to the actual hardware to be tested on one hand and communicates with the PC through a USB bus on the other hand.

In step 1, the virtual emulation software of the PC accesses the logic chip through the USB driver, and sends different control commands to the logic chip to generate different clocks.

In step 1, the virtual simulation software of the PC also counts the number of clocks, which is used as a basis for synchronizing clock cycles of the PC.

In step 2, the clock synchronization module is implemented as follows:

creating a read in the SystemC, designing a clock cycle by the read, wherein the clock cycle of the logic corresponds to the clock cycle of the real hardware to be synchronized, and then the core purpose is to keep the two clock cycles synchronized.

The logic chip is provided with a first USB port, the PC is provided with a second USB port, and the logic chip and the PC transmit a synchronous clock protocol through the first USB port and the second USB port.

The actual hardware is provided with a third USB port, the PC is provided with a fourth USB port, and the actual hardware and the PC transmit other data communication through the third USB port and the fourth USB port.

The PC is a windows or Linux system.

The invention discloses a method for realizing SystemC semi-physical simulation time synchronization, which has the following working principle: firstly, the clock input of the hardware cannot be generated spontaneously, but the clock pulse of different times is generated passively through an instruction issued by a PC host; if there is no instruction, the output of the clock oscillation remains unchanged in level. Then, after the PC machine issues an instruction for generating the clock, the clock synchronization chip receives the instruction, the clock is generated and output to the actual hardware, and then the hardware shows the logic behavior of the hardware, so that the purpose of simulation is achieved. Then the clock synchronization chip replies a signal to the PC indicating that the clock action has been performed, and so on until the next cycle. When the logic of software simulation is very complicated, the software may need to run for a long time to reach the next cycle, at this time, the synchronization chip still does not generate clock output because the synchronization chip has not obtained the instruction for generating the clock, and the behavior of the actual hardware is also equivalent to temporarily freezing to wait for the next synchronization of the software. The running mode ensures the time sequence synchronization of the software clock and the actual hardware, and meets the basic requirements of software and hardware collaborative simulation development.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A method for realizing SystemC semi-physical simulation time synchronization is characterized by comprising the following steps:

step 1: connecting a clock source generator between the PC and the actual hardware, wherein the clock source generator can generate a corresponding clock source according to a specified numerical value, and the clock source is used as a clock input source of the actual hardware in the semi-physical simulation;

step 2: writing a clock synchronization module in a SystemC program of the PC, wherein the clock synchronization module generates a clock output to drive actual hardware on one hand, and communicates a clock synchronization protocol with the PC through a USB bus on the other hand to synchronize the operation of the SystemC program;

in step 2, the clock synchronization module is implemented as follows:

2. The method according to claim 1, wherein in step 1, the clock source generator is a logic chip which generates a clock output to actual hardware to be tested on the one hand and communicates with a PC through a USB bus on the other hand.

3. The method according to claim 2, wherein in step 1, the virtual emulation software of the PC accesses the logic chip through the USB driver, and sends different control commands to the logic chip to generate different clocks.

4. The method of claim 3, wherein in step 1, the virtual emulation software of the PC also counts the number of clocks used as a basis for the PC to synchronize clock cycles.

5. The method of claim 2, wherein: the logic chip is provided with a first USB port, the PC is provided with a second USB port, and the logic chip and the PC transmit a synchronous clock protocol through the first USB port and the second USB port.

6. The method of claim 1, wherein: the actual hardware is provided with a third USB port, the PC is provided with a fourth USB port, and the actual hardware and the PC transmit other data communication through the third USB port and the fourth USB port.

7. The method of claim 1, wherein: the PC is a windows or Linux system.