JP5390464B2 - Simulation apparatus, simulation apparatus control method, and program - Google Patents

Description

  The present invention relates to a simulation apparatus, a simulation apparatus control method, and a program, and more particularly, to a simulation apparatus, a simulation apparatus control method, and a program that verify a system function by coordinating a plurality of simulation processes.

  In recent years, in the development of a system in which a plurality of processes cooperate to exert a desired function, a system level design method for simultaneously designing a plurality of processes has been widely used. In such a system level design method, it is necessary to execute a collaborative simulation for cooperating a plurality of processes in the middle of design, and to verify the causal relationship of each process.

For example, when developing a SoC (System on a Chip) in which a processor, memory, and peripheral circuits are integrated on one chip and hardware and software cooperate, using a system level design method, SoC system design At the initial stage, a system function model that defines processing functions and their order based on sequential processing by the processor installed in the system is examined, and the hardware and software parts required for the system are designed from this function model. Is advanced.
At this time, the design and development of a desired system can be promoted by executing cooperative simulation, causing hardware and software in the middle of design to operate in cooperation, and verifying the consistency of the causal relationship between the two.

  Conventionally, as a co-simulation, in a host computer equipped with a processor, a storage device, and an interface, a program representing the operation of system hardware and software in the middle of design is executed, and the system hardware and software are simulated. There is known a hardware / software co-simulation (hereinafter referred to as “HW / SW co-simulation”) that performs a cooperative operation and verifies the causal relationship between them (Non-Patent Document 1-2).

Here, the conventional cooperative simulation will be specifically described with reference to FIGS. 9 to 11 by taking the HW / SW cooperative simulation as an example.
As shown in FIG. 9, the functional model of the system to be subjected to HW / SW co-simulation is a source code (hereinafter referred to as “HW source code”) describing an operation model by the hardware part of the system and a software part. It is composed of source code describing an operation model (hereinafter referred to as “SW source code”).
The HW source code is a source code in which the operation by the hardware part is described in a hardware description language (SystemC or the like), and the SW source code is an operation in which the software part is described by a predetermined language (C language or the like). Source code.

  The conventional HW / SW co-simulation process by the host computer includes object code capable of executing hardware simulation on an operation model of the hardware part generated by compiling HW source code and SW source code, and software part The hardware simulator and the software simulator execute respective simulation processes based on the binary code such as an instruction word sequence for a processor capable of executing the software simulation for the operation model, and verify the causal relationship in the result of the simulation. .

  Hereinafter, a series of processing in the hardware simulation of the hardware portion by the host computer is referred to as “hardware processing”, and a series of processing in the software simulation of the software portion is referred to as “software processing”, and details of the conventional HW / SW co-simulation are described. explain.

  As shown in FIG. 10, the HW / SW co-simulation device 20 includes a software simulation execution unit 210, a hardware simulation execution unit 220, and a co-simulation execution unit 230. By mounting these components of the HW / SW co-simulation apparatus 20 on the host computer, the HW / SW co-simulation apparatus 20 executes the HW / SW co-simulation using the processor, storage device, and interface of the host computer. .

The software simulation execution unit 210 of the HW / SW co-simulation device 20 compiles the SW source code to generate a binary code such as an instruction word sequence for a processor that can execute the software simulation, and performs software processing based on the binary code. Execute.
For example, the operation of the software is simulated by executing a command extracted from the binary code by a software simulator such as ISS (Instruction Set Simulator).
Further, the time information required for processing one command extracted from the binary code can be obtained from the frequency of the clock when the simulation processing by a software simulator such as ISS is executed, and the software operation processing is performed by software simulation. Time can be accumulated.

The hardware simulation execution unit 220 compiles the HW source code, generates a test bench that is information indicating the conditions of hardware simulation including object code that can be executed by hardware simulation, and based on the test bench Perform hardware processing.
For example, a hardware simulator such as an EDA (Electronic Design Automation) tool is used to simulate the hardware operation by executing the object code in accordance with the conditions defined in the test bench.
The test bench incorporates time information required for executing the object code, and the hardware operation processing time can be accumulated by hardware simulation.

The co-simulation execution unit 230 monitors the processing time of the software operation accumulated by executing the software simulation and the processing time of the hardware operation accumulated by executing the hardware simulation, respectively. The timing of each simulation process is controlled.
Specifically, the co-simulation execution unit 230 monitors the occurrence of an event that affects the result of each simulation process among the respective simulation processes performed by the software simulation execution unit 210 or the hardware simulation execution unit 220. At the same time, the respective simulation processes by the software simulation execution unit 210 and the hardware simulation execution unit 220 are synchronized with the occurrence of this event.

  For example, as shown in FIG. 11, the co-simulation execution unit 230 includes a hardware register area access instruction (hereinafter referred to as “HW register area access instruction”) in the simulation process performed by the software simulation execution unit 210. ) Is monitored, and the simulation process of the software simulation execution unit 210 and the hardware simulation execution unit 220 is synchronized with the HW register area access instruction.

Information Processing Society of Japan, Vol. 45, No. 5 (May 2004, IPSJ-MGN450504) pp.456-463 Nikkei BP Nikkei Electronics July 29, 2002 (No.827) pp.104-133

  However, in the conventional collaborative simulation in which the execution start and end timings of the simulation are controlled in synchronization with commands that affect each other among a plurality of programs, the simulation processing of the commands in any one of the plurality of programs is performed. Depending on the progress, there may be a case where an unnecessary standby time is generated for the simulation process in the other program, and the simulation efficiency is lowered.

For example, in the case of the HW / SW co-simulation process as shown in FIG. 11, the command executed in the HW simulation process in period 3 is a command that affects the register value held in the register area. On the other hand, the command executed in the HW simulation process in the period 5 is a process that does not affect the register value.
That is, in the period 3, it is necessary to synchronize the start and end of the HW simulation process and the SW simulation process, but in the period 5, the SW simulation process is not necessarily synchronized with the HW simulation process. It is necessary to wait for completion, and unnecessary waiting time occurs.
Therefore, the smaller the HW simulation process in period 5, the more calculation time of the simulation process by the processor can be reduced. On the other hand, the more HW simulation process in this period, the more calculation time increases, leading to a decrease in simulation efficiency.

  Also, changing the behavior model of the hardware part that is the design target to improve the simulation efficiency not only wastes a great deal of design cost, but also the development efficiency that is the original purpose of executing the co-simulation. Deviation from improvement does not make sense for verification using co-simulation.

  Therefore, the present invention has been made to solve the above-described problem, and in a simulation process in which a plurality of processes are coordinated to verify the causal relationship of each treatment, unnecessary waiting time is suppressed, and simulation efficiency is improved. It aims at improving.

  In order to achieve the above object, the present invention provides a plurality of arithmetic units each simulating different target operations according to a plurality of instructions included in a computer program, and controlling the operation timing of these arithmetic units to perform the arithmetic operation. A control unit for coordinating the command executed in the unit, and at least one of the calculation units controls an operation clock when executing the command according to a command executed by the calculation unit It comprises a part.

  In addition, the calculation unit of the simulation apparatus according to the present invention includes: a command identifying unit that identifies whether one command among the plurality of commands is a command that affects an operation based on another command; A command adding unit that adds a command to change the frequency of the operation clock to the one command based on the identification result by the command identifying unit, and the clock control unit is added by the command adding unit. The frequency of the operation clock may be controlled based on the command.

  The command identifying unit of the simulation device according to the present invention includes at least one hardware program in which an operation model in an arbitrary logic circuit is described in a predetermined language, and an operation model of a function by an arbitrary processor in a predetermined language. In any one of the at least one software program described in (1), a read completion command indicating completion of reading of data stored in the hardware register and a write start command indicating start of writing are extracted, and the command is added. A predetermined frequency for the hardware program or the software program from which the read completion command and the write completion command have been extracted by the command identification unit immediately after the extracted read completion command. The first frequency is changed to an arbitrary second frequency. And adding a second command for changing the frequency of the clock to the predetermined first frequency immediately before the extracted write start command. The function of the system in cooperation with the software program may be verified.

According to the present invention, by controlling the frequency of the verification clock when the simulation is executed based on the code for executing the simulation generated by the code generation unit, the functions of the system can be coordinated with a plurality of simulation processes. In the co-simulation that verifies the model, it is possible to set the verification clock that matches each simulation process and execute the co-simulation process.
Therefore, the unnecessary standby time of the simulation process for verifying the function model of the system that exhibits a desired function can be suppressed by the cooperation of a plurality of processes, so that the simulation efficiency can be improved.

It is a figure which illustrates notionally HW / SW cooperation simulation in embodiment of this invention. It is a block diagram which shows the structure of the simulation apparatus concerning embodiment of this invention. It is a block diagram which shows the structure of the calculating part in the simulation apparatus concerning embodiment of this invention. It is a figure which shows an example of the program code to which the special command was added by the command addition part in embodiment of this invention. It is a figure which shows an example of the program code to which the special command was added by the command addition part in embodiment of this invention. It is a flowchart which shows operation | movement of the simulation apparatus concerning embodiment of this invention. It is a flowchart which shows operation | movement of the simulation apparatus concerning embodiment of this invention. It is a figure which shows the operation | movement sequence of the cooperative simulation in the simulation apparatus concerning embodiment of this invention. It is a figure which illustrates the conventional HW / SW cooperation simulation notionally. It is a block diagram which shows an example of a structure of the conventional HW / SW co-simulation apparatus. It is a figure which illustrates notionally the operation | movement of the conventional HW / SW cooperative simulation along time passage.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
A simulation apparatus according to an embodiment of the present invention performs a plurality of simulation processes by a plurality of programs in cooperation with each other in a system represented by a plurality of programs in consideration of the causal relationship between the processing operations of the programs. This is to verify the function of the system.

  In the present embodiment, a simulation apparatus that executes HW / SW co-simulation in which a hardware program that describes an operation model of the hardware part of the system and a software program that describes the operation model of the software part is taken as an example. explain.

FIG. 1 is a diagram conceptually illustrating the HW / SW cooperative simulation executed by the simulation apparatus according to the embodiment of the present invention.
As shown in FIG. 1, the function model of a system to be subjected to HW / SW co-simulation is a program source code (hereinafter referred to as “HW source”) in which an operation model of a hardware part is described in a hardware description language (such as SystemC). And a program source code (hereinafter referred to as “SW source code”) in which a software operation model is described in a predetermined program language (C language or the like).

  For example, when the HW / SW co-simulation is executed by the host computer, the host computer compiles the HW source code and SW source code, respectively, and executes a test bench or software simulation including object code that can execute hardware simulation. An execution code such as a binary code such as an instruction word sequence for an executable processor is generated.

The configuration and function of the simulation apparatus according to this embodiment will be described with reference to the block diagram shown in FIG.
As shown in FIG. 2, the simulation apparatus 10 according to the present embodiment includes operation units 110-1 to 110-n and a cooperative control unit 120.
The calculation units 110-1 to 110-n execute a first simulation that simulates the operation of different objects in accordance with a plurality of commands included in the computer program.
The first simulation can be, for example, a hardware simulation that verifies the processing operation in the HW source code, or a software simulation that verifies the processing operation in the SW source code.

The cooperative control unit 120 controls the operation timing of the two or more arithmetic units 110-1 to 110-n to coordinate the first simulations executed in the arithmetic units 110-1 to 110-n, and A second simulation for verifying the operation of the system exhibited by the cooperation of the commands is executed.
The second simulation can be, for example, a HW / SW cooperative simulation in which a hardware simulation and a software simulation are cooperatively operated.

The arithmetic unit 110-n of the simulation apparatus 10 includes a code generation unit 111-n, a program verification execution unit 112-n, and a clock control unit 113-n.
The code generation unit 111-n generates an execution code that causes the processor to execute a command included in the computer program based on the command included in the computer program.
The program verification execution unit 112-n of the calculation unit 110-n executes the first simulation based on the execution code generated by the code generation unit 111-n.
The clock control unit 113-n of the calculation unit 110-n sets the frequency of the operation clock when the first simulation is executed by the program verification execution unit 112-n to the execution code generated by the code generation unit 111-n. Control based on.

Here, the configuration of the calculation unit 110-n and the execution function of the first simulation by the calculation unit 110-n will be described in more detail with reference to FIGS.
As shown in FIG. 3, the code generation unit 111-n of the calculation unit 110-n further includes a command identification unit 111-n-1, a command addition unit 111-n-2, and a compilation unit 111-n-3. It consists of and.

The command identifying unit 111-n-1 receives other commands from the computer program in response to a command included in one computer program that is the execution target of the first simulation by the program verification execution unit 112-n. It is identified whether or not the command affects the operation by the command.
For example, a command for accessing a register of the hardware part described in the SW source code (HW register access command) is a command that affects the processing operation by the HW source code, that is, the operation of the hardware part. The command identifying unit 111-n-1 identifies the HW register access command described in the SW source code from other commands.

The command adding unit 111-n-2 generates an operation clock for executing the first simulation by the program verification execution unit 112-n based on the identification result for the command of the computer program by the command identifying unit 111-n-1. A special command that is a frequency change command is added to the computer program identified by the command identifying unit 111-n-1.
Here, an example of the SW source code to which the special command by the command adding unit 111-n-2 is added is shown in FIGS.

In FIG. 4, among the HW register access commands, the register write command (b) is identified by the command identifying unit 111-n-1, and the command adding unit 111-n-2 is immediately before this register write command (b). A special command (c) for executing the command (a) for controlling the operation clock is added.
In FIG. 5, among the HW register access commands, the register read command (d) is identified by the command identifying unit 111-n-1, and the command adding unit 111-n-2 is immediately after the register read command (d). The special command (e) for executing the command (a) for controlling the operation clock is added.

The compiling unit 111-n-3 performs execution for executing the first simulation by the program verification execution unit 112-n by compiling the computer program to which the special command is added by the command adding unit 111-n-2. Generate code.
For example, the SW source code to which the special instruction is added is compiled, and a binary code that is an instruction word sequence that causes the processor to execute an operation based on the SW source code is generated to enable software simulation.

  The program verification execution unit 112-n executes the first simulation based on the execution code generated by the compilation unit 111-n-3, and the clock control unit 113-n includes the special code added to the execution code. Based on the command, the frequency of the operation clock at the time of executing the first simulation is controlled.

Specifically, an execution code (here, binary code) that can be compiled by the compiling unit 111-n-3 by executing the SW simulation by adding a special command as shown in FIG. The generated program verification execution unit 112-n executes a first simulation for verifying the processing operation in the SW source code by causing the processor to execute the binary code.
At this time, when the clock control unit 113-n reads the special commands (c) and (e) included in the binary code generated by the compiling unit 111-n-3, the clock control unit 113-n The verification speed of the first simulation by the program verification execution unit 112-n is controlled by executing the command (a) for controlling the frequency of the operation clock according to the above.

For example, when controlling the operation clock of the software simulation process based on the binary code corresponding to the SW source code of FIG. 4, the special command (c) is a special command added immediately before the register write command (b). Yes, that is, a special command indicating the start of a register write command that is a command that affects the operation of the hardware.
Therefore, the command (a) for controlling the frequency of the operation clock called in accordance with the special command (c) controls the frequency of the operation clock to a first frequency set in advance that is a frequency for coordinating with the hardware simulation process. .

When the operation clock of the software simulation process is controlled based on the binary code corresponding to the SW source code of FIG. 5, the special command (e) is a special command added immediately after the register read command (d). That is, this is a special command indicating that the hardware operation is not affected by the completion of register reading. Therefore, the command (a) for controlling the frequency of the operation clock called in accordance with the special command (e) controls the frequency of the operation clock to a second frequency which is an arbitrary frequency. The second frequency can be a frequency obtained by multiplying the first frequency by an arbitrary constant.
Each component of the simulation apparatus 10 of the present embodiment described above is realized by installing a computer program (software) in a computer including a CPU, a memory, and an interface mounted on the simulation apparatus 10, and the simulation apparatus described above. The various functions of 10 are realized by the cooperation of various hardware resources of the computer and the computer program.

Next, the operation of the cooperative simulation for a plurality of programs of the simulation apparatus 10 of the present embodiment will be described with reference to the flowcharts shown in FIGS.
As shown in FIG. 6, when a plurality of programs to be simulated are input to the simulation apparatus 10 (S11), whether or not the commands included in each program are commands that affect the operation of other commands. Is identified (S12).

  When a command affecting each other's operation is identified, a special command is added to each program in accordance with the identified command (S13), and an execution code for causing the processor to execute the program with the special command added is executed. Generate (S14).

Subsequently, as shown in FIG. 7, the simulation apparatus 10 starts cooperative simulation for a plurality of programs based on the generated execution code (S21). When the special instruction is read in the execution code, the type of the special instruction is set. Determine (S22).
The special command included in the execution code indicates that the operation that the operation according to the arbitrary command included in the plurality of programs affects each other's operation is started or ended. A special command indicating the start of a command that affects the operation of each other program is referred to as a “first special command”, and a special command indicating the completion of the command is referred to as a “second special command”.

If the simulation apparatus 10 reads the special command from the execution code and then determines the type of the special command, the simulation apparatus 10 determines that the first special command ("first special command" in S22) corresponds to at least one program. The frequency of the simulation operation clock is set to the preset operation clock frequency when executing the cooperative simulation.
On the other hand, as a result of determining the type of the special command, if it is the second special command (“second special command” in S22), the frequency of the simulation operation clock for at least one program is an arbitrary frequency. Control to the second frequency. The second frequency can be a frequency obtained by multiplying the first frequency by an arbitrary constant.

  When the setting of the frequency of the operation clock is completed, the simulation apparatus 10 determines whether or not to end the simulation based on the execution code (S25). When the co-simulation is to be continued (“NO” in S25), the co-simulation is continued based on the execution code, and a simulation end instruction is issued from the user forcibly ending the simulation or an instruction of the execution code. In some cases (“YES” in S25), the simulation apparatus 10 ends the cooperative simulation.

  Here, in a system in which hardware and software cooperate, the function of the system is achieved by causing a processor to execute a hardware program describing an operation model of the hardware part and a software program describing the operation model of the software part. The operation of the simulation apparatus 10 will be described in detail with reference to FIG. 8, taking as an example a HW / SW co-simulation that is simulated by operating it in a pseudo manner.

As shown in FIG. 8, the calculation unit 110-1 of the simulation apparatus 10 operates from the SW source code of the software part of the system, and the calculation unit 110-2 operates from the HW source code of the hardware part of the system. An execution code to which a special command corresponding to the command that affects is added is generated (S101).
After the execution code is generated, the arithmetic units 110-1 and 110-2 start software simulation and hardware simulation based on the execution code with a preset operation clock of the HW / SW co-simulation (S102). . Here, the frequency of the preset operation clock of the HW / SW co-simulation is set as the first frequency.

  When the software simulation and the hardware simulation by the arithmetic units 110-1 and 110-2 are started, the cooperative control unit 120 monitors these simulation processes and synchronizes the results of the simulation processes and the operation timing (S103). ).

  When computing unit 110-1 reads a special command indicating completion of reading from the HW register access command from the execution code of the software simulation (S104), computing unit 110-1 sets the frequency of the operation clock in advance. The first frequency is set to the second frequency (S105). Here, the second frequency is a frequency obtained by multiplying the first frequency by an arbitrary constant m.

  After the frequency of the operation clock is reset, the arithmetic units 110-1 and 110-2 again perform software simulation and hardware simulation based on the execution code with the newly set operation clock (S106). The cooperative control unit 120 monitors these simulation processes and synchronizes the results of the simulation processes and the operation timing (S107). However, since the software operation and the hardware operation executed in S <b> 106 are operations that do not affect each other, the cooperative control unit 120 executes only the monitoring of each simulation process.

  When the arithmetic unit 110-1 reads a special command indicating the start of writing from the HW register access command from the execution code of the software simulation (S108), the arithmetic unit 110-1 is set with the frequency of the operation clock. The first frequency, which is the operation clock frequency of the HW / SW co-simulation set in advance, is set from the frequency of 2 (S109).

After the frequency of the operation clock is set again, the arithmetic units 110-1 and 110-2 continue the software simulation and the hardware simulation based on the execution code with the newly set operation clock (S110). The cooperative control unit 120 monitors these simulation processes and synchronizes the results of the simulation processes and the operation timing (S111).
Here, since the software operation and the hardware operation executed in S110 described above are operations that affect each other, the cooperative control unit 120 monitors each simulation process and outputs each simulation result to each other. Reflect the operation timing of each simulation.

Therefore, based on the execution code generated by compiling the HW source code and the SW source code to which the special command is added by the host computer, the simulation apparatus 10 according to the present embodiment includes a hardware simulator, The software simulator executes hardware simulation processing and software simulation processing, and verifies the causal relationship between the simulation results.
At this time, the simulation apparatus according to the present embodiment controls the frequency of the operation clock of the hardware simulator or software simulator based on the special instruction added to the generated execution code, and according to each simulation process The simulation process is executed at the verification speed.

As described above, according to the present embodiment, when simulating the operation of a system in which a plurality of programs cooperate, it is determined whether or not the operation of the command included in the program affects the operation of each program. By identifying, the execution timing and execution speed of multiple commands are synchronized when executing commands that have an effect, and the execution speed of multiple commands is set according to each command when executing commands that do not affect be able to.
Therefore, useless waiting time can be suppressed in simulation processing of a system in which a plurality of programs cooperate, and simulation efficiency can be improved.

  It can be used as a system level design tool mounted on a host computer, which is a development environment when large-scale LSI development design such as SoC is performed.

  DESCRIPTION OF SYMBOLS 10,20 ... Simulation apparatus, 110-1 to 110-n ... Operation part, 111-1 to 111-n ... Code generation part, 112-1 to 112-n ... Program verification execution part, 113-1 to 113-n ... Operation clock control unit, 111-n-1 ... Command identification unit, 113-n-1 ... Command identification unit, 113-n-1 ... Compilation unit, 120 ... Cooperation control unit, 210 ... Software simulation execution unit, 220 ... Hardware simulation execution unit, 230 ... Co-simulation execution unit.

Claims (3)

A plurality of arithmetic units each simulating different target operations according to a plurality of commands included in the computer program;
A cooperative control unit that controls the operation timing of these calculation units to coordinate the commands executed in the calculation unit;
At least one of the arithmetic units is
A command identifying unit for identifying whether one command among the plurality of commands is a command affecting the operation of the hardware part;
A command addition unit for adding a command to change the frequency of the operation clock to the command of 1 based on the identification result by the command identification unit;
And a clock control unit which controls the operating clock when executing the command in response to a command which the operation unit is executed,
The command identifying unit is
In at least one hardware program in which an operation model in an arbitrary logic circuit is described in a predetermined language, and at least one software program in which an operation model of a function by an arbitrary processor is described in a predetermined language, Extracting a read completion command indicating completion of reading of data stored in the hardware register and a write start command indicating start of writing;
The command adding unit is
A first frequency in which the frequency of the clock is predetermined immediately after the extracted read completion command for the hardware program or the software program from which the read completion command and the write completion command are extracted by the command identification unit. A first command for changing the frequency of the clock to an arbitrary second frequency, and a second command for changing the frequency of the clock to the predetermined first frequency immediately before the extracted write start command. Was added,
The clock control unit
The simulation apparatus, wherein the frequency of the operation clock is controlled based on the command added by the command adding unit . A plurality of arithmetic units each simulating different target operations according to a plurality of commands included in the computer program, and cooperative control for controlling the operation timing of these arithmetic units and coordinating the commands executed in the arithmetic units A control method of a simulation apparatus comprising:
The plurality of calculation units each simulates the operation of different objects according to the plurality of commands, and
The cooperative control unit controls the operation timing of the plurality of calculation steps to coordinate the commands executed in the plurality of calculation steps, and the command according to the commands executed by the calculation steps. A clock control step for controlling the operation clock when executing , and
The calculation step executed by at least one of the calculation units includes:
A command identifying step for identifying whether one command among the plurality of commands is a command affecting an operation based on another command;
A command addition step of adding a command to change the frequency of the operation clock based on the identification result of the command identification step to the one command;
The command identifying step includes
In at least one hardware program in which an operation model in an arbitrary logic circuit is described in a predetermined language, and at least one software program in which an operation model of a function by an arbitrary processor is described in a predetermined language, Extracting a read completion command indicating completion of reading of data stored in the hardware register and a write start command indicating start of writing;
The command adding step includes:
For the hardware program or the software program from which the read completion command and the write completion command have been extracted by the command identification step, a frequency of the operation clock is determined in advance immediately after the extracted read completion command. A first command for changing from one frequency to an arbitrary second frequency is added, and the frequency of the operation clock is changed to the predetermined first frequency immediately before the extracted write start command. Add a second command,
The clock control step includes
The simulation apparatus control method , wherein the cooperative control unit controls the frequency of the operation clock based on the command added in the command adding step . A computer-readable storage medium storing a simulation program for causing a computer to execute the simulation apparatus control method according to claim 2 .

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