JP2003242193A - Logic verifying device for reproducing and executing cooperation simulation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To completely reproduce a cooperation simulation when a failure is found in a verification design in a logic verifying device by the cooperation simulation. <P>SOLUTION: In a tracer 200, a command trace part 201 receives an execution status of a clock for emulation and a request/response command from an emulator input/output part 121, calculates a count number of the clock for emulation, prepares execution trace information for making the request/response command and the count number of the clock for emulation correspond to each other, and records the information in a trace buffer 202. A comparator 203 compares the execution trace information from the command trace part 201 and reproduction trace information from the trace buffer 202 and decides coincidence/ noncoincidence. A synchronous control part 204 decides the comparison result from the comparator 203 and delivers a command to reproduce the cooperation emulation to a transfer control part 122. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification device for reproducing and executing co-simulation, and more particularly to a logic verification device for reproducing and executing co-simulation using an emulator and a logic simulator.

[0002]

2. Description of the Related Art In designing a logic circuit of a computer or the like, a means for verifying the operation of the designed logic circuit is essential. As one of verification methods, a reconfigurable logic IC (Inte
There is an emulator composed of a grated circuit). The most common method is to configure a design circuit to be the target of logic verification (hereinafter referred to as verification design) on the emulator, and to connect the actual hardware to the emulator other than that. However, a method of running a logic simulator by software on a machine different from the emulator without using actual hardware and performing logic verification in cooperation with the emulator (targetless co-simulation method) has also been established.

As an example, MPU (Micro-Proc
essing Unit), memory, and I / O (I
A case will be taken up in which a machine configured from an nput / output device is designed, an MPU is used for verification design, and an I / O device is used as a virtual I / O process of a logic simulator to perform logic verification. In such a configuration, data is frequently exchanged between the MPU and the memory, and the I / O device uses the MP
Upon receiving an I / O request from the U, data will be transferred to and from the memory. The data transfer method includes program I / O transfer (PI / O transfer) via the MPU and DMA (Direct Memory A) for direct transfer to the memory.
access), but DMA transfer is generally used because it is faster.

FIG. 11 is a circuit block diagram showing a configuration of a logic verification device by prior art co-simulation, which has been proposed by the inventor of the present application (Japanese Patent Application No. 2001-006).
081). The configuration and operation of the logic verification device by the co-simulation of this prior art will be described in detail as a part of the first embodiment in the section of the embodiment of the invention described later, so it will not be described here in detail. The following effects can be obtained.

Virtual I / O process 110 and mounted memory 1
By performing the data transfer between 25 by the DMA transfer, the emulation and the I / O operation proceed at the same time, so that the effect of the co-simulation is maximized.

Further, in the co-simulation between the emulator 100 and the virtual I / O process 110, the control of the emulation clock is entrusted to the hardware control of the memory board 120, which allows easier and faster control than software control.

Further, it is not necessary to frequently switch the trigger of the emulator 100, and the reduction of the emulation speed due to the switching of the trigger is eliminated.

Furthermore, the verification using the large-capacity mounted memory 125 can be performed regardless of the mounted capacity of the memory mounted on the emulator 100.

[0009]

However, in the above-described logic verification device by the co-simulation of the prior art, when a defect is found in the verification design in the co-simulation, there is a case where it cannot be completely reproduced by re-execution. It was This is because the following points have not been reproduced.

Since all controls are on-demand, even in the co-simulation with exactly the same contents, the memory refresh and signal arbitration timing depending on the execution time change. Therefore, the timing of the response signal corresponding to the input to the emulator and the emulation clock count number cannot be exactly reproduced from the previous co-simulation.

The virtual I / O process 110 is a UNIX
Since it operates on an operating system such as (registered trademark), its operating speed fluctuates depending on the load of the machine on which the operating system operates, and the response time cannot be predicted.

An object of the present invention is to provide a logic verification device for co-simulation in the prior art which reproduces and executes co-simulation that completely reproduces co-simulation when a defect is found in the verification design. Especially.

[0013]

A logic verification apparatus for reproducing and executing co-simulation according to the present invention is a logic verification apparatus for performing co-simulation by an emulator and a logic simulator. The command and the clock count number for emulation in which the request / response command is generated are recorded, and when the previous co-simulation is reproduced, the request / response command and the request / response command being reproduced are reproduced.
Compares the emulation clock count generated by the response command with the recorded request / response command and emulation clock count. If the emulation clock count and the request / response command do not match, continue the comparison. , If the emulation clock count number and the request / response command match, command the execution of the request / response command, and if only the emulation clock count number matches, command the stop of the emulation clock and request. -It is characterized by having a tracer for instructing suspension of the request / response command when only the response command matches.

Further, the logic verification apparatus for reproducing and executing the co-simulation of the present invention is a verification design in which a circuit for logic verification is modeled, a clock supply circuit for supplying an emulation clock to the verification design, and the clock supply circuit. A virtual I / O process for performing a DMA transfer between an emulator having an emulator control unit for controlling the supply of an emulation clock to the embedded memory, and a mounted memory in response to an I / O request from the verification design; An emulator input / output unit that transmits and receives data in synchronization with the emulation clock of the verification design supplied from the emulator,
A DMA transfer unit that communicates with the virtual I / O process to access the mounted memory independently of the emulator, a memory access request from the emulator input / output unit that is a controller of the mounted memory, and the DMA transfer A memory controller that arbitrates a DMA request and a memory refresh request from a memory unit, and a memory board that includes a transfer controller that controls the own memory board to operate in cooperation with the emulator and the virtual I / O process; Receives the emulation clock and the execution status of the request / response command from the emulator input / output unit, calculates the emulation clock count number, and creates execution trace information that associates the request / response command with the emulation clock count number. Command trace section, a trace buffer for recording execution trace information from the command trace section and supplying the recorded execution trace information as reproduction trace information, execution trace information from the command trace section and reproduction trace from the trace buffer If the emulation clock count number and the request / response command do not match based on the comparator that compares the information and the comparison result from the comparator, the comparison is continued, and the emulation clock count number and the request / response command When the commands match, the transfer control unit is instructed to execute the request / response command, and when only the emulation clock count numbers match, the transfer control unit is instructed to stop the emulation clock of the emulator. And, if only request-response command matches is characterized by having a tracer and a synchronization control unit for commanding holding of the request-response command to the transfer controller.

Further, the logic verification apparatus for reproducing and executing the co-simulation of the present invention is a verification design in which a circuit for logic verification is modeled, a clock supply circuit for supplying an emulation clock to the verification design, and the clock supply circuit. An emulator having an emulator control unit for controlling supply of an emulation clock to the I / O device, an I / O device for performing DMA transfer between the mounted memory in response to an I / O request from the verification design, the mounted memory, the An emulator input / output unit that transmits and receives data in synchronization with the emulation clock of the verification design supplied from the emulator, communicates with the I / O device, and accesses the mounted memory independently of the emulator. O device control unit, control unit of the mounting memory A memory controller that arbitrates a memory access request from the emulator input / output unit, a DMA request and a memory refresh request from the I / O device control unit, and its own memory in cooperation with the emulator and the I / O device. A memory board having a transfer control unit that controls the board to operate, and an emulation clock and an execution status of a request / response command from the emulator input / output unit are received, and an emulation clock count number is calculated to make a request / request. A command trace section for creating execution trace information in which a response command and an emulation clock count number are associated with each other, the execution trace information from the command trace section is recorded, and the recorded execution trace information is referred to as reproduction trace information. Based on the comparison result from the comparator, and the trace buffer supplied as a trace buffer, the execution trace information from the command trace section and the reproduction trace information from the trace buffer, and the request count and request for emulation. If the response commands do not match, the comparison is continued. If the emulation clock count number and the request / response command match, the transfer control unit is instructed to execute the request / response command, and the emulation clock count. When only the numbers match, the transfer control unit is instructed to stop the emulation clock of the emulator, and when only the request / response commands match, the transfer control unit is instructed to hold the request / response command. And a tracer having a synchronization control unit for It is characterized by doing.

Furthermore, the logic verification apparatus for reproducing and executing the co-simulation according to the present invention is a verification design in which a circuit for logic verification is modeled, a clock supply circuit for supplying an emulation clock to the verification design, and the clock supply. A virtual I that performs DMA transfer between an emulator that includes an emulator control unit that controls the supply of an emulation clock to a circuit and a mounted memory in response to an I / O request from the verification design.
/ O process and virtual M that operates as a virtual MPU
The PU process, the mounted memory, the emulator input / output unit that transmits and receives data in synchronization with the verification design emulation clock supplied from the emulator, communicates with the virtual I / O process, and is independent of the emulator. To access the mounted memory by D
MA transfer unit, control unit of the mounted memory, memory access request from the emulator input / output unit, DM
A memory controller that arbitrates the DMA request and the memory refresh request from the A transfer unit, a transfer control unit that controls the own memory board to operate in cooperation with the emulator and the virtual I / O process,
And a memory board having a virtual MPU input / output unit for transmitting / receiving data to / from the virtual MPU process, and an emulation clock and execution status of request / response commands from the emulator input / output unit
A command trace unit that calculates the emulation clock count number and creates execution trace information that associates the request / response command with the emulation clock count number, and records the execution trace information from the command trace unit. A trace buffer that supplies execution trace information as reproduction trace information,
A comparator that compares the execution trace information from the command trace unit with the reproduction trace information from the trace buffer, and the emulation clock count number and the request / response command do not match based on the comparison result from the comparator. If, continue to compare,
When the emulation clock count number and the request / response command match, the transfer control unit is instructed to execute the request / response command, and when only the emulation clock count number matches, the emulator emulation clock And a tracer having a synchronization control unit for instructing the transfer control unit to hold the request / response command when only the request / response commands match. And

Further, the logic verification apparatus for reproducing and executing the co-simulation according to the present invention is a verification design in which a circuit for logic verification is modeled, a clock supply circuit for supplying an emulation clock to the verification design, and the clock supply circuit. An emulator having an emulator control unit for controlling the supply of an emulation clock to the I / O device, and an I / O device for performing DMA transfer between the mounted memory in response to the I / O request from the verification design.
A virtual MPU process that operates as a virtual MPU,
The mounted memory, an emulator input / output unit that transmits and receives data in synchronization with an emulation clock of the verification design supplied from the emulator, and the I / O
A DMA transfer unit that communicates with the O device to access the mounted memory independently of the emulator, a memory access request from the emulator input / output unit that is a controller of the mounted memory, and a DMA from the DMA transfer unit. Requests, and a memory controller that arbitrates memory refresh requests, a transfer controller that controls the own memory board to operate in cooperation with the emulator and the I / O device, and data transmission / reception with the virtual MPU process. A memory board having a virtual MPU input / output unit to be executed and an emulation clock and an execution status of a request / response command from the emulator input / output unit are received, and an emulation clock count is calculated to calculate the request / response command and the emulation clock. Cow Command trace section that creates execution trace information in association with the number of traces, a trace buffer that records the execution trace information from the command trace section and supplies the recorded execution trace information as reproduction trace information, and the command trace section Comparing the execution trace information of the above with the trace information reproduced from the trace buffer, and based on the comparison result from the comparator, if the emulation clock count number and the request / response command do not match, a comparison is made. If the emulation clock count number and the request / response command match, the transfer control unit is instructed to execute the request / response command, and if only the emulation clock count number matches, the emulator Emulation And a synchronization control unit for instructing the transfer control unit to suspend the request clock and, when only the request / response commands match, to suspend the request / response command to the transfer control unit. It is characterized by having.

Further, in the logic verification apparatus for reproducing and executing the co-simulation of the present invention, the request / response command is a data transfer request command from the emulator to the virtual I / O process, or the virtual I / O process. Data transfer end response command to the emulator,
There are four types of commands, an access request command from the emulator to the memory board and an access response command from the memory board to the emulator.

Furthermore, the logic verification device for reproducing and executing the co-simulation of the present invention is characterized in that the memory board operates at a high-speed clock independent of the verification design.

Further, the logic verification apparatus for reproducing and executing the co-simulation according to the present invention models two MPUs as the verification design and configures the other MPU as the virtual MPU process to construct two MPUs.
It is characterized in that logic verification of a multiprocessor consisting of U is performed.

Further, the logic verification apparatus for reproducing and executing the co-simulation according to the present invention operates the commercial MPU model as the virtual MPU process, and models the chipset connected to the MPU as the verification design to obtain the chip. It is characterized by performing logical verification of the set.

On the other hand, the co-simulation reproduction / execution method in the logic verification device for executing co-simulation reproduction / execution according to the present invention is the co-simulation reproduction / execution method in the logic verification device for co-simulation by the emulator and the logic simulator. Therefore, the request / response command generated during the execution of the co-simulation and the emulation clock count number generated by the request / response command are recorded. The response command and the emulation clock count number generated by the request / response command are compared with the recorded request / response command and emulation clock count number, and the emulation clock count number and the request / response frame are compared. If both codes do not match, the comparison is continued. If the emulation clock count number and the request / response command match, the request / response command is executed. If only the emulation clock count number matches, the emulation The clock is stopped, and when only the request / response command matches, the request / response command is held.

In the present invention, in order to solve the reproducibility of the co-simulation and to realize the optimum co-simulation, a tracer block is added to the logic verification device by the co-simulation of the prior art, and the reproducibility is improved. Equipped with a mechanism to guarantee. Tracer
The request / response command generated during the execution of the co-simulation and the emulation clock count number generated by the request / response command are recorded.
The response command and the emulation clock count number generated by the request / response command are compared with the recorded request / response command and emulation clock count numbers, and the emulation clock count number and the request / response command do not match. If the emulation clock count number and the request / response command match, the execution of the request / response command is instructed. If only the emulation clock count number matches, the emulation clock count The stop is instructed, and when only the request / response commands match, the request / response command is suspended. The function of this tracer makes it possible to reproduce a co-simulation whose timing is exactly the same as the previous time.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing the arrangement of a logic verification apparatus for reproducing and executing a co-simulation according to the first embodiment of the present invention. The logic verification device for reproducing and executing the co-simulation according to the present embodiment includes an emulator 100 and a virtual I / O.
Process 110, memory board 120, tracer 2
00 and the main parts thereof are configured.

The emulator 100 includes a verification design 101 in which a circuit for performing actual logic verification is modeled, a clock supply circuit 103 for supplying an emulation clock to the verification design 101, and a clock supply circuit 103.
And an emulator control unit 102 for controlling the supply of the emulation clock to the.

The virtual I / O process 110 DMA-transfers data to and from the mounting memory 125 in response to an I / O request from the verification design 101.

The memory board 120 includes an emulator input / output unit 121, a transfer control unit 122, and a DMA transfer unit 12.
3, memory controller 124, and mounted memory 125
Composed of and. The memory board 120 has a high-speed clock independent of the verification design 101 (hereinafter referred to as an internal clock), for example, the verification design 101 has several MH.
It operates with a clock of z, but operates at tens of MHz, which is one digit higher.

The emulator input / output unit 121 transmits / receives data in synchronization with the emulation clock of the verification design 101 supplied from the emulator 100.

The DMA transfer unit 123 communicates with the virtual I / O process 110, and independently of the emulator 100, the mounted memory 125 via the memory controller 124.
To access.

The transfer control unit 122 uses the emulator 100.
Also, control is performed so that the memory board 120 operates in cooperation with the virtual I / O process 110. Also,
It has a function of exchanging signals with the tracer 200 and giving an instruction to the clock supply circuit 103 in the emulator 100 in order to stop / restart the emulation of the verification design 101 according to a command request and a reproduction condition.

The memory controller 124 is a control unit of the mounting memory 125, and is a block that actually reads and writes data from the mounting memory 125. It also controls the memory refresh operation. The memory controller 124 has memory access requests from three locations at maximum, that is, a memory refresh request, a memory access request from the emulator input / output unit 121, and a DM from the DMA transfer unit 123.
When the A requests overlap, the transfer control unit 122 and the memory access request are arbitrated, the synchronization timing is calculated, and the priority order of the memory access request is determined. Then, the mounting memory 125 is accessed in the determined order, and the result is sent to each request source.

The tracer 200 is a block for completely reproducing the co-simulation, and includes a command trace section 201, a trace buffer 202, and a comparator 2.
03 and a synchronization control unit 204.

The command trace section 201 receives from the emulator input / output section 121 the emulation clock and the execution status of request / response commands such as data transmission / reception, calculates the current emulation clock count number, and outputs the request / response commands. Create execution trace information that correlates with the clock count for emulation. However, the request / response command for creating the execution trace information is a data transfer request command from the emulator 100 to the virtual I / O process 110, a data transfer end response command from the virtual I / O process 110 to the emulator 100, or the emulator 100. From the memory board 120 to the memory board 120 and an access response command from the memory board 120 to the emulator 100. Request / response commands other than these request / response commands that are closed by the memory board 120 and virtual I / O process 110 need not be synchronized with the emulation clock of the emulator 100, and these operations need to be synchronized. Execution trace information is not created because it should be processed behind a certain request / response command.

The trace buffer 202 records the execution trace information from the command trace unit 201. In addition, the comparator 203 uses the recorded execution trace information as reproduction trace information for reproducing the co-emulation.
Supply to.

The comparator 203 includes a command trace unit 20.
The execution trace information from 1 and the reproduction trace information from the trace buffer 202 are compared to determine a match / mismatch.

The synchronization control unit 204 determines the comparison result from the comparator 203 in synchronization with the synchronization signal of the emulation clock and the internal clock from the transfer control unit 122,
A command for reproducing the cooperative emulation is sent to the transfer control unit 122. The commands include a request / response command suspension instruction / instruction cancellation and an emulation clock stop instruction / instruction cancellation.

Referring to FIG. 2, the process of the emulator 100 is emulation execution environment setup step S101, emulation clock supply start step S102, and emulation step S103.
An emulation clock supply stop determination step S104, an emulation clock supply stop step S105, a restart request detection step S106, and an emulation clock supply restart step S107.

Referring to FIG. 3, virtual I / O process 1
The process of 10 is the co-simulation preparation step S1.
11, I / O request determination step S112, DMA transfer step S113, and DMA transfer end determination step S112.
And 114.

Referring to FIG. 4, the process of the memory board 120 includes initialization / emulation setting step S12.
1, a request detection step S122, a memory refresh step S123, a mounted memory access step S124, an I / O request command step S125 to the DMA transfer unit, and a DMA transfer end notification step S126.

Referring to FIG. 5, the processing of the DMA transfer unit 123 is performed by initialization / emulation setting step S13.
1, I / O request determination step S132, DMA transfer preparation step S133, and I / O to the virtual I / O process.
O request issuing step S134, DMA transfer executing step S135, transfer end determining step S136, DM
A transfer end notification step S137.

Referring to FIG. 6, the processing in the trace mode of the tracer 200 includes a trace buffer initialization step S201, an initialization / emulation setting step S202, and a request / response command presence / absence determination step S2.
03, a request / response command and emulation clock count number recording step S204, and a request / response command execution step S205.

Referring to FIG. 7, the process of the tracer 200 in the reproduction mode is the reproduction trace information loading step S.
301 and initialization / emulation setting step S3
02 and reproduction trace information reading step S303
A comparison result determination step S304, a request / response command execution step S305, an emulation clock stop and a request / response command hold release step S
306 and request / response command match determination step S31
1 and emulation clock stop step S31
2, an emulation clock count number coincidence determination step S321, and a request / response command suspension step 322.

Next, the operation of the logic verification device configured to reproduce and execute the co-simulation according to the first embodiment will be described.

In this embodiment, it is not always necessary to stop / restart the emulation clock for the verification design 101 for each I / O request. The emulation clock to the verification design 101 is stopped only when the processing time of the emulator 100 or the virtual I / O process 110 is different from that of the actual machine, and when exception processing of the verification job executed by the verification design 101 is performed. It is the case. Since each block of this embodiment operates in cooperation with each other, the operation of each block will be described. Actually, there is a higher-level process that manages the operations of all blocks, but the processing of the higher-level process is mainly responsible for overall management and activation / termination, and is omitted here because it is not related to the gist of the present invention.

First, the operation of the emulator 100 will be described.

Step S101: The model data of the verification design 101 is loaded into the emulator 100 to set up an environment in which emulation can be executed.

Step S102: Next, the emulator control section 102 commands the clock supply circuit 103 to start the supply of the emulation clock. As a result, the clock supply circuit 103 starts supplying the emulation clock to the verification design 101, and the verification design 101 starts emulation. The verification design 101 also supplies the emulation clock to the memory board 120 for synchronization.

Step S103: When the emulation progresses and an I / O request is issued from the verification design 101, the verification design 101 does not use this I / O request as a trigger for the emulator control unit 102, but directly. It is sent to the transfer control unit 122 via the emulator input / output unit 121 of the memory board 120. The I / O request is processed by the transfer control unit 122. The verification design 101 continues the emulation as it is.

Steps S104 and S105: When the clock supply circuit 103 receives a request for stopping the emulation clock from the transfer control unit 122, the clock supply circuit 103 stops the supply of the emulation clock and the verification design 101 Stop emulation.

Steps S106 and S107: When the clock supply circuit 103 receives a request for restarting the emulation clock from the transfer control unit 122, the clock supply circuit 103 restarts the supply of the emulation clock and the verification design 101 Restart emulation.

The transfer controller 122 sends a DMA transfer end notification to the verification design 10 through the emulator input / output unit 121.
If you send it to 1, the verification design 101,
It is processed by emulation.

Next, the operation of the virtual I / O process 110 will be described.

Step S111: First, the virtual I / O process 110 first makes necessary initial settings and the like to prepare for co-simulation.

Step S112: Next, the virtual I / O process 110 waits for an I / O request from the verification design 101 (wait state). This I / O request is actually received from the emulator input / output unit 121 by the transfer control unit 122 and reaches the virtual I / O process 110 via the DMA transfer unit 123.

Step S113: When there is an I / O request,
The virtual I / O process 110 transmits / receives data to / from the memory board 120. The data is DMA-transferred by communication with the DMA transfer unit 122.

Step S114: D based on I / O request
When the MA transfer is completed, the virtual I / O process 110 notifies the memory board 120 to that effect. Alternatively, the end of the last data transfer is detected on the memory board 120 side. After this, the virtual I / O process 110 executes the DMA
The transfer is ended, and the control is returned to step S112 to return to the wait state.

Next, the operation of the memory board 120 will be described. The memory board 120 operates with a high-speed clock independent of the emulator 100, and
Even if the requests for 5 conflict (collide), it is possible to perform arbitration without affecting the response to the emulator 100 or the virtual I / O process 110. This arbitration function enables the memory board 120 to simultaneously accept and process a plurality of requests and DMA transfers.

Step S121: First, the upper process sets the memory board 120 for initialization and emulation. A DRAM (Dynami) whose mounted memory 125 requires a memory refresh operation.
In the case of a module such as c Random Access Memory), refresh control is enabled, and a memory refresh operation is set according to a specified cycle.

Step S122: When there is a request from the verification design 101 to the memory board 120, the emulator input / output unit 121 accepts the request, and the request is sent to the transfer control unit 122. The transfer control unit 122 determines the content of the request and issues a memory access request or an I / O request to the memory controller 124 or the DMA transfer unit 123.
Further, a request for internal processing of the memory board 120 is
The memory controller 12 is controlled by the transfer control unit 122 itself.
Issued to 4.

When the requests conflict with each other, the memory controller 124 arbitrates the requests and executes the respective processes.

Step S123: In the case of a refresh request, the memory controller 124 determines the mounted memory 125.
Refresh process.

Step S124: In the case of a memory access request, the memory controller 124 causes the mounted memory 12
5 to read / write data and to / from the emulator input / output unit 121. Emulator input / output section 1
Reference numeral 21 transfers data in synchronization with the emulation clock supplied from the verification design 101.

Step S125: In case of I / O request,
The DMA transfer unit 123 is instructed to prepare for DMA transfer and issue an I / O request to the virtual I / O process 110. The DMA transfer unit 123 that has received the instruction executes the processes of steps S133 to S137 described below. The transfer control unit 122 stores that the I / O request has been issued, and returns the control to step S122 to accept the next request.

Step S126: The DMA transfer unit 123 finishes the DMA transfer, and the transfer control unit 1 is sent in Step S137.
I received the transfer end notification sent to 22 and memorized it
I / O request termination processing, that is, notification of DMA transfer termination via the emulator I / O unit 121.
Go to 1.

In addition to the operation described above, the transfer control unit 122 performs control necessary for co-simulation between the memory board 120 and other blocks. When it is necessary to control the emulation clock to the verification design 101, the clock supply circuit 103 is requested to stop and restart the emulation clock.

Next, the DMA transfer processing performed by the DMA transfer unit 123 will be described.

The DMA transfer unit 123 communicates with the virtual I / O process 110 to notify the I / O request and DM between the virtual I / O process 110 and the mounted memory 125.
Control A transfer.

Step S131: Simultaneously with step S121, the DMA transfer section 123 is initialized and the emulation is set.

Step S132: DMA transfer section 123
Waits for an I / O request command from the transfer control unit 122.

Step S133: DMA transfer section 123
Receives an I / O request command and prepares for DMA transfer.

Step S134: DMA transfer section 123
Issues an I / O request to the virtual I / O process 110.

Steps S135 and S136: The DMA transfer section 123 mediates the DMA transfer between the virtual I / O process 110 and the mounted memory 125. During this time, the memory controller 124 performs arbitration when the DMA transfer conflicts with another request, and reads / writes data from / to the mounting memory 125 at an appropriate timing.

Step S137: When the final DMA transfer based on the I / O request is completed, the DMA transfer section 123
This is notified to the transfer control unit 122, and step S132
Return control to and wait for the next command.

Next, the operation of the tracer 200 will be described.

The tracer 200 has two kinds of operation modes. One is a trace mode in which recording is performed to reproduce the operation of the emulator 100, and the other is a reproduction mode in which the previous cooperative emulation is reproduced. In the trace mode, the tracer 200
Execution trace information is recorded which is a pair of a request / response command that is synchronized for reproduction during execution of the co-simulation and a number of emulation clock counts generated by the request / response command. In the reproduction mode, the tracer 200 uses the recorded execution trace information as reproduction trace information to synchronize the previous co-simulation with the reproduced co-simulation.

First, the trace mode will be described (see FIG. 6).

Step S201: By the upper process,
The contents of the trace buffer 202 are initialized and writing is permitted.

Step S202: By the upper process,
Settings required for initialization and emulation are made.

Step S203: Command trace unit 2
01 indicates a request executed by the emulator 100 and the memory board 120 from the emulator input / output unit 121.
The execution status indicating the response command is always sent, and the four types of requests for recording execution trace information
Check the response command. When a request / response command for recording execution trace information is generated, control is passed to step S204.

Step S204: Command trace unit 2
The request / response command output from 01 is associated with the emulation clock count number and recorded in the trace buffer 202 as execution trace information. The request / response command and the emulation clock count number at which the request / response command is generated are recorded as a set of execution trace information. When a plurality of request / response commands are generated with the same emulation clock count number, the logical sum of all request / response commands generated with respect to the emulation clock count number is recorded.

Step S205: The request / response command is executed. Specifically, the synchronization control unit 204 sends a command for canceling the hold of the request / response command to the transfer control unit 122, and the transfer control unit 122 causes the emulator input / output unit 12 to operate.
1 or by instructing the DMA transfer unit 123 to release the hold of the request / response command, the request / response command is executed. Then, control is returned to step S203.

Next, the reproduction mode will be described (see FIG. 7).
reference).

When reproducing the previous co-simulation, the tracer 200 records execution trace information consisting of the request / response command being reproduced and the emulation clock count number at which the request / response command is generated. The comparator 203 compares the reproduced trace information including the request / response command and the emulation clock count number, and based on the comparison result, the synchronization control unit 204 determines that the emulation clock count number and the request / response command do not match. If the emulation clock count number and the request / response command match, the transfer control unit 122 is instructed to execute the request / response command, and if the emulation clock count number only matches. Emulation Transfer control unit to stop the use clock 12
2, and if only the request / response command matches, the transfer control unit 122 is instructed to hold the request / response command. With the function of the tracer 200, it is possible to reproduce a co-simulation whose timing is exactly the same as the previous time.

Step S301: By the upper process,
The reproduction trace information recorded in the trace mode at the time of the previous co-simulation is taken out from the saved file or the like, set in the trace buffer 202, and the reading is permitted.

Step S302: By the upper process,
Settings required for initialization and emulation are made.

Step S303: Trace buffer 20
The reproduction trace information to be compared is read from 2,
It is supplied to the comparator 203. The order of the reproduced trace information to be read is determined in the order of the recorded emulation clock count number.

Step S304: The comparator 203 compares the execution trace information sent from the command trace unit 201 with the reproduction trace information sent from the trace buffer 202. If both the emulation clock count and the request / response command do not match, the comparison continues. If only the emulation clock count numbers match, control is passed to step S311. If only the request / response commands match, step S3
Control is transferred to 21.

Step S311: The execution trace information request / response command is compared with the reproduction trace information request / response command. If they match, control is passed to step S305. If they do not match, if the supply of the emulation clock is further continued, the synchronization will not be established, so the control is shifted to step S312.

Step S312: The synchronization control unit 204
The transfer control unit 122 is instructed to stop the emulation clock of the emulator 100, and the transfer control unit 122 stops the transmission of the emulation clock from the clock supply circuit 103.

Step S321: The emulation clock count number of the execution trace information is compared with the emulation clock count number of the reproduction trace information. If they match, control is passed to step S305. If they do not match, synchronization cannot be achieved, so step S3
Control is transferred to 22.

Step S322: The synchronization control unit 204 sends a command to hold the request / response command to the transfer control unit 122, and the transfer control unit 122 causes the emulator input / output unit 12 to operate.
1 and the execution instruction of the request / response command issued to the DMA transfer unit 123 is suspended. As a result, the request / response command is put on hold until the emulation clock count numbers match.

Step S305: The request / response command is executed. Specifically, the synchronization control unit 204 sends a command for canceling the hold of the request / response command to the transfer control unit 122, and the transfer control unit 122 causes the emulator input / output unit 12 to operate.
1 or by instructing the DMA transfer unit 123 to release the hold of the request / response command, the request / response command is executed.

Step S306: If the emulation clock is stopped in step S312 or the request / response command is suspended in step S322, the emulation clock is suspended or the request / response command is suspended, and the process returns to step S303.
Control is transferred to the next process to be compared.

With the above-described reproduction mode, the emulator 100 operates at the timing completely matching the reproduction trace information which is the execution record of the previous co-simulation,
Co-simulation results are reproduced.

According to the first embodiment, the emulator 1 of the verification design 101 in the co-simulation is used.
Design 101 running on emulator 100 by ensuring complete reproducibility of operation on
It becomes possible to promptly identify the defect depending on the operation timing, which has occurred in step 1, and to realize more effective logic verification.

[Second Embodiment] FIG. 8 is a circuit block diagram showing the structure of a logic verification device for reproducing and executing a co-simulation according to a second embodiment of the present invention. The logic verification apparatus for reproducing and executing the co-simulation according to the present embodiment replaces the virtual I / O process 110 in the logic verification apparatus for reproducing and executing the co-simulation according to the first embodiment shown in FIG. hand,
The actual I / O device 130 is used. Therefore, DM
The A transfer unit 123 is replaced with the I / O device control unit 126, but functionally includes the function of the DMA transfer unit 123. Further, since the I / O device 130 needs to receive a command other than the I / O request from the verification design 101, the determination function is added to the memory board 120.

Next, the operation of the logic verification device configured to reproduce and execute the co-simulation according to the second embodiment will be described. It should be noted that the description of the part that performs the same operation as the logic verification device that executes the reproduction of the co-simulation according to the first embodiment shown in FIG. 1 will be omitted.

A request from the verification design 101 is accepted by the emulator input / output unit 121 and processed under the control of the transfer control unit 122. In the case of a normal memory access request, the memory access request is sent to the memory controller 124 as it is, and the data is read / written from / to the mounting memory 125. Command or I / O to I / O device 130
If it is a request, the transfer control unit 122 judges it and
A command or I / O request is issued to the I / O device control unit 126.

The I / O device controller 126 controls the I / O device 1
30 to control the command or I / O request processing. When the execution is completed, the transfer control unit 122 is notified of that fact.

The transfer control unit 122 uses the command or I /
The verification design 101 is notified of the completion of the execution of the O request via the emulator input / output unit 121.

When it is necessary to control the emulation clock for the verification design 101, the transfer control unit 122 requests the clock supply circuit 103 to stop and restart the emulation clock.

As described above, according to the second embodiment,
By performing data transfer between the I / O device 130 and the mounted memory 125 by DMA transfer, emulation and I / O
Since the O operation and the O operation proceed at the same time, the effect of the co-simulation is maximized.

Further, the emulator 100 and the I / O device 1
In the co-simulation between 30, the control of the emulation clock is entrusted to the hardware control of the memory board 120, so that the control can be performed easier and faster than the software control.

Further, it is not necessary to frequently switch the trigger of the emulator 100, and the reduction of the emulation speed due to the switching of the trigger is eliminated.

Furthermore, it is possible to perform verification using the large-capacity mounted memory 125 regardless of the mounted capacity of the memory mounted on the emulator 100.

[Third Embodiment] FIG. 9 is a block diagram showing the configuration of a logic verification apparatus for reproducing and executing co-simulation according to a third embodiment of the present invention. The logical verification device for reproducing and executing the co-simulation according to the third embodiment is different from the logical verification device for executing and reproducing the co-simulation according to the first embodiment shown in FIG. 140 is added. The virtual MPU process 140 includes a virtual MPU.
The input / output unit 128 is connected instead of the emulator input / output unit 121.

In the logic verification apparatus configured to reproduce and execute the co-simulation according to the third embodiment, the virtual MPU process 140 has the verification design 1
01 in parallel, the virtual MPU input / output unit 128 performs the same operation as the emulator input / output unit 121 for the verification design 101 by performing the virtual MPU operation.
This is performed for the PU process 140. Therefore, detailed description of those operations is omitted.

In the logic verification device that executes the reproduction of the co-simulation according to the third embodiment as described above,
The following operational examples are possible.

One is the logic verification of the multiprocessor. If the emulator 100 does not have the capacity to model two MPUs, one MPU can be verified by the verification design 10
Modeling as 1 and configuring the other as a virtual MPU process 140 to perform logic verification.

The other is to use a commercially available MPU model as a virtual MP.
It is an operation in which the chip set connected to the MPU is modeled in the verification design 101 as the U process 140 and the logic verification of the chip set is performed.

The logic verification device for reproducing and executing the co-simulation according to the third embodiment is also equivalent to the logic verification device for executing and reproducing the co-simulation according to the first and second embodiments. It goes without saying that the effect can be obtained.

[Fourth Embodiment] FIG. 10 is a block diagram showing the configuration of a logic verification device for reproducing and executing co-simulation according to a fourth embodiment of the present invention.
The logical verification device for reproducing and executing the co-simulation according to the fourth embodiment is different from the logical verification device for reproducing and executing the co-simulation according to the second embodiment shown in FIG. 8 in the virtual MPU process. 140 is added. The virtual MPU process 140 has a virtual MP
The U input / output unit 128 is connected instead of the emulator input / output unit 121.

In the logic verification apparatus configured as described above for reproducing and executing the co-simulation according to the fourth embodiment, the logic for executing and executing the co-simulation according to the third embodiment shown in FIG. As in the verification device, the virtual MPU process 140 operates the virtual MPU in parallel with the verification design 101 to generate a virtual MPU.
The PU input / output unit 128 performs the same operation as that of the emulator input / output unit 121 for the verification design 101 and the virtual MPU.
Perform on process 140. Therefore, detailed description of those operations is omitted.

The logic verification device for reproducing and executing the co-simulation according to the fourth embodiment is also equivalent to the logic verification device for reproducing and executing the co-simulation according to the first to third embodiments. It goes without saying that the effect can be obtained.

[0116]

The effects obtained by the present invention are as follows.

The first effect is to guarantee the complete reproducibility of the operation of the verification design on the emulator in the co-simulation, so that the defect depending on the operation timing generated by the verification design operating on the emulator can be promptly confirmed. It is possible to specify the above, and more effective logic verification can be realized. The reason is that the tracer compares the request / response command being reproduced and the emulation clock count generated by the request / response command with the recorded request / response command and emulation clock count, Based on the comparison result, if the emulation clock count number and the request / response command do not match, the comparison is continued, and if the emulation clock count number and the request / response command match, the request / response command is executed. Command is issued, and if only the emulation clock counts match, the emulation clock is stopped. If only the request / response commands match, the request / response command is suspended. Is.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a logic verification device for reproducing and executing co-simulation according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a process of an emulator in FIG.

3 is a flowchart showing processing of a virtual I / O process in FIG.

FIG. 4 is a flowchart showing a process of a memory board in FIG.

5 is a flowchart showing a process of a DMA transfer unit in FIG.

FIG. 6 is a flowchart showing processing in the trace mode of the tracer in FIG.

FIG. 7 is a flowchart showing processing in the reproduction mode of the tracer in FIG.

FIG. 8 is a circuit block diagram showing a configuration of a logic verification device for reproducing and executing a co-simulation according to a second embodiment of the present invention.

FIG. 9 is a circuit block diagram showing a configuration of a logic verification device for reproducing and executing co-simulation according to a third embodiment of the present invention.

FIG. 10 is a circuit block diagram showing a configuration of a logic verification device for reproducing and executing co-simulation according to a fourth embodiment of the present invention.

FIG. 11 is a circuit block diagram showing a configuration of a logic verification device based on prior art co-simulation.

[Explanation of symbols]

100 emulator 101 Verification design 102 Emulator control unit 103 clock supply circuit 110 Virtual I / O process 120 memory board 121 Emulator input / output section 122 Transfer control unit 123 DMA transfer unit 124 memory controller 125 mounted memory 126 I / O device controller 128 Virtual MPU input / output unit 130 I / O device 140 Virtual MPU process 200 Tracer 201 Command trace part 202 trace buffer 203 comparator 204 synchronization control unit

Claims (10)

[Claims] 1. A logic verification device for performing a co-simulation by an emulator and a logic simulator, recording a request / response command generated during execution of the co-simulation and an emulation clock count number generated by the request / response command, When reproducing the previous co-simulation, the request / response command being reproduced and the number of emulation clocks generated by the request / response command and the recorded request / response command and the number of emulation clock counts were recorded. If the emulation clock count number and the request / response command do not match, the comparison is continued. If the emulation clock count number and the request / response command match, the request / response command is compared.
Command the execution of a response command, command the stop of the emulation clock when only the number of emulation clock counts matches, and command the suspension of the request / response command when only the request / response command matches. A logic verification device having a tracer for reproducing and executing co-simulation. 2. An emulator comprising a verification design that models a circuit for performing logic verification, a clock supply circuit that supplies an emulation clock to the verification design, and an emulator control unit that controls the supply of the emulation clock to the clock supply circuit. And a virtual I / O process for performing DMA transfer with a mounted memory in response to an I / O request from the verification design, the mounted memory, and synchronization with the emulation clock of the verification design supplied from the emulator. An emulator input / output unit for transmitting and receiving data, a DMA transfer unit for communicating with the virtual I / O process and accessing the mounted memory independently of the emulator, and a controller for the mounted memory, which is the emulator. Memory access request from I / O unit Memory controller performs DMA request and arbitration memory refresh requests from the DMA transfer unit, and the emulator and the virtual I
Memory board including a transfer control unit that controls the own memory board to operate in cooperation with the I / O process, and an emulation clock that receives the emulation clock and the execution status of request / response commands from the emulator input / output unit. A command trace unit that calculates the count number and creates execution trace information in which the request / response command and the emulation clock count number are associated with each other, and records the execution trace information from the command trace unit and the recorded execution trace information. Based on the comparison result from the comparator, and a trace buffer that supplies the execution trace information from the command trace unit with the reproduction trace information from the trace buffer. If the clock count for synchronization and the request / response command do not match, the comparison is continued. If the clock count for emulation and the request / response command match, the request / response command is executed to the transfer control unit. Command, and if only the number of emulation clock counts matches, commands the transfer control unit to stop the emulation clock of the emulator, and if only request / response commands match, holds the request / response command And a tracer having a synchronization control unit for instructing the transfer control unit to execute the co-simulation reproduction execution. 3. An emulator comprising a verification design that models a circuit for performing logic verification, a clock supply circuit that supplies an emulation clock to the verification design, and an emulator control unit that controls the supply of the emulation clock to the clock supply circuit. And an I / O device that performs DMA transfer with the mounted memory in response to an I / O request from the verification design, the mounted memory,
An emulator input / output unit that transmits and receives data in synchronization with the emulation clock of the verification design supplied from the emulator, communicates with the I / O device, and accesses the mounted memory independently of the emulator. / O device control unit, a controller of the mounted memory, which arbitrates memory access requests from the emulator input / output unit, DMA requests and memory refresh requests from the I / O device control unit, and A memory board having a transfer control unit that controls the own memory board to operate in cooperation with the emulator and the I / O device, and receives an emulation clock and execution status of request / response commands from the emulator input / output unit. , Emulation black To calculate the number of clock count, request -
A command trace section for creating execution trace information in which a response command and an emulation clock count number are associated with each other, and a trace buffer for recording the execution trace information from the command trace section and supplying the recorded execution trace information as reproduction trace information. , A comparator that compares the execution trace information from the command trace unit with the reproduction trace information from the trace buffer, and the emulation clock count number and the request / response command are both based on the comparison result from the comparator. If they do not match, the comparison is continued, and if the emulation clock count number and the request / response command match, the transfer control unit is instructed to execute the request / response command. In case of failure, the synchronous control for instructing the transfer control unit to stop the emulator emulation clock, and for instructing the transfer control unit to hold the request / response command when only the request / response command matches. And a tracer having a unit. A logic verification device for reproducing and executing a co-simulation. 4. An emulator comprising a verification design that models a circuit for performing logic verification, a clock supply circuit that supplies an emulation clock to the verification design, and an emulator control unit that controls the supply of the emulation clock to the clock supply circuit. And a virtual I / O process for performing a DMA transfer with a mounted memory in response to an I / O request from the verification design, a virtual MPU process operating as a virtual MPU, the mounted memory, and the emulator. An emulator input / output unit that transmits and receives data in synchronization with the supplied verification design emulation clock, and a DMA transfer unit that communicates with the virtual I / O process and accesses the mounted memory independently of the emulator. , Is the control unit of the mounting memory Memory access request from the emulator input and output unit, DMA requests from the DMA transfer unit, and a memory controller for arbitrating memory refresh request, the emulator and the virtual I / O
A transfer control unit that controls the own memory board to operate in cooperation with a process, and the virtual MPU
A memory board having a virtual MPU input / output unit for transmitting and receiving data to and from a process, and an emulation clock and an execution status of a request / response command from the emulator input / output unit are received, and an emulation clock count number is calculated to make a request / request. A command trace section for creating execution trace information in which a response command and an emulation clock count number are associated with each other, and a trace buffer for recording the execution trace information from the command trace section and supplying the recorded execution trace information as reproduction trace information. , A comparator for comparing the execution trace information from the command trace unit with the reproduction trace information from the trace buffer, and the emulation clock count based on the comparison result from the comparator And the request / response command do not match, the comparison is continued. If the clock count number for emulation and the request / response command match, the transfer control unit is instructed to execute the request / response command to perform emulation. When only the clock count numbers match, the transfer control unit is instructed to stop the emulation clock of the emulator, and when only the request / response commands match, the transfer control unit suspends the request / response command. And a tracer having a synchronous control unit for instructing to the logic verification device for reproducing and executing the co-simulation. 5. An emulator comprising a verification design that models a circuit for performing logic verification, a clock supply circuit that supplies an emulation clock to the verification design, and an emulator control unit that controls the supply of the emulation clock to the clock supply circuit. An I / O device that performs DMA transfer with the mounted memory in response to an I / O request from the verification design, a virtual MPU process that operates as a virtual MPU, the mounted memory,
An emulator input / output unit that transmits and receives data in synchronization with the verification design emulation clock supplied from the emulator, and a DMA that communicates with the I / O device and accesses the mounted memory independently of the emulator. A transfer unit, a control unit of the mounted memory, a memory controller that arbitrates a memory access request from the emulator input / output unit, a DMA request from the DMA transfer unit, and a memory refresh request, the emulator, and the I / O A memory controller including a transfer control unit that controls the own memory board to operate in cooperation with the device, a virtual MPU input / output unit that transmits / receives data to / from the virtual MPU process, and an emulator input / output unit for emulation Clock and request / response Command trace section that receives the command execution status, calculates the emulation clock count number, and creates execution trace information in which the request / response command and the emulation clock count number are associated, and the execution trace from the command trace section A trace buffer that records information and supplies the recorded execution trace information as reproduction trace information, a comparator that compares the execution trace information from the command trace unit with the reproduction trace information from the trace buffer, and the comparator If the emulation clock count number and the request / response command do not match, the comparison is continued based on the result of the comparison, and if the emulation clock count number and the request / response command match, the comparison is completed. -If the transfer control unit is instructed to execute a response command and only the emulation clock counts match, the transfer control unit is instructed to stop the emulator emulation clock, and only the request / response commands match. And a tracer having a synchronous control unit for instructing the transfer control unit to hold the request / response command in the case of performing the above. 6. The request / response command includes a data transfer request command from the emulator to the virtual I / O process, a data transfer end response command from the virtual I / O process to the emulator, and the memory from the emulator. 4. There are four types of access request commands to the board and access response commands from the memory board to the emulator.
A logic verification device for reproducing and executing the co-simulation according to claim 3, claim 4, or claim 5. 7. The reproduction execution of the co-simulation according to claim 2, claim 3, claim 4, or claim 5, wherein the memory board operates with a high-speed clock independent of the verification design. A logic verification device that performs. 8. One MPU is modeled as the verification design, and the other MPU is modeled as the virtual MPU process.
5. The logical verification of a multiprocessor composed of two MPUs is performed by configuring U. 5.
Alternatively, a logic verification device that executes the reproduction of the co-simulation according to claim 5. 9. A commercial MPU as the virtual MPU process
6. The logic simulation of the chipset is performed by moving a model and modeling a chipset connected to the MPU as the verification design. Reproduction execution of the co-simulation according to claim 4 or 5, is performed. Logic verification device. 10. A reproduction / execution method of co-simulation in a logic verification device which performs co-simulation by an emulator and a logic simulator, wherein a request / response command generated during execution of the co-simulation and the request / response command are generated. When the previous co-simulation is reproduced, the request / response command being reproduced and the emulation clock count generated by the request / response command and the recorded request / response command are recorded. The response command and the emulation clock count number are compared. If the emulation clock count number and the request / response command do not match, the comparison is continued. If so, the request / response command is executed. If only the emulation clock count numbers match, the emulation clock is stopped. If only the request / response command matches, the request / response command is executed. Reproduction and execution method of co-simulation characterized by holding.