CN103093059A - Real-time and efficient distributed semi-physical simulation system construction method - Google Patents
Real-time and efficient distributed semi-physical simulation system construction method Download PDFInfo
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Abstract
A real-time and efficient distributed semi-physical simulation system construction method comprises seven steps that a simulation system and a semi-physical simulation interface are respectively arranged on different host computers to form a distributed semi-physical simulation system together with a physical system; the semi-physical simulation interface is arranged as a time-controlled member; the host computer of the semi-physical simulation interface is connected with a global position system (GPS) receiver through a serial port, and the serial port is initialized; a program main thread of the semi-physical simulation interface is in clock synchronization with a GPS; the program main thread of the semi-physical simulation interface sends synchronization information packets to the simulation system and the physical system regularly; clock synchronization among all members of the semi-physical simulation system is achieved; and communication data processing is achieved by a program auxiliary thread of the semi-physical simulation interface. According to the real-time and efficient distributed semi-physical simulation system construction method, computing resources and system overheads are saved, a layered mixing clock synchronization method is adopted to enable a simulation time and the astronomical time to be in a specified constrained relationship, communication data interaction and processing are achieved, and instantaneity of large-scale and complicated semi-physical simulation systems is guaranteed.
Description
Technical field
The present invention relates to a kind of distributed semi-physical analogue system construction method of real-time high-efficiency, belong to the semi-true object emulation technology field.
Background technology
The computer system simulation technology is to utilize correlation technique to integrated technology reality or that system imagination carries out the dynamic operation experimental study.Computer Simulation has embodied the methodology of experiment thinking in theory, apriority with science, it is particularly complex large system analysis of real system, research, test, assessment, development and skill training provide a kind of advanced person method, those past have effectively been promoted take qualitative analysis as main subject to the quantification future development, and obtain significant benefit in the related application field, especially in military field, design and development for modern weapons, armament systems improve, remodeling and test and for armament systems operator's training, irreplaceable effect is arranged.
Hardware-in-the-loop simulation is a kind of with the emulation in the equipment access emulation loop of reality, adopt hardware-in-the-loop simulation except the development quality that can improve system, also can make the material object that accurately to set up model directly enter the emulation loop, further calibrating mathematical model, the functions of detection system.
Real-time is the basic demand of hardware-in-the-loop simulation.System in kind has the real-time characteristics of physics, and analogue system is a typical polymer grade analogue system, supports different polymerization degree, varigrained emulation, and be adjustable its working time, can be faster than actual physics time, i.e. faster than real time simulation; Also can be slower than actual physics time, i.e. slower-than-real-time simulation.
The time delay of analogue system and equipment in kind all will have influence on the real-time of semi-matter simulating system, and then have influence on accuracy and the credibility of emulation.The real time problems of hardware-in-the-loop simulation mainly comprises the following aspects: the data communication of the time delay that the time series analysis of real-time emulation algorithm, analogue system, hardware cause and compensation, semi-matter simulating system postpones.Wherein about the research of real-time emulation algorithm comparative maturity, it mainly adopts real-time integral algorithm, difference of function value-based algorithm etc. fast; About the time series analysis problem of analogue system, the reasonable distribution artificial tasks is also handled the relation of emulation frame time well, is the problem that simulation technical field need to solve; Time delay and compensation problem about hardware causes are mainly determined by the hardware self performance; And the data communication of semi-matter simulating system delay is to cause in the transmission of data, information process between each semi-matter simulating system member, if process the Real Time Communication Problems between bad each member, this part time delay will be brought to the real-time of hardware-in-the-loop simulation and have a strong impact on.Present semi-matter simulating system mostly is large complicated distributed semi-physical analogue system, therefore, how to guarantee the real-time of system and reduces the key that the data communication processing delay becomes semi-matter simulating system.Therefore, need badly and seek a kind of real-time, efficient semi-matter simulating system construction method, satisfy the requirement of real-time of large complicated half distributing emulation system in kind.
Summary of the invention
The present invention is take the requirement of real-time that guarantees semi-matter simulating system as target, take into account concurrent processing performance and the efficient of hardware-in-the-loop simulation interface, employing is based on the layer-stepping mix clock synchronous method of system layer thought, utilize one process multithread mode and thread pool Design Mode, built a kind of distributed semi-physical analogue system with real-time and efficient characteristics.
Technical scheme of the present invention is as follows:
The construction method of the distributed semi-physical analogue system of a kind of real-time high-efficiency of the present invention, the method concrete steps are as follows:
Step 1, analogue system and hardware-in-the-loop simulation interface are deployed in respectively on different main frames, jointly consist of the distributed semi-physical analogue system with system in kind.
The analogue system that whole system is coupled together by LAN (Local Area Network), hardware-in-the-loop simulation interface system and system in kind form, wherein analogue system can comprise a plurality of simulation subsystems, these simulation subsystems and hardware-in-the-loop simulation interface system is deployed in respectively on different main frames moves.
Interaction between analogue system and system in kind and contact each other data interaction by the hardware-in-the-loop simulation interface system and process (comprise virtual data change to virtual data to True Data conversion and True Data) realization.
Step 2, hardware-in-the-loop simulation interface are set to time control member.
Analogue system, hardware-in-the-loop simulation interface system and system in kind all have autonomy, have the internal time mechanism of this node of control and management operation.The hardware-in-the-loop simulation interface system is set to the time control member of whole semi-matter simulating system, its program adopts the C++ programming language, develop under Windows XP operating system Microsoft Visual C++ environment, realize the clock synchronous management to whole system.
Step 3, hardware-in-the-loop simulation interface serial port of host computer connect gps receiver, serial ports initialization.
Select GPS OEM hardware receiver, hardware-in-the-loop simulation interface system main frame connects gps receiver by serial ports.Hardware-in-the-loop simulation interface system program main thread directly uses the Win32API function to open serial ports, and it is carried out the initiation parameter configuration, and it is asynchronous communication means that serial interface communication mode is set, and baud rate is 9600 bps.Gps receiver switches on power, and makes it in running order.
Step 4, hardware-in-the-loop simulation interface routine main thread are synchronizeed with gps clock.
In running order gps receiver is constantly crossed serial ports to the $ GPRMC information exchange of the NMEA0183 communication standard form that receives and is sent in hardware-in-the-loop simulation interface main frame.In buffer memory, before not dealing with, the raw data in buffer memory is a lot of byte stream to hardware-in-the-loop simulation interface main frame the data placement that receives from serial ports, as: (" $ GPRMC, 020310, V; 0000.0000, N, 00000.0000; W; 000.0,000.0,311005; 007.2, W*62 ").
Hardware-in-the-loop simulation interface mainframe program main thread uses the Win32API function to open serial ports, receive information from serial ports, read the $ GPRMC information that is transmitted by GPS, by using serial ports class Com to extract UTC(world unified time) time is as the logical time of hardware-in-the-loop simulation interface system, and its logical timer is unconditionally advanced with the propelling of phy clock.
Step 5, hardware-in-the-loop simulation interface routine main thread regularly send the synchronizing information bag to analogue system and system in kind.
Hardware-in-the-loop simulation interface routine main thread adopts " giving the correct time " mechanism, every 30ms, the UTC time that extracts is broadcast to each simulation subsystem and system in kind as the standard time by lan interfaces (Ethernet interface 100BaseT).
Step 6, complete each member's clock synchronous of semi-matter simulating system.
The time synchronization information bag that analogue system and system in kind send by the passive reception hardware-in-the-loop simulation of lan interfaces interface, and by PCS (Probabilistic Synchronization Algorithm) probability synchronous method, the logical timer of hardware-in-the-loop simulation interface main frame is estimated.That is: in each synchronizing cycle (30ms), hardware-in-the-loop simulation interface main frame is to the message bag of Web broadcast with own timestamp, analogue system and these message of the passive reception of system host in kind.The network delay of supposing these Network Synchronization message bags is to add up independently, and the average of this stochastic variable and variance are to measure in advance.If a certain destination node is received the message bag of n hardware-in-the-loop simulation interface main frame, analogue system main frame or system host in kind to the clock difference of hardware-in-the-loop simulation interface main frame are:
In formula (1), d is that host node is to the average of the network delay of destination node; T
iThe timestamp of being beaten in i message bag for host node; R
iBe the local zone time of destination node when receiving i message bag.The PCS method reaches given synchronization accuracy γ by the given probability of following formula:
In formula (2), n is the number of the message of the required transmission of synchronizing process; ε is the synchronous error of algorithm; E
dAverage for Internet Transmission; σ
dBe the variance of Network Transmission Delays, Φ () is complementary error function.Calculate synchronous error and failure probability according to formula (1) and (2), adjust accordingly the local logical timer of analogue system and system in kind.
Step 7, hardware-in-the-loop simulation interface routine are completed communication data from thread and are processed.
The hardware-in-the-loop simulation interface routine adopts one process multi-thread design pattern, and in the main thread completion system, the time synchronized management, adopt the thread pool Design Mode from thread, completes data receiver, parsing, response and transmission between analogue system and system in kind.
The hardware-in-the-loop simulation interface routine is with all I/O(of system input and output) access of resource is packaged into unified interface, no longer allows all intercept simultaneously I/O event (data input and output) from thread simultaneously.T allows a thread go to intercept the event of I/O handle at any time, and other threads are in waiting status, claims that the thread of intercepting is the L thread, and the thread of wait is the F thread.The L thread is after listening to the I/O event, and from I/O handle receipt message, then the thread of one side notice wait is taken over the I/O handle, on one side this message of continuation processing.At this moment, L thread has originally been surrendered control, becomes the F thread after handling message.
L thread other F threads when waiting for the I/O event all are in waiting status, and obtain the disposal right of I/O event when the L thread after, the L thread is initiated the promote_new_leader process at once, continues to intercept new I/O event to produce new L thread.At this moment, the L thread just provides a signal, only can take the time seldom, and this thread carries out the new L thread synchronization of the processing fundamental sum of data.The L thread adds thread pool again after handling the I/O event, at this moment, the sequence of the handle of this thread is last, thereby eliminates the sequence expense.
Compared with prior art, innovation of the present invention is:
1. the present invention proposes a kind of construction method of the distributed semi-physical analogue system based on system layer thought, and the analogue system computing function is separated with communication function, saves the analogue system computational resource, reduces the analogue system expense.
2. the present invention adopts layer-stepping mix clock synchronous method, completes clock synchronous to analogue system and actual load system by the hardware-in-the-loop simulation interface, has guaranteed the real-time accuracy of semi-matter simulating system.
3. the present invention adopts one process multi-thread programming pattern to realize that clock synchronous is controlled and data interaction is processed, when guaranteeing that clock synchronous is controlled, utilize the interaction process ability of thread pool programmed method assurance communication data, significantly improve data processing performance and the efficient of hardware-in-the-loop simulation.
Description of drawings
Fig. 1 is the structural drawing of the distributed semi-physical analogue system of real-time high-efficiency of the present invention;
Fig. 2 is the process flow diagram of the distributed semi-physical analogue system construction method of real-time high-efficiency of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
The construction method of the distributed semi-physical analogue system of a kind of real-time high-efficiency of the present invention, flow process realizes by following steps as shown in Figure 2:
Step 1, analogue system and hardware-in-the-loop simulation interface are deployed in respectively on different main frames, jointly consist of the distributed semi-physical analogue system with system in kind.
As shown in Figure 1, the analogue system that whole system is coupled together by LAN (Local Area Network), hardware-in-the-loop simulation interface system and system in kind form, wherein analogue system can comprise a plurality of simulation subsystems, these simulation subsystems and hardware-in-the-loop simulation interface system is deployed in respectively on different main frames moves.
Interaction between analogue system and system in kind and contact each other data interaction by the hardware-in-the-loop simulation interface system and process (comprise virtual data change to virtual data to True Data conversion and True Data) realization.
Step 2, hardware-in-the-loop simulation interface are set to time control member.
Analogue system, hardware-in-the-loop simulation interface system and system in kind all have autonomy, have the internal time mechanism of this node of control and management operation.The hardware-in-the-loop simulation interface system is set to the time control member of whole semi-matter simulating system, its program adopts the C++ programming language, develop under Windows XP operating system Microsoft Visual C++ environment, realize the clock synchronous management to whole system.
Step 3, hardware-in-the-loop simulation interface serial port of host computer connect gps receiver, serial ports initialization.
Select GPS OEM hardware receiver, hardware-in-the-loop simulation interface system main frame connects gps receiver by serial ports.Hardware-in-the-loop simulation interface system program main thread directly uses the Win32API function to open serial ports, and it is carried out the initiation parameter configuration, and it is asynchronous communication means that serial interface communication mode is set, and baud rate is 9600 bps.Gps receiver switches on power, and makes it in running order.
Step 4, hardware-in-the-loop simulation interface routine main thread are synchronizeed with gps clock.
In running order gps receiver is constantly crossed serial ports to the $ GPRMC information exchange of the NMEA0183 communication standard form that receives and is sent in hardware-in-the-loop simulation interface main frame.In buffer memory, before not dealing with, the raw data in buffer memory is a lot of byte stream to hardware-in-the-loop simulation interface main frame the data placement that receives from serial ports, as: (" $ GPRMC, 020310, V; 0000.0000, N, 00000.0000; W; 000.0,000.0,311005; 007.2, W*62 ").
Hardware-in-the-loop simulation interface mainframe program main thread uses the Win32API function to open serial ports, receive information from serial ports, read the $ GPRMC information that is transmitted by GPS, by using serial ports class Com to extract UTC(world unified time) time is as the logical time of hardware-in-the-loop simulation interface system, and its logical timer is unconditionally advanced with the propelling of phy clock.
Step 5, hardware-in-the-loop simulation interface routine main thread regularly send the synchronizing information bag to analogue system and system in kind.
Hardware-in-the-loop simulation interface routine main thread adopts " giving the correct time " mechanism, every 30ms, the UTC time that extracts is broadcast to each simulation subsystem and system in kind as the standard time by lan interfaces (Ethernet interface 100BaseT).
Step 6, complete each member's clock synchronous of semi-matter simulating system.
The time synchronization information bag that analogue system and system in kind send by the passive reception hardware-in-the-loop simulation of lan interfaces interface, and by PCS (Probabilistic Synchronization Algorithm) probability synchronous method, the logical timer of hardware-in-the-loop simulation interface main frame is estimated.That is: in each synchronizing cycle (30ms), hardware-in-the-loop simulation interface main frame is to the message bag of Web broadcast with own timestamp, analogue system and these message of the passive reception of system host in kind.The network delay of supposing these Network Synchronization message bags is to add up independently, and the average of this stochastic variable and variance are to measure in advance.If a certain destination node is received the message bag of n hardware-in-the-loop simulation interface main frame, analogue system main frame or system host in kind to the clock difference of hardware-in-the-loop simulation interface main frame are:
In formula (1), d is that host node is to the average of the network delay of destination node; T
iThe timestamp of being beaten in i message bag for host node; R
iBe the local zone time of destination node when receiving i message bag.The PCS method reaches given synchronization accuracy γ by the given probability of following formula:
In formula (2), n is the number of the message of the required transmission of synchronizing process; ε is the synchronous error of algorithm; E
dAverage for Internet Transmission; σ
dBe the variance of Network Transmission Delays, Φ () is complementary error function.Calculate synchronous error and failure probability according to formula (1) and (2), adjust accordingly the local logical timer of analogue system and system in kind.
Step 7, hardware-in-the-loop simulation interface routine are completed communication data from thread and are processed.
The hardware-in-the-loop simulation interface routine adopts one process multi-thread design pattern, and in the main thread completion system, the time synchronized management, adopt the thread pool Design Mode from thread, completes data receiver, parsing, response and transmission between analogue system and system in kind.
The hardware-in-the-loop simulation interface routine is with all I/O(of system input and output) access of resource is packaged into unified interface, no longer allows all intercept simultaneously I/O event (data input and output) from thread simultaneously.T allows a thread go to intercept the event of I/O handle at any time, and other threads are in waiting status, claims that the thread of intercepting is the L thread, and the thread of wait is the F thread.The L thread is after listening to the I/O event, and from I/O handle receipt message, then the thread of one side notice wait is taken over the I/O handle, on one side this message of continuation processing.At this moment, L thread has originally been surrendered control, becomes the F thread after handling message.
L thread other F threads when waiting for the I/O event all are in waiting status, and obtain the disposal right of I/O event when the L thread after, the L thread is initiated the promote_new_leader process at once, continues to intercept new I/O event to produce new L thread.At this moment, the L thread just provides a signal, only can take the time seldom, and this thread carries out the new L thread synchronization of the processing fundamental sum of data.The L thread adds thread pool again after handling the I/O event, at this moment, the sequence of the handle of this thread is last, thereby eliminates the sequence expense.
Claims (1)
1. the construction method of the distributed semi-physical analogue system of a real-time high-efficiency, it is characterized in that: the method concrete steps are as follows:
Step 1, analogue system and hardware-in-the-loop simulation interface are deployed in respectively on different main frames, jointly consist of the distributed semi-physical analogue system with system in kind; The analogue system that whole system is coupled together by LAN (Local Area Network), hardware-in-the-loop simulation interface system and system in kind form, wherein analogue system comprises a plurality of simulation subsystems, these simulation subsystems and hardware-in-the-loop simulation interface system is deployed in respectively on different main frames moves; Interaction between analogue system and system in kind and contact each other data interaction by the hardware-in-the-loop simulation interface system and process and realize namely comprising that virtual data changes to virtual data to True Data conversion and True Data;
Step 2, hardware-in-the-loop simulation interface are set to time control member;
Analogue system, hardware-in-the-loop simulation interface system and system in kind all have autonomy, have the internal time mechanism of this node of control and management operation; The hardware-in-the-loop simulation interface system is set to the time control member of whole semi-matter simulating system, its program adopts the C++ programming language, develop under Windows XP operating system Microsoft Visual C++ environment, realize the clock synchronous management to whole system;
Step 3, hardware-in-the-loop simulation interface serial port of host computer connect gps receiver, serial ports initialization;
Select GPS OEM hardware receiver, hardware-in-the-loop simulation interface system main frame connects gps receiver by serial ports, hardware-in-the-loop simulation interface system program main thread directly uses the Win32API function to open serial ports, it is carried out the initiation parameter configuration, it is asynchronous communication means that serial interface communication mode is set, baud rate is 9600 bps, and gps receiver switches on power, and makes it in running order;
Step 4, hardware-in-the-loop simulation interface routine main thread are synchronizeed with gps clock;
In running order gps receiver is constantly crossed serial ports to the $ GPRMC information exchange of the NMEA0183 communication standard form that receives and is sent in hardware-in-the-loop simulation interface main frame, hardware-in-the-loop simulation interface main frame the data placement that receives from serial ports in buffer memory, before not dealing with, raw data in buffer memory is a lot of byte stream, as: " $ GPRMC, 020310; V, 0000.0000, N; 00000.0000, W, 000.0; 000.0; 311005,007.2, W*62 ";
Hardware-in-the-loop simulation interface mainframe program main thread uses the Win32API function to open serial ports, receive information from serial ports, read the $ GPRMC information that is transmitted by GPS, by use serial ports class Com extract the UTC time be world unified time as the logical time of hardware-in-the-loop simulation interface system, its logical timer is unconditionally advanced with the propelling of phy clock;
Step 5, hardware-in-the-loop simulation interface routine main thread regularly send the synchronizing information bag to analogue system and system in kind;
Hardware-in-the-loop simulation interface routine main thread adopts " giving the correct time " mechanism, is that Ethernet interface 100BaseT be broadcast to each simulation subsystem and in kind system as the standard time by lan interfaces with the UTC time that extracts every 30ms;
Step 6, complete each member's clock synchronous of semi-matter simulating system;
The time synchronization information bag that analogue system and system in kind send by the passive reception hardware-in-the-loop simulation of lan interfaces interface, and be that Probabilistic Synchronization Algorithm probability synchronous method is estimated the logical timer of hardware-in-the-loop simulation interface main frame by PCS; That is: in each 30ms, hardware-in-the-loop simulation interface main frame is to the message bag of Web broadcast with own timestamp synchronizing cycle, analogue system and these message of the passive reception of system host in kind; The network delay of supposing these Network Synchronization message bags is to add up independently, and the average of this stochastic variable and variance are to measure in advance; If a certain destination node is received the message bag of n hardware-in-the-loop simulation interface main frame, analogue system main frame or system host in kind to the clock difference of hardware-in-the-loop simulation interface main frame are:
In formula (1), d is that host node is to the average of the network delay of destination node; T
iThe timestamp of being beaten in i message bag for host node; R
iBe the local zone time of destination node when receiving i message bag; The PCS method reaches given synchronization accuracy γ by the given probability of following formula:
In formula (2), n is the number of the message of the required transmission of synchronizing process; ε is the synchronous error of algorithm; E
dAverage for Internet Transmission; σ
dBe the variance of Network Transmission Delays, Φ () is complementary error function, calculates synchronous error and failure probability according to formula (1) and (2), adjusts accordingly the local logical timer of analogue system and system in kind;
Step 7, hardware-in-the-loop simulation interface routine are completed communication data from thread and are processed;
The hardware-in-the-loop simulation interface routine adopts one process multi-thread design pattern, and in the main thread completion system, the time synchronized management, adopt the thread pool Design Mode from thread, completes data receiver, parsing, response and transmission between analogue system and system in kind;
The access that the hardware-in-the-loop simulation interface routine is the input and output resource with all I/O of system is packaged into unified interface, and no longer allowing all intercept simultaneously the I/O event from thread simultaneously is the data input and output; T allows a thread go to intercept the event of I/O handle at any time, and other threads are in waiting status, claims that the thread of intercepting is the L thread, and the thread of wait is the F thread; The L thread is after listening to the I/O event, and from I/O handle receipt message, then the thread of notice wait is on one side taken over the I/O handle, continue to process this message on one side, at this moment, L thread has originally been surrendered control, becomes the F thread after handling message;
L thread other F threads when waiting for the I/O event all are in waiting status, and obtain the disposal right of I/O event when the L thread after, the L thread is initiated the promote_new_leader process at once, continues to intercept new I/O event to produce new L thread; At this moment, the L thread just provides a signal, only can take the time seldom, and this thread carries out the new L thread synchronization of the processing fundamental sum of data; The L thread adds thread pool again after handling the I/O event, at this moment, the sequence of the handle of this thread is last, thereby eliminates the sequence expense.
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