CN103093059B - A kind of distributed semi-physical simulation system construction method of real-time high-efficiency - Google Patents
A kind of distributed semi-physical simulation system construction method of real-time high-efficiency Download PDFInfo
- Publication number
- CN103093059B CN103093059B CN201310046765.4A CN201310046765A CN103093059B CN 103093059 B CN103093059 B CN 103093059B CN 201310046765 A CN201310046765 A CN 201310046765A CN 103093059 B CN103093059 B CN 103093059B
- Authority
- CN
- China
- Prior art keywords
- hardware
- thread
- loop simulation
- simulation interface
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
A construction method for the distributed semi-physical analogue system of real-time high-efficiency, it has seven large steps: one, be deployed on different main frame respectively by analogue system and hardware-in-the-loop simulation interface, jointly form distributed semi-physical analogue system with prototype system; Two, hardware-in-the-loop simulation interface is set to time controling member; Three, hardware-in-the-loop simulation Interface Host serial ports connects gps receiver, serial ports initialization; Four, hardware-in-the-loop simulation interface routine main thread is synchronous with gps clock; Five, hardware-in-the-loop simulation interface routine main thread regularly sends synchronizing information bag to analogue system and prototype system; Six, each member's clock synchronous of semi-matter simulating system is completed; Seven, hardware-in-the-loop simulation interface routine completes communication data process from thread.Present invention saves computational resource and system overhead, adopt layer-stepping mix clock synchronous method, make simulation time and astronomical time meet the restriction relation of regulation; Realize the mutual and process of communication data, ensure the real-time of large complicated semi-matter simulating system.
Description
Technical field
The present invention relates to a kind of distributed semi-physical simulation system construction method of real-time high-efficiency, belong to semi-true object emulation technology field.
Background technology
Computer system simulation technology utilizes the system of correlation technique to reality or imagination to carry out an integrated technology of dynamic operation experimental study.Computer Simulation embodies the methodology of experiment thinking in theory, there is the apriority of science, it is real system particularly complex large system analysis, research, test, assessment, development and skill training provide a kind of method of advanced person, effectively promote the subject of those past based on qualitative analysis to quantification future development, and obtain significant benefit in related application field, especially in military field, for the design and evaluation of modern weapons, armament systems improve, remodeling and test and training for armament systems operator, there is irreplaceable effect.
Hardware-in-the-loop simulation is a kind of by the emulation in the equipment access of reality emulation loop, adopt hardware-in-the-loop simulation except can improving the development quality of system, also can make the material object of accurate Modling model cannot directly enter emulation loop, further calibrating mathematical model, the functions of detection system.
Real-time is the basic demand of hardware-in-the-loop simulation.Prototype system has the real-time feature of physics, and analogue system is a typical constructive simulation system, and support different polymerization degree, varigrained emulation, its working time is adjustable, can faster than actual physics time, i.e. faster than real time simulation; Also the actual physics time can be slower than, i.e. slower-than-real-time simulation.
The time delay of analogue system and equipment in kind all will have influence on the real-time of semi-matter simulating system, and then have influence on accuracy and the credibility of emulation.The real time problems of hardware-in-the-loop simulation mainly comprises the following aspects: the data communication delays of the time delay that the time series analysis of real-time emulation algorithm, analogue system, hardware cause and compensation, semi-matter simulating system.Wherein about the research comparative maturity of real-time emulation algorithm, it mainly adopts real-time integral algorithm, fast function difference algorithm etc.; About the timing analysis problems of analogue system, reasonable distribution artificial tasks also handles the relation of emulation frame time well, is the problem that simulation technical field needs to solve; The time delay caused about hardware and compensation problem, determine primarily of hardware self performance; And the data communication delays of semi-matter simulating system transmits between each semi-matter simulating system member in data, information process to cause, if process the Real Time Communication Problems between bad each member, this part time delay has a strong impact on bringing to the real-time of hardware-in-the-loop simulation.Present semi-matter simulating system mostly is large complicated distributed semi-physical analogue system, therefore, how to ensure the real-time of system and reduces the key that data communication processing delay becomes semi-matter simulating system.Therefore, need badly and find a kind of in real time, efficient semi-matter simulating system construction method, meet the requirement of real-time of large complicated half distributing emulation system in kind.
Summary of the invention
The present invention is to ensure that the requirement of real-time of semi-matter simulating system is for target, take into account concurrent processing performance and the efficiency of hardware-in-the-loop simulation interface, adopt the layer-stepping mix clock synchronous method based on system layer thought, utilize one process multithread mode and thread pool Design Mode, construct a kind of distributed semi-physical analogue system with real-time and efficient feature.
Technical scheme of the present invention is as follows:
The construction method of the distributed semi-physical analogue system of a kind of real-time high-efficiency of the present invention, the method concrete steps are as follows:
Step one, analogue system and hardware-in-the-loop simulation interface are deployed on different main frame respectively, jointly form distributed semi-physical analogue system with prototype system.
The analogue system that whole system is coupled together by LAN (Local Area Network), hardware-in-the-loop simulation interface system and prototype system form, wherein analogue system can comprise multiple simulation subsystem, these simulation subsystems and hardware-in-the-loop simulation interface system is deployed in respectively on different main frame and runs.
Interaction between analogue system and prototype system and communication with one another are realized by the data interaction process (comprising virtual data to change to True Data conversion and True Data to virtual data) of hardware-in-the-loop simulation interface system.
Step 2, hardware-in-the-loop simulation interface are set to time controling member.
Analogue system, hardware-in-the-loop simulation interface system and prototype system all have autonomy, have the internal time mechanism that this node of control and management runs.Hardware-in-the-loop simulation interface system is set to the time controling member of whole semi-matter simulating system, its program adopts C++ programming language, develop under Windows XP operating system Microsoft Visual C++ environment, realize managing the clock synchronous of whole system.
Step 3, hardware-in-the-loop simulation Interface Host serial ports connect gps receiver, serial ports initialization.
Select GPS OEM hardware receiver, hardware-in-the-loop simulation interface system main frame connects gps receiver by serial ports.Hardware-in-the-loop simulation interface system program main thread directly uses Win32API function to open serial ports, carries out initiation parameter configuration to it, and arranging serial interface communication mode is asynchronous communication means, and baud rate is 9600 bps.Gps receiver switches on power, and makes it in running order.
Step 4, hardware-in-the-loop simulation interface routine main thread are synchronous with gps clock.
In running order gps receiver is constantly sent to the $ GPRMC information of the NMEA0183 communication standard format received in hardware-in-the-loop simulation Interface Host by serial ports.Hardware-in-the-loop simulation Interface Host is the data placement received from serial ports in buffer memory, and before not dealing with, the raw data in buffer memory is a lot of byte stream, as: (" $ GPRMC, 020310, V; 0000.0000, N, 00000.0000; W; 000.0,000.0,311005; 007.2, W*62 ").
Hardware-in-the-loop simulation Interface Host program main thread uses Win32API function to open serial ports, information is received from serial ports, read the $ GPRMC information transmitted by GPS, extract UTC(world unified time by using serial ports class Com) time as the logical time of hardware-in-the-loop simulation interface system, its logical timer is unconditionally advanced with the propelling of phy clock.
Step 5, hardware-in-the-loop simulation interface routine main thread regularly send synchronizing information bag to analogue system and prototype system.
Hardware-in-the-loop simulation interface routine main thread adopts " giving the correct time " mechanism, every 30ms, UTC time as the standard time extracted is broadcast to each simulation subsystem and prototype system by lan interfaces (Ethernet interface 100BaseT).
Step 6, complete each member's clock synchronous of semi-matter simulating system.
The time synchronization information bag that analogue system and prototype system are sent by lan interfaces passive reception hardware-in-the-loop simulation interface, and estimated by PCS (the Probabilistic Synchronization Algorithm) logical timer of probability synchronous method to hardware-in-the-loop simulation Interface Host.That is: in each synchronizing cycle (30ms), hardware-in-the-loop simulation Interface Host is to message bag, analogue system and these message of the passive reception of prototype system main frame with oneself timestamp of Web broadcast.Assuming that the network delay of these Network Synchronization message bags is statistical iteration, and the average of this stochastic variable and variance measure in advance.If a certain destination node receives the message bag of n hardware-in-the-loop simulation Interface Host, then analogue system main frame or prototype system main frame to the clock difference of hardware-in-the-loop simulation Interface Host are:
In formula (1), d is the average of host node to the network delay of destination node; T
ifor host node in i-th message bag the timestamp beaten; R
ifor the local zone time of destination node when receiving i-th message bag.PCS method reaches given synchronization accuracy γ by the probability given by following formula:
In formula (2), n is the number of the required message transmitted of synchronizing process; ε is the synchronous error of algorithm; E
dfor the average of Internet Transmission; σ
dfor the variance of Network Transmission Delays, Φ () is complementary error function.Calculate synchronous error and failure probability according to formula (1) and (2), adjust the local logical timer of analogue system and prototype system accordingly.
Step 7, hardware-in-the-loop simulation interface routine complete communication data process from thread.
Hardware-in-the-loop simulation interface routine adopts one process multi-thread design pattern, and in main thread completion system, time synchronized management, adopts thread pool Design Mode from thread, complete the data receiver between analogue system and prototype system, parsing, response and transmission.
Hardware-in-the-loop simulation interface routine is by all system I/O(input and output) access of resource is packaged into unified interface, no longer allows allly intercept I/O event (data input and output) from thread simultaneously simultaneously.T allows a thread go to intercept the event of I/O handle at any time, and other threads are in waiting status, and claim the thread of intercepting to be L thread, the thread of wait is F thread.L thread is after listening to I/O event, and from I/O handle receipt message, the thread adapter I/O handle of then notice wait, while continue this message of process.Now, L thread has originally surrendered control, becomes F thread after processing message.
L thread other F threads when waiting for I/O event are all in waiting status, and after L thread obtains the disposal right of I/O event, L thread initiates promote_new_leader process at once, continues to intercept new I/O event to produce new L thread.Now, L thread just provides a signal, and only can take little time, the L thread synchronization that the process fundamental sum of this thread to data is new is carried out.L thread rejoins thread pool after processing I/O event, and now, the handle sequence of this thread is last, thus eliminates sequence expense.
Compared with prior art, innovation of the present invention is:
1. the present invention proposes a kind of construction method of the distributed semi-physical analogue system based on system layer thought, analogue system computing function is separated with communication function, saves analogue system computational resource, reduces analogue system expense.
2. the present invention adopts layer-stepping mix clock synchronous method, completes the clock synchronous to analogue system and actual load system, ensure that the real-time accuracy of semi-matter simulating system by hardware-in-the-loop simulation interface.
3. the present invention adopts one process multi-thread programming pattern to realize clock synchronous control and data interaction process, while guarantee clock synchronous controls, utilize thread pool programmed method to ensure the interaction process ability of communication data, significantly improve data processing performance and the efficiency of hardware-in-the-loop simulation.
Accompanying drawing explanation
Fig. 1 is the structural drawing of the distributed semi-physical analogue system of real-time high-efficiency of the present invention;
Fig. 2 is the process flow diagram of the distributed semi-physical simulation system construction method of real-time high-efficiency of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The construction method of the distributed semi-physical analogue system of a kind of real-time high-efficiency of the present invention, flow process as shown in Figure 2, is realized by following steps:
Step one, analogue system and hardware-in-the-loop simulation interface are deployed on different main frame respectively, jointly form distributed semi-physical analogue system with prototype system.
As shown in Figure 1, the analogue system that whole system is coupled together by LAN (Local Area Network), hardware-in-the-loop simulation interface system and prototype system form, wherein analogue system can comprise multiple simulation subsystem, these simulation subsystems and hardware-in-the-loop simulation interface system is deployed in respectively on different main frame and runs.
Interaction between analogue system and prototype system and communication with one another are realized by the data interaction process (comprising virtual data to change to True Data conversion and True Data to virtual data) of hardware-in-the-loop simulation interface system.
Step 2, hardware-in-the-loop simulation interface are set to time controling member.
Analogue system, hardware-in-the-loop simulation interface system and prototype system all have autonomy, have the internal time mechanism that this node of control and management runs.Hardware-in-the-loop simulation interface system is set to the time controling member of whole semi-matter simulating system, its program adopts C++ programming language, develop under Windows XP operating system Microsoft Visual C++ environment, realize managing the clock synchronous of whole system.
Step 3, hardware-in-the-loop simulation Interface Host serial ports connect gps receiver, serial ports initialization.
Select GPS OEM hardware receiver, hardware-in-the-loop simulation interface system main frame connects gps receiver by serial ports.Hardware-in-the-loop simulation interface system program main thread directly uses Win32API function to open serial ports, carries out initiation parameter configuration to it, and arranging serial interface communication mode is asynchronous communication means, and baud rate is 9600 bps.Gps receiver switches on power, and makes it in running order.
Step 4, hardware-in-the-loop simulation interface routine main thread are synchronous with gps clock.
In running order gps receiver is constantly sent to the $ GPRMC information of the NMEA0183 communication standard format received in hardware-in-the-loop simulation Interface Host by serial ports.Hardware-in-the-loop simulation Interface Host is the data placement received from serial ports in buffer memory, and before not dealing with, the raw data in buffer memory is a lot of byte stream, as: (" $ GPRMC, 020310, V; 0000.0000, N, 00000.0000; W; 000.0,000.0,311005; 007.2, W*62 ").
Hardware-in-the-loop simulation Interface Host program main thread uses Win32API function to open serial ports, information is received from serial ports, read the $ GPRMC information transmitted by GPS, extract UTC(world unified time by using serial ports class Com) time as the logical time of hardware-in-the-loop simulation interface system, its logical timer is unconditionally advanced with the propelling of phy clock.
Step 5, hardware-in-the-loop simulation interface routine main thread regularly send synchronizing information bag to analogue system and prototype system.
Hardware-in-the-loop simulation interface routine main thread adopts " giving the correct time " mechanism, every 30ms, UTC time as the standard time extracted is broadcast to each simulation subsystem and prototype system by lan interfaces (Ethernet interface 100BaseT).
Step 6, complete each member's clock synchronous of semi-matter simulating system.
The time synchronization information bag that analogue system and prototype system are sent by lan interfaces passive reception hardware-in-the-loop simulation interface, and estimated by PCS (the Probabilistic Synchronization Algorithm) logical timer of probability synchronous method to hardware-in-the-loop simulation Interface Host.That is: in each synchronizing cycle (30ms), hardware-in-the-loop simulation Interface Host is to message bag, analogue system and these message of the passive reception of prototype system main frame with oneself timestamp of Web broadcast.Assuming that the network delay of these Network Synchronization message bags is statistical iteration, and the average of this stochastic variable and variance measure in advance.If a certain destination node receives the message bag of n hardware-in-the-loop simulation Interface Host, then analogue system main frame or prototype system main frame to the clock difference of hardware-in-the-loop simulation Interface Host are:
In formula (1), d is the average of host node to the network delay of destination node; T
ifor host node in i-th message bag the timestamp beaten; R
ifor the local zone time of destination node when receiving i-th message bag.PCS method reaches given synchronization accuracy γ by the probability given by following formula:
In formula (2), n is the number of the required message transmitted of synchronizing process; ε is the synchronous error of algorithm; E
dfor the average of Internet Transmission; σ
dfor the variance of Network Transmission Delays, Φ () is complementary error function.Calculate synchronous error and failure probability according to formula (1) and (2), adjust the local logical timer of analogue system and prototype system accordingly.
Step 7, hardware-in-the-loop simulation interface routine complete communication data process from thread.
Hardware-in-the-loop simulation interface routine adopts one process multi-thread design pattern, and in main thread completion system, time synchronized management, adopts thread pool Design Mode from thread, complete the data receiver between analogue system and prototype system, parsing, response and transmission.
Hardware-in-the-loop simulation interface routine is by all system I/O(input and output) access of resource is packaged into unified interface, no longer allows allly intercept I/O event (data input and output) from thread simultaneously simultaneously.T allows a thread go to intercept the event of I/O handle at any time, and other threads are in waiting status, and claim the thread of intercepting to be L thread, the thread of wait is F thread.L thread is after listening to I/O event, and from I/O handle receipt message, the thread adapter I/O handle of then notice wait, while continue this message of process.Now, L thread has originally surrendered control, becomes F thread after processing message.
L thread other F threads when waiting for I/O event are all in waiting status, and after L thread obtains the disposal right of I/O event, L thread initiates promote_new_leader process at once, continues to intercept new I/O event to produce new L thread.Now, L thread just provides a signal, and only can take little time, the L thread synchronization that the process fundamental sum of this thread to data is new is carried out.L thread rejoins thread pool after processing I/O event, and now, the handle sequence of this thread is last, thus eliminates sequence expense.
Claims (1)
1. a construction method for the distributed semi-physical analogue system of real-time high-efficiency, is characterized in that: the method concrete steps are as follows:
Step one, analogue system and hardware-in-the-loop simulation interface are deployed on different main frame respectively, jointly form distributed semi-physical analogue system with prototype system; The analogue system that whole system is coupled together by LAN (Local Area Network), hardware-in-the-loop simulation interface system and prototype system form, wherein analogue system comprises multiple simulation subsystem, these simulation subsystems and hardware-in-the-loop simulation interface system is deployed in respectively on different main frame and runs; Interaction between analogue system and prototype system and communication with one another realize namely comprising virtual data by the data interaction process of hardware-in-the-loop simulation interface system and change to virtual data to True Data conversion and True Data;
Step 2, hardware-in-the-loop simulation interface are set to time controling member;
Analogue system, hardware-in-the-loop simulation interface system and prototype system all have autonomy, have the internal time mechanism that this node of control and management runs; Hardware-in-the-loop simulation interface system is set to the time controling member of whole semi-matter simulating system, its program adopts C++ programming language, develop under Windows XP operating system Microsoft Visual C++ environment, realize managing the clock synchronous of whole system;
Step 3, hardware-in-the-loop simulation Interface Host serial ports connect gps receiver, serial ports initialization;
Select GPS OEM hardware receiver, hardware-in-the-loop simulation interface system main frame connects gps receiver by serial ports, hardware-in-the-loop simulation interface system program main thread directly uses Win32API function to open serial ports, initiation parameter configuration is carried out to it, arranging serial interface communication mode is asynchronous communication means, baud rate is 9600 bps, and gps receiver switches on power, and makes it in running order;
Step 4, hardware-in-the-loop simulation interface routine main thread are synchronous with gps clock;
In running order gps receiver is constantly sent to the $ GPRMC information of NMEA 0183 communication standard format received in hardware-in-the-loop simulation Interface Host by serial ports, hardware-in-the-loop simulation Interface Host the data placement received from serial ports in buffer memory, before not dealing with, the raw data in buffer memory is a lot of byte stream;
Hardware-in-the-loop simulation Interface Host program main thread uses Win32API function to open serial ports, information is received from serial ports, read the $ GPRMC information transmitted by GPS, by using serial ports class Com to extract UTC time and world unified time as the logical time of hardware-in-the-loop simulation interface system, its logical timer is unconditionally advanced with the propelling of phy clock;
Step 5, hardware-in-the-loop simulation interface routine main thread regularly send synchronizing information bag to analogue system and prototype system;
Hardware-in-the-loop simulation interface routine main thread adopts " giving the correct time " mechanism, every 30ms, UTC time as the standard time extracted is broadcast to each simulation subsystem and prototype system by lan interfaces and Ethernet interface 100BaseT;
Step 6, complete each member's clock synchronous of semi-matter simulating system;
The time synchronization information bag that analogue system and prototype system are sent by lan interfaces passive reception hardware-in-the-loop simulation interface, and estimated by the logical timer of the probability synchronous method of PCS and Probabilistic Synchronization Algorithm to hardware-in-the-loop simulation Interface Host; That is: in each synchronizing cycle 30ms, hardware-in-the-loop simulation Interface Host to the message bag of Web broadcast with oneself timestamp, analogue system and these message of the passive reception of prototype system main frame; Assuming that the network delay of these Network Synchronization message bags is statistical iteration, and the average of the network delay of these Network Synchronization message bags and variance measure in advance; If a certain destination node receives the message bag of n hardware-in-the-loop simulation Interface Host, then analogue system main frame or prototype system main frame to the clock difference of hardware-in-the-loop simulation Interface Host are:
In formula (1), d is the average of host node to the network delay of destination node; T
ifor host node in i-th message bag the timestamp beaten; R
ifor the local zone time of destination node when receiving i-th message bag; PCS method reaches given synchronization accuracy γ by the probability given by following formula:
In formula (2), n is the number of the required message transmitted of synchronizing process; ε is the synchronous error of algorithm; E
dfor the average of Internet Transmission; σ
dfor the variance of Network Transmission Delays, Φ (〃) is complementary error function, calculates synchronous error and failure probability, adjust the local logical timer of analogue system and prototype system accordingly according to formula (1) and (2);
Step 7, hardware-in-the-loop simulation interface routine complete communication data process from thread;
Hardware-in-the-loop simulation interface routine adopts one process multi-thread design pattern, and in main thread completion system, time synchronized management, adopts thread pool Design Mode from thread, complete the data receiver between analogue system and prototype system, parsing, response and transmission;
The access of all system I/O and input and output resource is packaged into unified interface by hardware-in-the-loop simulation interface routine, no longer allows allly intercept I/O event and data input and output from thread simultaneously simultaneously; T allows a thread go to intercept the event of I/O handle at any time, and other threads are in waiting status, and claim the thread of intercepting to be L thread, the thread of wait is F thread; L thread, after listening to I/O event, from I/O handle receipt message, then notifies the thread adapter I/O handle waited for, while continue this message of process, now, L thread has originally surrendered control, becomes F thread after processing message;
L thread other F threads when waiting for I/O event are all in waiting status, and after L thread obtains the disposal right of I/O event, L thread initiates promote_new_leader process at once, continues to intercept new I/O event to produce new L thread; Now, L thread just provides a signal, and only can take little time, the L thread synchronization that the process fundamental sum of this thread to data is new is carried out; L thread rejoins thread pool after processing I/O event, and now, the handle sequence of this thread is last, thus eliminates sequence expense.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310046765.4A CN103093059B (en) | 2013-02-05 | 2013-02-05 | A kind of distributed semi-physical simulation system construction method of real-time high-efficiency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310046765.4A CN103093059B (en) | 2013-02-05 | 2013-02-05 | A kind of distributed semi-physical simulation system construction method of real-time high-efficiency |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103093059A CN103093059A (en) | 2013-05-08 |
| CN103093059B true CN103093059B (en) | 2015-08-05 |
Family
ID=48205619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310046765.4A Expired - Fee Related CN103093059B (en) | 2013-02-05 | 2013-02-05 | A kind of distributed semi-physical simulation system construction method of real-time high-efficiency |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103093059B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106197413B (en) * | 2016-07-08 | 2018-04-06 | 北京航空航天大学 | A kind of airborne distributed location attitude measurement system |
| CN109086532A (en) * | 2018-08-09 | 2018-12-25 | 广东工业大学 | A kind of tiered warehouse facility HWIL simulation modeling method based on OOPN pessimistic concurrency control |
| CN109143894A (en) * | 2018-09-28 | 2019-01-04 | 中冶赛迪技术研究中心有限公司 | A kind of semi-matter simulating system and method based on Open Source Framework |
| CN111123883B (en) * | 2018-10-30 | 2023-03-31 | 阿波罗智能技术(北京)有限公司 | Dual-drive unmanned vehicle simulation method, device, equipment and computer readable medium |
| CN109981206B (en) * | 2019-02-26 | 2021-01-26 | 深圳猛犸电动科技有限公司 | Time synchronization method, device, system, terminal equipment and storage medium |
| CN109948213A (en) * | 2019-03-11 | 2019-06-28 | 北京世冠金洋科技发展有限公司 | A kind of synergy emulation method and device based on FMI standard |
| CN111338427B (en) * | 2020-02-27 | 2021-06-15 | 深圳航天科技创新研究院 | Method for realizing SystemC semi-physical simulation time synchronization |
| CN111324046B (en) * | 2020-02-28 | 2022-10-25 | 中国电力科学研究院有限公司 | Method and system for performing cooperative operation on distributed simulation system |
| CN113110111B (en) * | 2021-05-10 | 2023-02-17 | 电子科技大学长三角研究院(衢州) | Distributed semi-physical simulation system based on NS3 |
| CN113360395A (en) * | 2021-06-24 | 2021-09-07 | 中国电子科技集团公司第十四研究所 | Real-time interactive management technology for simulation system |
| CN117057171B (en) * | 2023-10-12 | 2024-02-06 | 中国电子科技集团公司第十研究所 | Semi-packaging simulation method combining measured data and simulation data |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102096376A (en) * | 2010-12-30 | 2011-06-15 | 中国科学院长春光学精密机械与物理研究所 | Mixed time sequence synchronous control method in physical simulation |
| CN102298334A (en) * | 2011-08-31 | 2011-12-28 | 北京空间飞行器总体设计部 | Breakpoint simulation controller and control method for ground simulation system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080091403A1 (en) * | 2006-10-16 | 2008-04-17 | Harrison Gregory A | Large Training System Simulation Using Dynamic Network Entities |
-
2013
- 2013-02-05 CN CN201310046765.4A patent/CN103093059B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102096376A (en) * | 2010-12-30 | 2011-06-15 | 中国科学院长春光学精密机械与物理研究所 | Mixed time sequence synchronous control method in physical simulation |
| CN102298334A (en) * | 2011-08-31 | 2011-12-28 | 北京空间飞行器总体设计部 | Breakpoint simulation controller and control method for ground simulation system |
Non-Patent Citations (4)
| Title |
|---|
| "一种基于虚拟现实技术的分布式半实物仿真平台研究和实现";王绍棣等;《系统仿真学报》;20010531;第13卷(第3期);第381-384页 * |
| "分布式仿真系统实时性实现技术研究";石岩等;《无线电工程》;20091231;第39卷(第8期);第11-13、16页 * |
| "制导控制半实物仿真系统设计";陈伯翰等;《航空计算技术》;20100131;第40卷(第1期);第119-122页 * |
| "高精度GPS观测数据的实时仿真研究";范国清等;《国防科技大学学报》;20091231;第31卷(第3期);第60-64页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103093059A (en) | 2013-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103093059B (en) | A kind of distributed semi-physical simulation system construction method of real-time high-efficiency | |
| US10908941B2 (en) | Timestamping data received by monitoring system in NFV | |
| Pellizzoni et al. | Worst case delay analysis for memory interference in multicore systems | |
| CN106844822B (en) | Carrier rocket semi-physical simulation method supporting rapid virtual-real interchange | |
| CN105930580B (en) | Time synchronization and data exchange device and method for joint simulation of power system and information communication system | |
| CN103281772B (en) | A kind of method for synchronizing time of wireless sensor network and system | |
| Lauer et al. | Latency and freshness analysis on IMA systems | |
| Mandal et al. | Analytical performance models for NoCs with multiple priority traffic classes | |
| Shrivastava et al. | Time in cyber-physical systems | |
| CN113747563A (en) | Synchronous acquisition method and device for power internet of things sensors | |
| Domínguez et al. | Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm | |
| CN106227641A (en) | A kind of hardware performance monitoring method and system | |
| CN107220107B (en) | Multi-clock multi-task parallel real-time simulation system and method | |
| Steiner et al. | The TTEthernet synchronisation protocols and their formal verification | |
| Lamps et al. | Conjoining emulation and network simulators on linux multiprocessors | |
| JP4961589B2 (en) | Network system and slave synchronization method | |
| Srinivasan et al. | An analysis of the delayed gradients problem in asynchronous sgd | |
| Chen et al. | High-precision time synchronization chip design for industrial sensor and actuator network | |
| Bogomolov et al. | Benchmark for verification of fault-tolerant clock synchronization algorithms | |
| Li et al. | Modeling ttethernet startup service in systemc for verifying fault-tolerant protocol under fail-omission scenarios | |
| CN101873338A (en) | Event synchronizing method for parallel simulation and simulators | |
| D'Souza et al. | Quartzv: Bringing quality of time to virtual machines | |
| KR20200070972A (en) | Method for controlling time information based serial communication and apparatus for the same | |
| Addad et al. | Delay evaluation and compensation in ethernet-networked control systems | |
| Palizban et al. | Multi-simulation environment for smart grid: Co-simulation approach |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150805 Termination date: 20170205 |