CN107220107B - Multi-clock multi-task parallel real-time simulation system and method - Google Patents
Multi-clock multi-task parallel real-time simulation system and method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45591—Monitoring or debugging support
Abstract
The invention discloses a multi-clock multi-task parallel real-time simulation system and a method, wherein the system comprises: the clock domain control module is used for acquiring a plurality of pulse clock sources and outputting a plurality of clock excitation information to the simulation control module; the simulation control module is used for distributing and controlling clock excitation information through a clock scheduling mechanism, sending clock scheduling driving signals to a plurality of simulation tasks and monitoring data of the simulation tasks in real time; the hardware interface mapping module is used for describing the operation of the hardware interface in the form of a simulation task language; and the simulation task module is used for performing independent operation under the driving of the clock scheduling driving signal of the simulation control module and completing corresponding hardware interface operation through the hardware interface mapping module. The simulation system of the invention can form the homologous clock drive and the heterogeneous clock drive according to the multi-task application requirement, thereby meeting the parallel simulation requirement of multi-clock and multi-task.
Description
Technical Field
The invention belongs to the technical field of real-time simulation of engineering systems, relates to a real-time simulation system, and particularly relates to a multi-clock multi-task parallel real-time simulation system and method.
Background
The real-time simulation system is the key for realizing algorithm simulation, modeling a controlled object and finishing closed-loop simulation of the control system by the control technology. The method requires that the time proportion of the simulation task is consistent with that of a real system, so that dynamic input can be stably received and dynamic output can be stably sent in real time, and the real-time simulation system can be accessed to a physical system, so that errors caused by complex system modeling are avoided, and the real-time performance of simulation is further ensured, so that the method is widely applied to analysis, research and design of a control system.
With the increasing complexity of controlled objects in control systems, the difficulty of multi-task simulation is increasing. The more nodes in the simulation environment, the larger the scale, the more simulation tasks are needed, and the direct heterogeneity difference of each simulation task is larger and larger. The method mainly shows that the requirements of the tasks in different periods are gradually increased on the basis of the tasks in the same period in the multi-task simulation, and the requirements of the clocks in different periods are also gradually increased on the basis of the clocks in the same source in the multi-task simulation. The traditional simulator has the control of clock management focused on solving the multi-task requirements of the same source and the same period, and cannot solve the multi-clock and multi-task simulation requirements of the same source and different periods and the multi-clock and multi-task simulation requirements of heterogeneous clocks.
In multi-task simulation, a large number of simulation tasks are established, and interfaces and scheduling mechanisms of the simulation tasks are not effectively and properly managed, so that the execution efficiency of a simulation engine and the development efficiency of the simulation tasks are influenced. In the traditional simulation machine, system scheduling, clock management and execution of simulation tasks are often mixed, so that the development work is not clear and transparent, the transplantation and maintenance of the simulation tasks are not facilitated, and the design dependence of the simulation tasks on a specific simulation system and the design dependence of the simulation tasks on a specific clock source cannot be separated.
With the growing maturity of distributed application environments, bus communication technology has gained more attention and application, and a bus can be a channel for data exchange of each simulation task and simulation node. The clock scheduling of each simulation task is completed through the bus, the existing clock resources can be saved, the bus data drive can be utilized, the design of the simulation tasks is optimized, the traditional simulator cannot acquire the bus data drive in the data bus to serve as the simulation clock, and therefore the limitation of the traditional simulator to distributed application is greatly increased.
With the rapid development of the control system industry and the development of the simulation task, the design requirements of rapid design, rapid simulation and rapid verification can be met. This means that there is a higher utilization of the need for emulated device resources. The traditional simulation equipment can only provide the support of hardware resources and system resources for one group of simulation tasks, and the reuse of the simulation system equipment cannot be realized.
The invention patent with the Chinese grant publication number of CN102929158B discloses a multi-core multi-model parallel distributed real-time simulation system, which describes a method for providing task scheduling, and completes the simulation function of multi-model on a multi-core processor, but can not simulate multi-clock application.
The invention patent with the Chinese granted publication number of CN103136032B discloses a multi-core system parallel simulation system, which describes that a simulation model aiming at a specific hardware environment is built quickly, so that the verification of a multi-core system static scheduling algorithm is accelerated, but simulation support is not provided for multi-task application and multi-clock application.
Disclosure of Invention
The invention aims to provide a multi-clock multi-task parallel real-time simulation system and a method, which solve the problem that the prior art cannot carry out multi-clock multi-task simulation, and can form a homologous clock drive and a heterogeneous clock drive according to the multi-task application requirement so as to drive the multi-task simulation requirement.
In order to achieve the above object, the present invention provides a multi-clock and multi-task parallel real-time simulation system, comprising: the clock domain control module is used for acquiring a plurality of pulse clock sources and outputting a plurality of clock excitation information to the simulation control module; the simulation control module is used for distributing and controlling the clock excitation information through a clock scheduling mechanism, sending clock scheduling driving signals to a plurality of simulation tasks and simultaneously monitoring the data of the simulation tasks in real time; the hardware interface mapping module is used for describing the operation of the hardware interface in the form of a simulation task language; and the simulation task module is used for carrying out independent operation once under the driving of the clock scheduling driving signal of the simulation control module and completing corresponding hardware interface operation once through the hardware interface mapping module.
Wherein the clock excitation information comprises: the same source clock excitation information and/or the heterogeneous clock excitation information.
Wherein, the simulation task comprises: several isochronous tasks and/or several asynchronous tasks.
The clock domain control module comprises: the pulse clock acquisition submodule is used for acquiring a clock signal in a pulse clock source, performing interrupt entrustment on the acquired pulse clock source and sending the pulse clock signal to the clock excitation submodule; the bus clock acquisition submodule is used for acquiring bus signals in a bus, performing data driving on the acquired bus data signals, performing interrupt delegation and sending the bus data signals to the clock excitation submodule; and the clock excitation submodule is used for receiving the interrupt entrusts of the pulse clock acquisition submodule and the bus clock acquisition submodule, and when receiving a time pulse clock signal or a bus data driving signal, the clock excitation submodule generates a clock excitation signal and sends the clock excitation signal to the simulation control module.
The simulation control module comprises: the resource configuration submodule is used for sending the resource configuration information of a plurality of simulation tasks to the simulation task centralized middle-layer submodule and sending the clock information of the plurality of simulation tasks to the clock scheduling submodule; the clock scheduling submodule is used for acquiring clock excitation information from the clock domain control module; and the simulation task centralized interlayer submodule is used for defining the basic attributes of the simulation tasks, instantiating a plurality of simulation tasks according to the resource configuration information and the clock excitation information and forming a simulation task set.
The basic attributes of the simulation task comprise: processor information on which the emulation task runs, hardware environment, supervisory bus environment, and clock excitation information interface.
The simulation control module further comprises: and the simulation task set scheduling submodule is used for suspending the simulation task module, and sending a clock scheduling driving signal of the corresponding simulation task to the simulation task module after the simulation task module receives the corresponding clock excitation information when the clock excitation is triggered.
The simulation control module further comprises: the data discovery submodule is used for monitoring data request information in the monitoring bus and finishing the extraction of required data in the simulation task set scheduling submodule through a queue of inter-task communication; the data simultaneous transmission sub-module is used for sending the data content in the data discovery sub-module to the simulation system dynamic monitoring upper computer through the monitoring bus, receiving a simulation data modification instruction of the simulation system dynamic monitoring upper computer and modifying the data of the corresponding simulation task module; and the data storage sub-module is used for locally storing the data content in the data discovery sub-module, the simulation data modification instruction of the simulation system dynamic monitoring upper computer and the operation content of the data transmission sub-module.
The hardware operation of the hardware interface mapping module specification comprises: analog quantity acquisition operation, analog quantity output operation, I/O interface read-write operation, inter-task memory exchange operation, bus data read-write operation, reflective memory data read-write operation and network communication protocol read-write operation; the bus data read-write operation comprises the following steps: CAN bus data read-write operation and 1553B bus data read-write operation.
The invention also provides a method for scheduling the same-source different-period and/or different-source multi-task clocks, which adopts the multi-clock multi-task parallel real-time simulation system and comprises the following steps:
the first step is as follows: deploying clock information periods { T _1, T _2,... T _ i, …, T _ n } of each isochronous or/and asynchronous task { M _1, M _2,. M _ i, …, M _ n } in a resource configuration submodule;
the second step is that: in the initialization process of the simulation system, a clock scheduling submodule loads a resource configuration submodule to acquire clock information periods { T _1, T _2,. T _ i, …, T _ n } of synchronous or/and asynchronous task tasks { M _1, M _2,. M _ i, …, M _ n };
the third step: suspending clock excitation in the clock excitation submodule and waiting for clock excitation triggering;
the fourth step: when a synchronous task is carried out, when clock excitation is triggered, marking a current state clock T and accumulating, traversing a clock information period { T _1, T _2,. T _ i, … and T _ n } of the synchronous task, judging whether the current state clock T meets T ═ T _ i, triggering a clock scheduling driving signal of a corresponding task M _ i when the condition is met, and otherwise, waiting for next clock excitation until the traversal is completed; when asynchronous task is carried out, when clock excitation i of heterogeneous clock i is triggered, clock scheduling driving signal i is triggered, asynchronous task i responds to execution and waits for triggering of other clock excitation.
The invention also provides a time sequence signal response method for the same-source different-period and/or heterogeneous multi-task clock scheduling, which triggers clock excitation according to the method for the same-source different-period and/or heterogeneous multi-task clock scheduling, and triggers the ith clock scheduling driving signal when the current time ti is T _ i, so that the ith synchronous or/and asynchronous task is responded and executed.
When n synchronous tasks are carried out, the fundamental frequency of a homologous clock is T0, when T _ i is i T0, 0< i is not more than n and is a natural number, at the time ti, for the p-th synchronous task, 0< p is not more than n and is a natural number, when i can be divided by p, the p-th clock schedules a driving signal to trigger, and the p-th synchronous task responds to execute; when i cannot be divided by p, the p-th clock scheduling driving signal is not triggered; when i is equal to 0, at time t0, n clock scheduling driving signals corresponding to n synchronous tasks are all triggered, and the n synchronous tasks are all executed in response.
When n asynchronous tasks are carried out, the trigger time of the clock scheduling driving signal corresponding to each asynchronous task is separated, so that each asynchronous task respectively responds to and executes, and each asynchronous task has no common synchronous node.
The multi-clock and multi-task parallel real-time simulation system and the method solve the problem that the prior art can not carry out multi-clock and multi-task simulation, and have the following advantages:
(1) the simulation system of the invention distributes and schedules the acquired clock excitation information, and forms a homologous clock drive and a heterogeneous clock drive according to the multi-task application requirement so as to drive the multi-task simulation requirement;
(2) the invention extracts the difference resources (CPU, hardware environment, monitoring bus environment and clock excitation information) of each simulation task and the simulation task through the simulation task centralized interlayer sub-module, so that the design and maintenance of the simulation task are more flexible and independent;
(3) the invention takes bus data drive as a method of the simulation clock, and expands the multi-clock application of the simulation system and the application scene of the distributed bus;
(4) the invention can carry out heterogeneous clock multitask clock scheduling, under the condition of no conflict of hardware resources, the multitask parallel operation has no correlation characteristic, so that the simulation system can be applied to a plurality of simulation tasks, the reusability of the simulation system equipment is increased, and the utilization rate of the equipment is improved;
(5) the invention provides a simulation system for the application of real-time simulation of a multi-unit formation type, and the system can be used as an aggregate of the multi-unit to simulate the formation type and can also be used as a unit individual to participate in the aggregate of the multi-unit to simulate the formation type. When the simulation system is used as an aggregate of multiple units, each unit is used as a synchronous task in the simulation system and is controlled by a same source clock; when the simulation system is taken as a unit individual, the simulation system is applied to one of synchronous tasks in a formation system and is controlled by a same source clock in the formation system.
Drawings
Fig. 1 is a schematic structural diagram of a multi-clock and multi-task parallel real-time simulation system according to embodiment 1 of the present invention.
Fig. 2 is a flowchart of the same-source asynchronous multi-task clock scheduling according to embodiment 1 of the present invention.
Fig. 3 is a timing diagram of the same-source asynchronous multi-task clock scheduling according to embodiment 1 of the present invention.
Fig. 4 is a flowchart of heterogeneous clock multitask clock scheduling according to embodiment 2 of the present invention.
Fig. 5 is a timing diagram of the heterogeneous clock multitask clock scheduling in embodiment 2 of the present invention.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
The invention relates to a multi-clock and multi-task parallel real-time simulation system, which comprises: the clock domain control module is used for acquiring a plurality of pulse clock sources and outputting a plurality of clock excitation information to the simulation control module; the simulation control module is used for distributing and controlling the clock excitation information, sending the clock excitation information to the plurality of simulation tasks and monitoring the data of the simulation tasks in real time; the hardware interface mapping module is used for describing the operation of the hardware interface in the form of a simulation task language; and the simulation task module is used for completing one independent operation under the driving of the clock excitation information of the simulation control module and completing one corresponding hardware interface operation through the hardware interface mapping module.
The clock excitation information includes: the same source clock excitation information and/or the heterogeneous clock excitation information. The simulation task comprises the following steps: several isochronous tasks and/or several asynchronous tasks.
The clock domain control module comprises: the pulse clock acquisition submodule is used for acquiring a clock signal in a pulse clock source, performing interrupt entrustment on the acquired pulse clock source and sending the pulse clock signal to the clock excitation submodule; the bus clock acquisition submodule is used for acquiring bus signals in a bus, performing data driving on the acquired bus data signals, performing interrupt delegation and sending the bus data signals to the clock excitation submodule; and the clock excitation submodule is used for receiving the interrupt entrusts of the pulse clock acquisition submodule and the bus clock acquisition submodule, and when receiving a time pulse clock signal or a bus data driving signal, the clock excitation submodule generates a clock excitation signal and sends the clock excitation signal to the simulation control module.
The simulation control module comprises: the resource configuration submodule is used for sending the resource configuration information of a plurality of simulation tasks to the simulation task centralized middle-layer submodule and sending the clock information of the plurality of simulation tasks to the clock scheduling submodule; the clock scheduling submodule is used for acquiring clock excitation information from the clock domain control module; and the simulation task centralized interlayer submodule is used for defining the basic attributes of the simulation tasks, instantiating a plurality of simulation tasks according to the resource configuration information and the clock excitation information and forming a simulation task set.
The basic attributes of the simulation task include: processor information on which the emulation task runs, hardware environment, supervisory bus environment, and clock excitation information interface.
The simulation control module further comprises: and the simulation task set scheduling submodule is used for suspending the simulation task module, and sending a clock scheduling driving signal of the corresponding simulation task to the simulation task module after the simulation task module receives the corresponding clock excitation information when the clock excitation is triggered.
The simulation control module further comprises: the data discovery submodule is used for monitoring data request information in the monitoring bus and finishing the extraction of required data in the simulation task set scheduling submodule through a queue of communication among tasks; the data synchronous transmission sub-module is used for sending the data content in the data discovery sub-module to the simulation system dynamic monitoring upper computer through the monitoring bus, receiving a simulation data modification instruction of the simulation system dynamic monitoring upper computer and modifying the data of the corresponding simulation task module; and the data storage submodule is used for locally storing the data content in the data discovery submodule, the simulation data modification instruction of the simulation system dynamic monitoring upper computer and the operation content of the data synchronous transmission submodule.
The hardware operations of the above hardware interface mapping module specification further include (but are not limited to): analog quantity acquisition operation, analog quantity output operation, I/O interface read-write operation, inter-task memory exchange operation, bus data read-write operation, reflective memory data read-write operation and network communication protocol read-write operation. The hardware operation of the hardware interface mapping module specification can also be other extensible custom hardware interface operation.
The bus data read-write operation comprises the following steps: CAN bus data read-write operation and 1553B bus data read-write operation.
The invention relates to a method for scheduling homologous different periods and/or heterogeneous multitask clocks, which adopts a multi-clock and multi-task parallel real-time simulation system and comprises the following steps:
the first step is as follows: deploying clock information periods { T _1, T _2,... T _ i, …, T _ n } of each isochronous or/and asynchronous task { M _1, M _2,. M _ i, …, M _ n } in a resource configuration submodule;
the second step is that: in the initialization process of the simulation system, a clock scheduling submodule loads a resource configuration submodule to acquire clock information periods { T _1, T _2,. T _ i, …, T _ n } of synchronous or/and asynchronous task tasks { M _1, M _2,. M _ i, …, M _ n };
the third step: suspending clock excitation in the clock excitation submodule and waiting for clock excitation triggering;
the fourth step: when a synchronous task is carried out, when clock excitation is triggered, marking a current state clock T and accumulating, traversing a clock information period { T _1, T _2,. T _ i, … and T _ n } of the synchronous task, judging whether the previous state clock T meets T ═ T _ i, triggering a clock scheduling driving signal of a corresponding task M _ i when the condition is met, and otherwise, waiting for next clock excitation until the traversal is completed; when asynchronous task is carried out, when clock excitation i of heterogeneous clock i is triggered, clock scheduling driving signal i is triggered, asynchronous task i responds to execution and waits for triggering of other clock excitation.
The invention relates to a time sequence signal response method for homologous different period and/or heterogeneous multitask clock scheduling, which triggers clock excitation according to the homologous different period and/or heterogeneous multitask clock scheduling method, and triggers an ith clock scheduling driving signal when the current time ti is T _ i, so that the ith synchronous or/and asynchronous task is responded and executed.
When n synchronous tasks are carried out, the fundamental frequency of a homologous clock is T0, when T _ i is i T0, 0< i is not more than n and is a natural number, at the time ti, for the p-th synchronous task, 0< p is not more than n and is a natural number, when i can be divided by p, the p-th clock schedules a driving signal to trigger, and the p-th synchronous task responds to execute; when i cannot be divided by p, the p-th clock scheduling driving signal is not triggered; when i is equal to 0, at time t0, n clock scheduling driving signals corresponding to n synchronous tasks are all triggered, and the n synchronous tasks are all executed in response.
When n asynchronous tasks are carried out, the trigger time of the clock scheduling driving signal corresponding to each asynchronous task is separated, so that each asynchronous task respectively responds to and executes, and each asynchronous task has no common synchronous node.
Example 1
As shown in fig. 1, a schematic structural diagram of a multi-clock and multi-task parallel real-time simulation system according to embodiment 1 of the present invention is shown, where the system includes: the system comprises a simulation control module 1, a clock domain control module 2, a simulation task module 3 and a hardware interface mapping module 4.
Wherein, the simulation control module 1 comprises: the system comprises a resource configuration submodule 101, a simulation task set scheduling submodule 102, a simulation task set middle-layer submodule 103, a clock scheduling submodule 104, a data discovery submodule 105, a data simultaneous transmission submodule 106 and a data storage submodule 106.
Wherein, the clock domain control module 2 comprises: a pulse clock acquisition submodule 202, a bus clock acquisition submodule 203 and a clock excitation submodule 201.
A method for scheduling a homologous and asynchronous multi-task clock, as shown in fig. 2, which is a flowchart of the homologous and asynchronous multi-task clock scheduling in embodiment 1 of the present invention, when performing homologous and asynchronous multi-task clock scheduling driving, the method specifically includes:
first step S1: deploying, in the resource configuration submodule 101, clock information periods { T _1, T _2,. T _ i, …, T _ n } of each synchronization task { M _1, M _2,. M _ i, …, M _ n };
second step S2: the clock scheduling sub-module 104 loads the resource configuration sub-module 101 during the initialization process of the simulation system, and obtains the clock information periods { T _1, T _2,. T _ i, …, T _ n } of the synchronization tasks { M _1, M _2,. M _ i, …, M _ n };
third step S3: suspending clock excitation in the clock excitation submodule and waiting for clock excitation triggering;
fourth step S4: when clock excitation is triggered, marking a current state clock T for accumulation, traversing a clock information period { T _1, T _2,. T _ i, …, T _ n } of a synchronous task, judging whether the previous state clock T meets T ═ T _ i, triggering a clock scheduling driving signal of a corresponding task M _ i when the condition is met, and otherwise, waiting for next clock excitation until traversal is completed.
A timing signal response method for homologous and asynchronous clock scheduling, as shown in fig. 3, is a timing chart of homologous and asynchronous clock scheduling in embodiment 1 of the present invention, and a simulation task of a simulation system in this embodiment includes: the three synchronization tasks are synchronization task 1A (1 st synchronization task), synchronization task 2A (2 nd synchronization task), and synchronization task 3A (3 rd synchronization task), respectively. The simulation cycle (i.e., clock information cycle) of the sync task 1A is T1, the simulation cycle (i.e., clock information cycle) of the sync task 2A is T2, and the simulation cycle (i.e., clock information cycle) of the sync task 3A is T3. The fundamental frequency of the homologous clock of the present system is T0. Wherein, T1-T0, T2-2T 0 and T3-3T 0. After the homologous different-period multi-task clock is scheduled and started, the task response conditions in different periods are as follows:
(1) when t0(t0 ═ 0) triggers, the clock scheduling driving signal 1B (1 st clock scheduling driving signal) triggers, and the synchronous task 1A responds to execution; triggering a clock scheduling driving signal 2B (a 2 nd clock scheduling driving signal), and responding and executing a synchronous task 2A; triggering a clock scheduling driving signal 3B (a 3 rd clock scheduling driving signal), and responding and executing a synchronous task 3A;
(2) when T1(T1 ═ T1) triggers, the clock scheduling driving signal 1B triggers, and the synchronous task 1A responds to execution; the clock scheduling driving signal 2B is not triggered, and the clock scheduling driving signal 3B is not triggered;
(3) when T2(T2 ═ T2) triggers, the clock scheduling driving signal 1B triggers, and the synchronous task 1A responds to execution; triggering a clock scheduling driving signal 2B, and responding and executing a synchronous task 2A; the clock scheduling driving signal 3B is not triggered;
(4) when T3(T3 ═ T3) triggers, the clock scheduling driving signal 1B triggers, and the synchronous task 1A responds to execution; the clock scheduling driving signal 2B is not triggered; triggering a clock scheduling driving signal 3B, and responding and executing a synchronous task 3A;
(5) when T4(T4 ═ 4T0) triggers, the clock scheduling driving signal 1B triggers, and the synchronous task 1A responds to execution; triggering a clock scheduling driving signal 2B, and responding and executing a synchronous task 2A; the clock scheduling driving signal 3B is not triggered;
(6) when T5(T5 ═ 5T0) triggers, the clock scheduling driving signal 1B triggers, and the synchronous task 1A responds to execution; the clock scheduling driving signal 2B is not triggered; the clock scheduling driving signal 3B is not triggered;
(7) when T6(T6 ═ 6T0) triggers, the clock schedule drive signal 1B triggers, and the synchronous task 1 responds to execution; triggering a clock scheduling driving signal 2B, and responding and executing a synchronous task 2A; the clock scheduling driving signal 3B triggers and the synchronous task 3A responds to execution.
T0 and t6 are the synchronization points of the simulation task set in the above-mentioned same source asynchronous multi-task clock scheduling.
Example 2
A method for scheduling a heterogeneous multi-task clock, as shown in fig. 4, which is a flowchart of scheduling a heterogeneous clock multi-task clock according to embodiment 2 of the present invention, when performing heterogeneous clock multi-task clock scheduling driving, the method specifically includes:
first step S1': clock information periods { T _1, T _2, · T _ i, …, T _ n } of various asynchronous tasks { M _1, M _2,. M _ i, …, M _ n } are deployed in the resource configuration submodule 101;
second step S2': in the initialization process of the simulation system, the clock scheduling sub-module 104 loads the resource configuration sub-module 101 to obtain the clock information periods { T _1, T _2,. T _ i, …, T _ n } of the asynchronous tasks { M _1, M _2,. M _ i, …, M _ n }
Third step S3': suspending each heterogeneous clock excitation in the clock excitation submodule and waiting for clock excitation triggering;
fourth step S4': when the clock excitation i of the heterogeneous clock i is triggered, the clock scheduling driving signal i is triggered, the asynchronous task i responds to execution, and the rest clock excitation is waited to trigger.
A timing signal response method for heterogeneous multi-task clock scheduling, as shown in fig. 5, is a timing diagram of heterogeneous clock multi-task clock scheduling in embodiment 2 of the present invention, and a simulation task of a simulation system in this embodiment further includes: two asynchronous tasks, respectively asynchronous task 1A '(asynchronous task 1 st) and asynchronous task 2A' (asynchronous task 2 nd). The simulation cycle (i.e., clock information cycle) of the asynchronous task 1A 'is T1, and the simulation cycle (i.e., clock information cycle) of the asynchronous task 2A' is T2. After the heterogeneous clock multitask clock is scheduled and started, task response conditions in different periods are as follows:
(1) when t0, t1, t2, t3, t4, t5, t6 trigger, the clock scheduling driving signal 1B '(the 1 st clock scheduling driving signal) triggers, and the asynchronous task 1A' responds to execution;
(2) when t10, t11, t12 and t13 trigger, t10 is slower than t0 by half period, t11 is slower than t2 by half period, t12 is slower than t4 by half period, t13 is slower than t6 by half period, the clock scheduling driving signal 2B '(the 2 nd clock scheduling driving signal) triggers, and the asynchronous task 2A' responds and executes;
the above-described asynchronization task 1 and asynchronization task 2 do not have a common synchronization node.
In summary, the multi-clock and multi-task parallel real-time simulation system and method of the present invention can form a homologous clock driver and a heterogeneous clock driver according to the multi-task application requirement, thereby satisfying the parallel simulation requirement of multi-clock and multi-task.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (9)
1. A multi-clock, multi-task, parallel real-time simulation system, comprising:
the clock domain control module is used for acquiring a plurality of pulse clock sources and outputting a plurality of clock excitation information to the simulation control module;
the simulation control module is used for distributing and controlling the clock excitation information through a clock scheduling mechanism, sending clock scheduling driving signals to a plurality of simulation tasks and simultaneously monitoring the data of the simulation tasks in real time;
the hardware interface mapping module is used for describing the operation of the hardware interface in the form of a simulation task language; and
the simulation task module is used for carrying out independent operation once under the driving of a clock scheduling driving signal of the simulation control module and completing corresponding hardware interface operation once through the hardware interface mapping module;
wherein the clock excitation information comprises: homologous clock excitation information and/or heterogeneous clock excitation information;
wherein, the simulation task comprises: a number of isochronous tasks and/or a number of asynchronous tasks;
the clock domain control module comprises:
the pulse clock acquisition submodule is used for acquiring a clock signal in a pulse clock source, performing interrupt entrustment on the acquired pulse clock source and sending the pulse clock signal to the clock excitation submodule;
the bus clock acquisition submodule is used for acquiring bus signals in a bus, performing data driving on the acquired bus data signals, performing interrupt delegation and sending the bus data signals to the clock excitation submodule;
and the clock excitation submodule is used for receiving the interrupt entrusts of the pulse clock acquisition submodule and the bus clock acquisition submodule, and when receiving a time pulse clock signal or a bus data driving signal, the clock excitation submodule generates a clock excitation signal and sends the clock excitation signal to the simulation control module.
2. The multi-clock, multi-task and parallel real-time simulation system of claim 1, wherein the simulation control module comprises:
the resource configuration submodule is used for sending the resource configuration information of a plurality of simulation tasks to the simulation task centralized middle-layer submodule and sending the clock information of the plurality of simulation tasks to the clock scheduling submodule;
the clock scheduling submodule is used for acquiring clock excitation information from the clock domain control module;
and the simulation task centralized interlayer submodule is used for defining the basic attributes of the simulation tasks, instantiating a plurality of simulation tasks according to the resource configuration information and the clock excitation information and forming a simulation task set.
3. The multi-clock, multi-task and parallel real-time simulation system of claim 2, wherein the basic properties of the simulation task comprise: processor information on which the emulation task runs, hardware environment, supervisory bus environment, and clock excitation information interface.
4. The multi-clock, multi-task and parallel real-time simulation system of claim 2, wherein the simulation control module further comprises:
and the simulation task set scheduling submodule is used for suspending the simulation task module, and sending a clock scheduling driving signal of the corresponding simulation task to the simulation task module after the simulation task module receives the corresponding clock excitation information when the clock excitation is triggered.
5. The multi-clock, multi-task and parallel real-time simulation system of claim 4, wherein the simulation control module further comprises:
the data discovery submodule is used for monitoring data request information in the monitoring bus and finishing the extraction of required data in the simulation task set scheduling submodule through a queue of inter-task communication;
the data simultaneous transmission sub-module is used for sending the data content in the data discovery sub-module to the simulation system dynamic monitoring upper computer through the monitoring bus, receiving a simulation data modification instruction of the simulation system dynamic monitoring upper computer and modifying the data of the corresponding simulation task module; and
and the data storage sub-module is used for locally storing the data content in the data discovery sub-module, the simulation data modification instruction of the simulation system dynamic monitoring upper computer and the operation content of the data synchronous transmission sub-module.
6. The multi-clock, multi-task, parallel real-time simulation system of claim 2, wherein the hardware operations of the hardware interface mapping module specification comprise: analog quantity acquisition operation, analog quantity output operation, I/O interface read-write operation, inter-task memory exchange operation, bus data read-write operation, reflective memory data read-write operation and network communication protocol read-write operation;
the bus data read-write operation comprises the following steps: CAN bus data read-write operation and 1553B bus data read-write operation.
7. A method for scheduling homogeneous multicycle and/or heterogeneous multitask clocks, which is characterized in that the method employs the multi-clock multitask parallel real-time simulation system as claimed in any one of claims 2-6, and comprises:
the first step is as follows: deploying clock information periods { T _1, T _2,... T _ i, …, T _ n } of each isochronous or/and asynchronous task { M _1, M _2,. M _ i, …, M _ n } in a resource configuration submodule;
the second step is that: in the initialization process of the simulation system, a clock scheduling submodule loads a resource configuration submodule to acquire clock information periods { T _1, T _2,. T _ i, …, T _ n } of synchronous or/and asynchronous task tasks { M _1, M _2,. M _ i, …, M _ n };
the third step: suspending clock excitation in the clock excitation submodule and waiting for clock excitation triggering;
the fourth step: when a synchronous task is carried out, when clock excitation is triggered, marking a current state clock T and accumulating, traversing a clock information period { T _1, T _2,. T _ i, …, T _ n } of the synchronous task, judging whether the current state clock T meets T ═ T _ i, if so, triggering a clock scheduling driving signal corresponding to the task M _ i, otherwise, waiting for next clock excitation until the traversal is completed; when asynchronous task is carried out, when clock excitation i of heterogeneous clock i is triggered, clock scheduling driving signal i is triggered, asynchronous task i responds to execution and waits for triggering of other clock excitation.
8. A method for responding to timing signals of a homogeneous metacycle and/or heterogeneous multitask clock scheduling, characterized in that the method triggers clock excitation by the method for homogeneous metacycle and/or heterogeneous multitask clock scheduling according to claim 7, and triggers an ith clock scheduling driving signal when a current time ti is T _ i, so that an ith synchronous or/and asynchronous task response is executed.
9. The method according to claim 8, wherein the base frequency of the homologous clock is T0 when n synchronization tasks are performed, when T _ i ═ T0, 0< i ≦ n, and is a natural number, at time ti, for the p-th synchronization task, 0< p ≦ n, and is a natural number, and when i can be divided by p, the p-th clock scheduling driving signal triggers and the p-th synchronization task is performed in response; when i cannot be divided by p, the p-th clock scheduling driving signal is not triggered; when i is equal to 0, at the time t0, triggering n clock scheduling driving signals corresponding to n synchronous tasks, wherein the n synchronous tasks are all executed in response;
when n asynchronous tasks are carried out, the trigger time of the clock scheduling driving signal corresponding to each asynchronous task is separated, so that each asynchronous task respectively responds to and executes, and each asynchronous task has no common synchronous node.
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