CN111008065A - Multi-branch parallel simulation method - Google Patents
Multi-branch parallel simulation method Download PDFInfo
- Publication number
- CN111008065A CN111008065A CN201911234744.9A CN201911234744A CN111008065A CN 111008065 A CN111008065 A CN 111008065A CN 201911234744 A CN201911234744 A CN 201911234744A CN 111008065 A CN111008065 A CN 111008065A
- Authority
- CN
- China
- Prior art keywords
- simulation
- clock
- task
- module
- flow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004088 simulation Methods 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004891 communication Methods 0.000 claims abstract description 14
- 230000005284 excitation Effects 0.000 claims description 6
- 238000004364 calculation method Methods 0.000 claims description 5
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000002452 interceptive effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention provides a multi-branch parallel simulation method, which comprises the following steps of S1, defining a simulation soft bus, wherein the simulation soft bus is a virtual bus running in a plurality of simulators; s2, each simulator receives a simulation task for simulation and is connected to the same virtual bus; s3, dividing each simulation task into three communication data of clock flow, control flow and data flow; s4, dividing the three communication data into different subtasks according to the subordinate simulation tasks; s5, each of the plurality of simulators is assigned to execute one or more corresponding subtasks of the simulation task; s6, executing the simulation task by calling each simulator to execute the corresponding sub-task; the method has the advantages of fast and stable simulation operation.
Description
Technical Field
The invention belongs to the technical field of simulation, and particularly relates to a multi-branch parallel simulation method.
Background
The traditional simulation scheduling belongs to hard real-time scheduling, the simulation progress is strictly consistent with a physical clock, and the simulation model is easy to overtime, so that the simulation fails; in the dispatching center, the interactive data of the distributed model interface which can be stored is limited and far less than the requirement of large data volume of a modern simulation system; as the multi-branch parallel simulation system develops to multi-user concurrent simulation, it becomes more important to ensure the safe operation of the simulation system.
Disclosure of Invention
The invention aims to provide a multi-branch parallel simulation method to solve the problems that the traditional simulation mode cannot meet the requirements of the development of the existing sub-parallel simulation system to multi-user concurrent simulation, the simulation failure is easy to cause, the interactive data of a distributed model interface is limited, and the like.
The invention provides the following technical scheme:
a multi-branch parallel simulation method comprises the following steps: s1, defining a simulation soft bus which is a virtual bus running in a plurality of simulators; s2, each simulator receives a simulation task for simulation and is connected to the same virtual bus; s3, dividing each simulation task into three communication data of clock flow, control flow and data flow; s4, dividing the three communication data into different subtasks according to the subordinate simulation tasks; s5, each of the plurality of simulators is assigned to execute one or more corresponding subtasks of the simulation task; s6, executing the simulation task by calling each simulator to execute the corresponding sub-task.
Further, the simulator comprises a clock domain module, a control module, an interface module and a simulation module.
Further, the clock domain module is configured to obtain communication data of a clock stream and output a plurality of clock excitation information to the control module; the control module is used for acquiring communication data of control flow, distributing and controlling the clock excitation information, sending clock scheduling driving signals to the plurality of simulation tasks and monitoring the data of the simulation tasks in real time; the hardware module is used for describing the operation of the hardware interface in the form of a simulation task language; and the simulation module is used for carrying out independent operation once under the driving of the clock scheduling driving signal of the control module and completing corresponding hardware interface operation once through the hardware module.
Furthermore, the subtasks are divided into a control flow use control subtask, a clock flow use clock subtask and a data flow use data subtask according to the clock flow, the control flow and the data flow.
Furthermore, the simulation task is composed of at least one simulation scheduling engine, at least one simulation model and a simulation soft bus, and is distributed and deployed to a plurality of simulators according to the consumption of the simulation model and the calculation resources of the simulation model, wherein the calculation resources refer to the percentage of the CPU occupied by the simulation model and the size of the memory occupied space, and the calculation resources are distributed and deployed to the plurality of simulators according to the requirements.
Further, the CPU is configured to represent the simulation task as a hierarchical tree structure and divide the simulation task into the subtasks by recursively traversing the hierarchical tree structure.
The invention has the beneficial effects that:
the invention relates to a multi-branch parallel simulation method, which realizes the concurrent execution of multi-simulation tasks of a multi-purpose simulator through the design of a simulation soft bus; the correct operation of the distributed parallel simulation system is ensured by adding the simulation scheduling backup; the simulation task is executed by calling each simulator to execute the corresponding distributed subtasks, and parallel processing is used for reducing simulation time; the problem of limited interaction data of the distributed model interface is solved through a plurality of simulators.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic flow diagram of the process of the present invention.
Detailed Description
As shown in fig. 1, a multi-branch parallel simulation method includes the following steps:
s1, defining a simulation soft bus which is a virtual bus running in a plurality of simulators;
s2, each simulator receives a simulation task for simulation and is connected to the same virtual bus;
s3, dividing each simulation task into three communication data of clock flow, control flow and data flow;
the simulator comprises a clock domain module, a control module, an interface module and a simulation module.
The clock domain module is used for acquiring communication data of clock streams and outputting a plurality of clock excitation information to the control module; the control module is used for acquiring communication data of control flow, distributing and controlling clock excitation information, sending clock scheduling driving signals to the plurality of simulation tasks and monitoring the data of the simulation tasks in real time; the hardware module is used for describing the operation of the hardware interface in the form of a simulation task language; and the simulation module is used for carrying out independent operation once under the driving of the clock scheduling driving signal of the control module and completing corresponding hardware interface operation once through the hardware module.
S4, dividing the three communication data into different subtasks according to the subordinate simulation tasks;
the subtasks are divided into a control flow use control subtask, a clock flow use clock subtask, and a data flow use data subtask according to a clock flow, a control flow, and a data flow.
S5, each of the plurality of simulators is assigned to execute one or more corresponding subtasks of the simulation task;
and S6, executing the simulation task by calling each simulator to execute the corresponding sub-task.
The simulation task consists of at least one simulation scheduling engine, at least one simulation model and a simulation soft bus, and is distributed and deployed into a plurality of simulators according to the consumption of the simulation model and the calculation resources, namely the percentage of the simulation model occupying the CPU and the size of the memory occupying space, as required, so that at least one simulation model operates in each simulator; the CPU is configured to represent the simulation task as a hierarchical tree structure and to divide the simulation task into subtasks by recursively traversing the hierarchical tree structure.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A multi-branch parallel simulation method is characterized by comprising the following steps:
s1, defining a simulation soft bus which is a virtual bus running in a plurality of simulators;
s2, each simulator receives a simulation task for simulation and is connected to the same virtual bus;
s3, dividing each simulation task into three communication data of clock flow, control flow and data flow;
s4, dividing the three communication data into different subtasks according to the subordinate simulation tasks;
s5, each of the plurality of simulators is assigned to execute one or more corresponding subtasks of the simulation task;
s6, executing the simulation task by calling each simulator to execute the corresponding sub-task.
2. The method of claim 1, wherein the simulator comprises a clock domain module, a control module, an interface module and a simulation module.
3. The method according to claim 2, wherein the clock domain module is configured to obtain communication data of a clock stream and output a plurality of clock excitation information to the control module; the control module is used for acquiring communication data of control flow, distributing and controlling the clock excitation information, sending clock scheduling driving signals to the plurality of simulation tasks and monitoring the data of the simulation tasks in real time; the hardware module is used for describing the operation of the hardware interface in the form of a simulation task language; and the simulation module is used for carrying out independent operation once under the driving of the clock scheduling driving signal of the control module and completing corresponding hardware interface operation once through the hardware module.
4. The method of claim 1, wherein the subtasks are divided into a control flow use subtask, a clock flow use clock subtask, and a data flow use data subtask according to clock flow, control flow, and data flow.
5. The method according to claim 1, wherein the simulation task comprises at least one simulation scheduling engine, at least one simulation model and a simulation soft bus, and the simulation scheduling engine, the at least one simulation model and the simulation soft bus are distributed and deployed to a plurality of simulators according to the consumption of the simulation model and the calculation resources, namely the percentage of the simulation model occupying the CPU and the size of the memory occupying space, according to needs, so that at least one simulation model runs in each simulator.
6. The method according to claim 5, wherein said CPU is configured to represent said simulation tasks as a hierarchical tree structure and to divide said simulation tasks into said subtasks by recursively traversing said hierarchical tree structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911234744.9A CN111008065A (en) | 2019-12-05 | 2019-12-05 | Multi-branch parallel simulation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911234744.9A CN111008065A (en) | 2019-12-05 | 2019-12-05 | Multi-branch parallel simulation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111008065A true CN111008065A (en) | 2020-04-14 |
Family
ID=70114780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911234744.9A Pending CN111008065A (en) | 2019-12-05 | 2019-12-05 | Multi-branch parallel simulation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111008065A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140052430A1 (en) * | 2012-04-27 | 2014-02-20 | Mentor Graphics Corporation | Partitionless Multi User Support For Hardware Assisted Verification |
| CN107220107A (en) * | 2017-06-29 | 2017-09-29 | 上海新跃联汇电子科技有限公司 | A kind of multi-clock multi-task parallel real-time emulation system and method |
| CN109800054A (en) * | 2018-12-24 | 2019-05-24 | 四川知周科技有限责任公司 | A kind of distributed parallel real-time simulation scheduling implementation method |
-
2019
- 2019-12-05 CN CN201911234744.9A patent/CN111008065A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140052430A1 (en) * | 2012-04-27 | 2014-02-20 | Mentor Graphics Corporation | Partitionless Multi User Support For Hardware Assisted Verification |
| CN107220107A (en) * | 2017-06-29 | 2017-09-29 | 上海新跃联汇电子科技有限公司 | A kind of multi-clock multi-task parallel real-time emulation system and method |
| CN109800054A (en) * | 2018-12-24 | 2019-05-24 | 四川知周科技有限责任公司 | A kind of distributed parallel real-time simulation scheduling implementation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8069446B2 (en) | Parallel programming and execution systems and techniques | |
| Coakley et al. | Exploitation of high performance computing in the FLAME agent-based simulation framework | |
| CN112286645B (en) | GPU resource pool scheduling system and method | |
| CN108710536B (en) | Multilevel fine-grained virtualized GPU (graphics processing Unit) scheduling optimization method | |
| CN109814990A (en) | A kind of distributed parallel collaborative simulation framework | |
| CN102279766A (en) | Method and system for concurrently simulating processors and scheduler | |
| KR20050000487A (en) | Scheduling method and realtime processing system | |
| CN105830026A (en) | Apparatus and method for scheduling graphics processing unit workloads from virtual machines | |
| CN111552550A (en) | Task scheduling method, device and medium based on GPU (graphics processing Unit) resources | |
| CN103369054A (en) | Acquisition task management method and system | |
| US8768680B2 (en) | Simulator of multi-core system employing reconfigurable processor cores and method of simulating multi-core system employing reconfigurable processor cores | |
| CN115146582A (en) | Simulation method, simulation device, electronic apparatus, and computer-readable storage medium | |
| CN103077068A (en) | Realizing method for shared memory based high-performance simulation system | |
| CN102508696B (en) | A kind of asymmetric resource regulating method and device | |
| US7614056B1 (en) | Processor specific dispatching in a heterogeneous configuration | |
| CN103020008B (en) | The reconfigurable micro server that computing power strengthens | |
| CN111008065A (en) | Multi-branch parallel simulation method | |
| CN102331961A (en) | Method, system and dispatcher for simulating multiple processors in parallel | |
| US10592473B2 (en) | Method for improving energy efficiency of map-reduce system and apparatus thereof | |
| DE102020113932A1 (en) | VIRTUALIZATION AND MULTIPLE CLIENT SUPPORT IN GRAPHICS PROCESSORS | |
| CN112560184B (en) | Parallel computing system and method for aircraft simulation model | |
| CN114004730A (en) | Deep neural network multi-model parallel reasoning method based on graphics processor | |
| Liu et al. | BSPCloud: A hybrid distributed-memory and shared-memory programming model | |
| CN114610440A (en) | Method and system for constructing operating environment of simulator system | |
| CN113504966A (en) | GPU cluster scheduling strategy simulation method and GPU cluster simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200414 |
|
| RJ01 | Rejection of invention patent application after publication |