CN105701298A - Simulation platform design method based on Power PC SoC framework - Google Patents
Simulation platform design method based on Power PC SoC framework Download PDFInfo
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Abstract
A simulation platform design method based on a Power PC SoC framework comprises the following steps: instruction set simulation, using QEMU virtual machine dynamic binary system translation technology as an instruction set simulation device of the Power PC SoC framework simulation platform to carry out instruction set simulation; modeling key assemblies in the simulation platform, accurately modeling main equipment modules and slave equipment modules according to a System C transaction level modeling method, and designing the Power PC SoC framework simulation platform with complete functions; interruption design, realizing an interruption system of the simulation platform. The novel method can realize software and hardware cooperation simulation, can reduce design risks and error correction cost, can accelerate product design process, reduces product market period, and instruction set expansion and IP module functions can provide certain guide meanings for hardware development.
Description
Technical field
The present invention relates to a kind of Design of Simulation Platform method。Particularly relate to a kind of based on the modeling of SystemC transaction-level, the Design of Simulation Platform method based on PowerPCSoC framework on PowerPCSoC emulation platform basis。
Background technology
SoC design based on ESL (ESL, ElectronicSystemLevel) can build hardware platform fast Development/verification software application program rapidly, and then determines the optimum framework of system, it is achieved the collaborative design of the software and hardware of SoC。ESL design packet is containing two kinds of technology, a kind of method being based on transaction-level modeling, the behavior of hardware module is carried out Accurate Model by the available SystemC language of the method, and with the checking of this completion system and design space detection, but accurate modeling causes that described hardware platform simulation velocity is excessively slow, larger system/application software cannot be run, such as operating system, high definition video decoding etc.。Another kind of method is virtual machine technique, lays particular emphasis on the description to hardware capability。Therefore, simulation velocity is very fast, can run the large scale systems such as operating system or application software, but excessively thick modeling accuracy causes cannot the quality of SoC framework being estimated。How comprehensively the advantage of both the above method, improve simulation velocity while ensureing ESL design accuracy and become SoC design methodology field problem of interest。
PowerPC is the central processing unit of a kind of reduced instruction set computer framework being derived by POWER framework。PowerPC framework is acknowledged as the representative of second filial generation high-performance Reduced Instruction Set Computer。PowerPC has high-performance, high stability, reliability, good softwarecompatible, the advantages such as the chip performance range of choice is big, it is applied not only to large server, on individual PC, and is widely used in the fields such as automotive electronics, aviation electronics, monitoring device, printing device, Industry Control, armarium。
Summary of the invention
The technical problem to be solved is, there is provided a kind of while ensureing ESL design accuracy, improve simulation velocity so that user just can carry out the co-development of software and hardware and the Design of Simulation Platform method based on PowerPCSoC framework of functional verification under not having real hardware condition。
The technical solution adopted in the present invention is: a kind of Design of Simulation Platform method based on PowerPCSoC framework, comprises the steps:
1) instruction set simulation, adopts the binary translation technology of QEMU virtual machine to emulate flat isa simulator as PowerPCSoC framework and carries out instruction set simulation；
2) key component in emulation platform is modeled, based on SystemC transaction-level modeling method, complete main device module and the Accurate Model from EM equipment module, design the emulation platform of the PowerPCSoC framework with complete function；
3) design of interruption, it is achieved the interruption system of emulation platform。
Step 1) described in instruction set simulation be in QEMU on the basis of PowerPC framework realize, first all PowerPC instruction set are added in the instruction catalogue of QEMU, then go to search the corresponding instruction in QEMU instruction catalogue according to the operation code of PowerPC instruction。
Comprising two parts in described QEMU instruction catalogue, Part I is the definition according to instruction operation code, and the numerical value of operation is stored in QEMU instruction catalogue, forms the index of instruction catalogue；Part II is that described function resolves into microoperation command adapted thereto in order to realize the function corresponding to the function of arbitrary instruction。
Step 1) described in instruction set simulation specifically include:
Create op.c file, and define all of microoperation function；Each microoperation function in op.c file, capital generates a fixing microoperation eigenvalue functions, microoperation eigenvalue functions is each microoperation one fixing eigenvalue of distribution, define in the gen_op.h file created, PowerPC instruction translation is become multiple microoperation eigenvalue functions by the translate.c file created, and then generate microoperation eigenvalue array, according to microoperation eigenvalue array, search the microoperation concordance list that op.c file generates, generate TB block instruction Buffer, constitute the isa simulator of PowerPC, thus carrying out instruction set simulation。
Step 2) described in main device module include SystemCWrapper and isa simulator；Described includes from EM equipment module: memorizer, tty display, framebuffer frame buffer picture display module and time clock module。
Step 2) described in the Accurate Model to main device module include:
SystemCWrapper realizes a class, the described SystemCWrapper class realized provides a function interface ISStomemoryaccess accessing memorizer for isa simulator, main device module realizes two threads, one thread is used for realizing decoding flow process, carries out work decoding according to current PC value；Another one thread is used for realizing interrupt processing function；While (1) loop structure it is, to ensure the continuous service of main device module inside each thread；Main device module needs actively to send read-write requests to from EM equipment module, goes to read accordingly from the data of EM equipment module by bus by read and the write of main device module interface；Instruction fetch needs to access continually memorizer, a large amount of system time can be wasted, in order to save this part system memory access time, by the function interface in the described SystemCWrapper class realized, enable isa simulator DASD thus obtaining instruction and data；Each main device module has an address mapping table, for recording all address spaces from equipment, by described address mapping table determine that main device module to access from the numbering corresponding to EM equipment module。
For realizing in the thread of decoding flow process, the program of one TB block of translation also performs in each loop body；In interrupt thread, wake-up interrupts thread whenever having interruption to arrive, process and interrupt, labelling interrupt flag bit；Upper once decode flow process start time, interrupt if it find that existing, preserve current PC value and status register, jump to interruption offset vector, perform corresponding interrupt service routine, process and interrupt。
Step 2) described in include from the Accurate Model of EM equipment module:
From EM equipment module, depositor is with 32 bit wide formal definitions, and 4 alignment are pressed in address, it is achieved two threads, and a thread is for realizing from EM equipment module basic function, the main basic function described from EM equipment module；One thread sends interruption, it is complete the function required by main equipment from equipment for informing to main device module, it is while (1) loop structure inside each thread, to ensure the continuous service from EM equipment module, is realized from the synchronization between equipment by sleep awakening mechanism。
Step 3) described in design of interruption, it is achieved the interruption system of emulation platform is,
First one readable mark position of design, described flag bit is to open up space, plot location in available address space, is called synchronization global variable；Described synchronization global variable represents with a byte, and 0 represents unreadable, and 1 represents readable, in order to ensure address align, open up 32 the i.e. address space of 4byte, during beginning, described synchronization global variable is set to 0, past from EM equipment module write data afterwards, start and start working from EM equipment module, judge to synchronize whether global variable is set to 1 subsequently into the cycle stage, if synchronizing global variable is 0, show to run from EM equipment module not yet to terminate, then circular wait；If being set to 1, then show that application program continues executing with from EM equipment module end of run；
The interrupt vector address of PowerPC framework is 0x500, in time having interruption to occur, first isa simulator preserves current PC value and status register, then amendment current PC value is 0x500, the instruction obtained when ensureing decoding next time is the instruction of address 0x500, at 0x500 address place by memcopy function, a jump instruction is added on 0x500 address, then branch to the first address of interrupt service routine, perform interrupt service routine；
Described interrupt service routine includes assembly program and c program, in order to ensure the properly functioning of application program, interrupt service routine needs saving scene, interrupt service routine utilizes assembly program saving scene: choose a piece of available address space, all of general register and status register are pressed in described address space, call jump instruction afterwards, make assembly program jump to c program；C program major function is to realize interrupting service, synchronization global variable is set to 1 and carries out interrupt processing, after interrupt processing, jump back to assembly program；Now assembly program restoring scene, general register in press-in address space and status register are popped, after all depositors are popped, call instruction rfi returns PC pointer and status register, application program continues executing with, thus completing the design of the high-level simulation platform based on PowerPCSoC framework。
The Design of Simulation Platform method based on PowerPCSoC framework of the present invention, it is achieved that the collaborative simulation of software and hardware, reduces design risk and cost for correcting error, accelerates the design cycle of product, shorten the market periods of product。Meet the application to the double requirements high-level simulation platform of Department of Electronics's irrespective of size design accuracy and speed of the SoC design field so that user just can carry out co-development and the functional verification of software and hardware under not having real hardware condition。PowerPC framework is as the representative of reduced instruction set computer, and product is also widely used in all trades and professions。Carry out software development at the high-level simulation platform based on PowerPC framework, shorten the construction cycle of the product of PowerPC framework, simultaneously by the function of expansion instruction set and IP module, hardware development is had certain directive significance。
Accompanying drawing explanation
Fig. 1 is the flow chart generating Buffer instruction；
Fig. 2 is the emulation platform framework based on PowerPCSoC framework of the present invention；
Fig. 3 be in the present invention interrupt system call schematic diagram。
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing, the Design of Simulation Platform method based on PowerPCSoC framework of the present invention is described in detail。
The Design of Simulation Platform method based on PowerPCSoC framework of the present invention, the comprehensive advantage based on transaction-level modeling and two kinds of methods of virtual machine technique, utilizes the method for the binary translation of QEMU virtual machine to carry out the design of isa simulator for PowerPC405 series processors。And based on SystemC transaction-level modeling method, complete from EM equipment module, in the PowerPCSoC such as interrupt module, DCR depositor, the Accurate Model of key component, simulates the hardware behavior of SoC exactly。Finally, on designed PowerPCSoC emulation platform basis, the development process of software is devised, it is achieved that the Hardware/Software Collaborative Design of SoC。
The Design of Simulation Platform method based on PowerPCSoC framework of the present invention, comprises the steps:
1) instruction set simulation, adopts the binary translation technology of QEMU virtual machine to carry out instruction set simulation as the isa simulator that PowerPC405 is serial；
Described instruction set simulation is to realize on the basis of PowerPC framework in QEMU, is first added to by all PowerPC instruction set in the instruction catalogue of QEMU, then goes to search the corresponding instruction in QEMU instruction catalogue according to the operation code of PowerPC instruction；Described finger QEMU makes and comprises two parts in table, and Part I is the definition according to instruction operation code, and the numerical value of operation is stored in QEMU instruction catalogue, forms the index of instruction catalogue；Part II is that described function resolves into microoperation command adapted thereto in order to realize the function corresponding to the function of arbitrary instruction。
Described instruction set simulation is as it is shown in figure 1, specifically include:
Create op.c file, and define all of microoperation function, in program compilation process, by op.c file generated microoperation concordance list；Each microoperation function in op.c file simultaneously, capital generates a fixing microoperation eigenvalue functions, microoperation eigenvalue functions is each microoperation one fixing eigenvalue of distribution, define in the gen_op.h file created, PowerPC instruction translation is become multiple microoperation eigenvalue functions by the translate.c file created, and then generate microoperation eigenvalue array, according to microoperation eigenvalue array, search by the microoperation concordance list of op.c file generated, generate TB block instruction Buffer, constitute the isa simulator of PowerPC, thus carrying out instruction set simulation。
2) key component in emulation platform is modeled, based on SystemC transaction-level modeling method, complete main device module and the Accurate Model from key components such as EM equipment modules, design the emulation platform of the PowerPCSoC framework with more complete function；
Described main device module includes SystemCWrapper and isa simulator；The ancillary equipment of platform all inherits one from equipment class, realizes read-write interface from equipment class, receives the request of data that main equipment sends。Described includes from EM equipment module: memorizer, tty display, framebuffer frame buffer picture display module and time clock module。
As in figure 2 it is shown, the described Accurate Model to main device module includes:
SystemCWrapper realizes a class, the described SystemCWrapper class realized provides a function interface ISStomemoryaccess accessing memorizer for isa simulator, main device module realizes two threads, one thread is used for realizing decoding flow process, carries out work decoding according to current PC value；Another one thread is used for realizing interrupt processing function；While (1) loop structure it is, to ensure the continuous service of main device module inside each thread；For realizing in the thread of decoding flow process, the program of one TB block of translation also performs in each loop body；In interrupt thread, wake-up interrupts thread whenever having interruption to arrive, process and interrupt, labelling interrupt flag bit；Upper once decode flow process start time, interrupt if it find that existing, preserve current PC value and status register, jump to interruption offset vector, perform corresponding interrupt service routine, process and interrupt。Main device module needs actively to send read-write requests to from EM equipment module, goes to read accordingly from the data of EM equipment module by bus by read and the write of main device module interface；Instruction fetch needs to access continually memorizer, a large amount of system time can be wasted, in order to save this part system memory access time, by the function interface in the described SystemCWrapper class realized, enable isa simulator DASD thus obtaining instruction and data；Each main device module has an address mapping table, for recording all address spaces from equipment, by described address mapping table determine that main device module to access from the numbering corresponding to EM equipment module。
As in figure 2 it is shown, described includes from the Accurate Model of EM equipment module:
From EM equipment module, depositor is with 32 bit wide formal definitions, and 4 alignment are pressed in address, similar with main equipment, it is achieved two threads, and a thread is for realizing from EM equipment module basic function, the main basic function described from EM equipment module；Such as, in tty module, the major function of this thread be exactly the data-printing that main equipment is write on virtual terminal, and for example framebuffer module, according to the data write, process through complicated data, image be shown in frame buffer one by one。One thread sends interruption, is complete the function required by main equipment for informing to main device module from equipment, waits after realizing entrance sleep from EM equipment module basic function, sends to main device module and interrupts, notifies the processed data of main device module。It is while (1) loop structure inside each thread, to ensure the continuous service from EM equipment module, is realized from the synchronization between equipment by sleep awakening mechanism。
3) design of interruption, it is achieved the interruption system of emulation platform。
As it is shown on figure 3, described design of interruption, it is achieved the interruption system of emulation platform is that first application program initializes synchronization global variable, to equipment transmission data, starting device, terminates subsequently into the operating of blocked state waiting facilities；Equipment has worked and can send interruption to CPU；After CPU carries out interrupt service routine process, application program can continue executing with。
First assurance function is correct, should enter blocked state after application program launching equipment。If application program is unplugged, then be easy to produce mistake, application program is likely to reading data before equipment completes computing。So needing one special readable mark position of design, this flag bit can design one special position of design in the module, it is possible to opens up so space, plot location in available address space。The mode of the former similar poll, the mode of the more similar interruption of the latter, so the method that the present invention adopts the space, location that opens a piece of land, in Fig. 3, this position is referred to as synchronization global variable。Namely first designing a readable mark position, described flag bit is to open up space, plot location in available address space, is called synchronization global variable；
Described synchronization global variable represents with a byte, and 0 represents unreadable, and 1 represents readable, in order to ensure address align, open up 32 the i.e. address space of 4byte, when application program starts, described synchronization global variable is set to 0, past from EM equipment module write data afterwards, start and start working from EM equipment module, judge to synchronize whether global variable is set to 1 subsequently into the cycle stage, if synchronizing global variable is 0, show to run from EM equipment module not yet to terminate, then circular wait；If being set to 1, then show that application program continues executing with from EM equipment module end of run；
The interrupt vector address of PowerPC framework is 0x500, in time having interruption to occur, first isa simulator preserves current PC value and status register, then amendment current PC value is 0x500, the instruction obtained when ensureing decoding next time is the instruction of address 0x500, at 0x500 address place by memcopy function, a jump instruction is added on 0x500 address, then branch to the first address of interrupt service routine, perform interrupt service routine；
Described interrupt service routine includes assembly program and c program, in order to ensure the properly functioning of application program, interrupt service routine needs saving scene, interrupt service routine utilizes assembly program saving scene: choose a piece of available address space, all of general register and status register are pressed in described address space, call jump instruction afterwards, make assembly program jump to c program；C program major function is to realize interrupting service, synchronization global variable is set to 1 and carries out interrupt processing, after interrupt processing, jump back to assembly program；Now assembly program restoring scene, pops the general register in press-in address space and status register, the operation that depositor is accessed by pop down and the operation popped exactly, uses stw (depositing) and lwz (taking) to complete。After all depositors are popped, call instruction rfi returns PC pointer and status register, and application program continues executing with, thus completing the design of emulation platform based on PowerPCSoC framework。
Claims (9)
1. based on the Design of Simulation Platform method of PowerPCSoC framework, it is characterised in that comprise the steps:
1) instruction set simulation, adopts the binary translation technology of QEMU virtual machine to emulate flat isa simulator as PowerPCSoC framework and carries out instruction set simulation；
2) key component in emulation platform is modeled, based on SystemC transaction-level modeling method, complete main device module and the Accurate Model from EM equipment module, design the emulation platform of the PowerPCSoC framework with complete function；
3) design of interruption, it is achieved the interruption system of emulation platform。
2. the Design of Simulation Platform method based on PowerPCSoC framework according to claim 1, it is characterized in that, step 1) described in instruction set simulation be in QEMU on the basis of PowerPC framework realize, first all PowerPC instruction set are added in the instruction catalogue of QEMU, then go to search the corresponding instruction in QEMU instruction catalogue according to the operation code of PowerPC instruction。
3. the Design of Simulation Platform method based on PowerPCSoC framework according to claim 2, it is characterized in that, comprising two parts in described QEMU instruction catalogue, Part I is the definition according to instruction operation code, the numerical value of operation is stored in QEMU instruction catalogue, forms the index of instruction catalogue；Part II is that described function resolves into microoperation command adapted thereto in order to realize the function corresponding to the function of arbitrary instruction。
4. the Design of Simulation Platform method based on PowerPCSoC framework according to claim 1, it is characterised in that step 1) described in instruction set simulation specifically include:
Create op.c file, and define all of microoperation function；Each microoperation function in op.c file, capital generates a fixing microoperation eigenvalue functions, microoperation eigenvalue functions is each microoperation one fixing eigenvalue of distribution, define in the gen_op.h file created, PowerPC instruction translation is become multiple microoperation eigenvalue functions by the translate.c file created, and then generate microoperation eigenvalue array, according to microoperation eigenvalue array, search the microoperation concordance list that op.c file generates, generate TB block instruction Buffer, constitute the isa simulator of PowerPC, thus carrying out instruction set simulation。
5. the Design of Simulation Platform method based on PowerPCSoC framework according to claim 1, it is characterised in that step 2) described in main device module include SystemCWrapper and isa simulator；Described includes from EM equipment module: memorizer, tty display, framebuffer frame buffer picture display module and time clock module。
6. the Design of Simulation Platform method based on PowerPCSoC framework according to claim 1, it is characterised in that step 2) described in the Accurate Model to main device module include:
SystemCWrapper realizes a class, the described SystemCWrapper class realized provides a function interface ISStomemoryaccess accessing memorizer for isa simulator, main device module realizes two threads, one thread is used for realizing decoding flow process, carries out work decoding according to current PC value；Another one thread is used for realizing interrupt processing function；While (1) loop structure it is, to ensure the continuous service of main device module inside each thread；Main device module needs actively to send read-write requests to from EM equipment module, goes to read accordingly from the data of EM equipment module by bus by read and the write of main device module interface；Instruction fetch needs to access continually memorizer, a large amount of system time can be wasted, in order to save this part system memory access time, by the function interface in the described SystemCWrapper class realized, enable isa simulator DASD thus obtaining instruction and data；Each main device module has an address mapping table, for recording all address spaces from equipment, by described address mapping table determine that main device module to access from the numbering corresponding to EM equipment module。
7. the Design of Simulation Platform method based on PowerPCSoC framework according to claim 7, it is characterised in that be used in the thread realizing decoding flow process, in each loop body, the program of one TB block of translation also performs；In interrupt thread, wake-up interrupts thread whenever having interruption to arrive, process and interrupt, labelling interrupt flag bit；Upper once decode flow process start time, interrupt if it find that existing, preserve current PC value and status register, jump to interruption offset vector, perform corresponding interrupt service routine, process and interrupt。
8. the Design of Simulation Platform method based on PowerPCSoC framework according to claim 1, it is characterised in that step 2) described in include from the Accurate Model of EM equipment module:
From EM equipment module, depositor is with 32 bit wide formal definitions, and 4 alignment are pressed in address, it is achieved two threads, and a thread is for realizing from EM equipment module basic function, the main basic function described from EM equipment module；One thread sends interruption, it is complete the function required by main equipment from equipment for informing to main device module, it is while (1) loop structure inside each thread, to ensure the continuous service from EM equipment module, is realized from the synchronization between equipment by sleep awakening mechanism。
9. the Design of Simulation Platform method based on PowerPCSoC framework according to claim 1, it is characterised in that step 3) described in design of interruption, it is achieved the interruption system of emulation platform is,
First one readable mark position of design, described flag bit is to open up space, plot location in available address space, is called synchronization global variable；Described synchronization global variable represents with a byte, and 0 represents unreadable, and 1 represents readable, in order to ensure address align, open up 32 the i.e. address space of 4byte, during beginning, described synchronization global variable is set to 0, past from EM equipment module write data afterwards, start and start working from EM equipment module, judge to synchronize whether global variable is set to 1 subsequently into the cycle stage, if synchronizing global variable is 0, show to run from EM equipment module not yet to terminate, then circular wait；If being set to 1, then show that application program continues executing with from EM equipment module end of run；
The interrupt vector address of PowerPC framework is 0x500, in time having interruption to occur, first isa simulator preserves current PC value and status register, then amendment current PC value is 0x500, the instruction obtained when ensureing decoding next time is the instruction of address 0x500, at 0x500 address place by memcopy function, a jump instruction is added on 0x500 address, then branch to the first address of interrupt service routine, perform interrupt service routine；
Described interrupt service routine includes assembly program and c program, in order to ensure the properly functioning of application program, interrupt service routine needs saving scene, interrupt service routine utilizes assembly program saving scene: choose a piece of available address space, all of general register and status register are pressed in described address space, call jump instruction afterwards, make assembly program jump to c program；C program major function is to realize interrupting service, synchronization global variable is set to 1 and carries out interrupt processing, after interrupt processing, jump back to assembly program；Now assembly program restoring scene, general register in press-in address space and status register are popped, after all depositors are popped, call instruction rfi returns PC pointer and status register, application program continues executing with, thus completing the design of the high-level simulation platform based on PowerPCSoC framework。
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