JP2003067438A - Method for generating simulation model, method of simulation and its recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a simulation of an intermediate level between an algorithm description and an RT level description, and provide its language. SOLUTION: The algorithm description 3 is lowered to a clock level description 8 under limited resources. A plurality of functions in the algorithm description 3 are decomposed into partial functions which can operate in a unit clock and the partial functions are assembled to restore the plurality of functions. The plurality of functions are described in a language in which a register is a variable as a clock level simulator 8 that is a clock level description. The language in which the register is a variable is the most suitable as a programming language operative in a clock unit. The language has been an undiscovered language which was located in a lower position than the algorithm level and in a higher position than the RT level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation method, a simulation model, a recording medium corresponding to them, and a method of generating their descriptions. In particular, the simulation is appropriately switched between algorithm description and RT level description. The present invention relates to a simulation method for generating a simulation model at a desired stage at high speed to simulate an algorithm at high speed or in detail, a simulation model, a recording medium corresponding to the simulation model, and a method for generating their descriptions.

[0002]

2. Description of the Related Art Large-scale circuits are designed by automatic design equipment. The design flow of the automatic design apparatus uses a general-purpose programming language such as C, a highest-level description in which a desired behavior flow is described in a dedicated behavior level description language, using hardware resources such as registers and adders. It has the step of writing down to a lower level description such as an RT level description which is made more hardware. As shown in FIGS. 13 (a) and 13 (b), the behavioral level simulation model 101 having a high degree of abstraction is the only simulation performed from the beginning to the end, as shown in FIGS. 13 (a) and 13 (b). The RT level simulation model 102 cannot be simulated in the middle of the simulation, and in the RT level simulation model 102 having a low abstraction level, only this is simulated from the beginning to the end. The simulation of the behavioral level simulation model 101 was not performed.

As described above, the behavior level simulation model 101 and the RT level simulation model 10
2 was treated as being independent of each other and different, and it was impossible to switch from one system simulation to the other system simulation during the simulation. In general, high-speed simulation models are used in situations where speed is important, RT levels are used in situations where accuracy is important, and other low-level simulation models with lower levels are used in situations where more precision is required. Was used.

However, when performing a simulation for functional verification, there is a demand for a particularly detailed examination between a certain time t1 and another certain time t2. Even in such a case, if a highly accurate simulator is used for the verification from time t0 to time t2, it takes a lot of time for the function inspection.

As a technique for solving such a problem, a mixed simulation technique for switching between a plurality of simulation models having different degrees of abstraction is disclosed in Japanese Patent Laid-Open No. 5-61934, "Parallel Logic Simulator WIZDOM". (57th National Convention of Information Processing Society,
1998). The switching disclosed here is switching between an instruction level simulation model and a simulation model such as a hardware simulator or an RT level simulation model having different degrees of abstraction. The reason why such switching is possible is that both models have a common structure in registers and the like. Further, a technique for performing simulation switching between a gate level and an electronic circuit level is known from Japanese Patent Laid-Open No. 7-110826. This switching enables transfer of both information by utilizing the one-to-one correspondence between the terminals of the gate circuit and the terminals of the electronic circuit.
This is done by digital conversion. In addition, JP-A-10
-261002 discloses the movement of the circuit by using a certain circuit description format with a detailed definition model and a rough definition model, and discloses switching between the models. Such switching between high and low levels having a one-to-one correspondence and switching between the same levels using a common description format with different levels of detail are known.

However, the highest programming language description level called behavior description level and the lower description level R
Between the T levels, the structure for holding the simulation state does not correspond one-to-one, and data cannot be transferred between the two levels, so switching simulation between these levels has been conventionally impossible. In order to more appropriately speed up and detail the simulation, it has been particularly desired to establish a technique for switching the simulation model between the levels for which the one-to-one correspondence is not described.

In order to establish such a technique, the present inventor converts a behavioral level description describing a processing flow of a logic circuit into an RT level description by a function synthesizing tool, and converts the behavioral level description and the RT level description. Input to the corresponding compiler to generate the behavior level simulation model structure and the RT level simulation model structure, generate the corresponding means of the behavior level simulation model structure and the RT level simulation model structure, and determine the behavior level simulation model structure and the RT level. A simulation method has been proposed in which the variable value of the register is shared between both levels so that the behavior level simulation and the RT level simulation are switched and executed through corresponding means based on the simulation model structure (see : Japanese Patent Application No. 11-057040
issue).

In the process of executing the simulation by such a simulation method, the present inventor has found that the conventional RT level description automatically generated from the algorithm description having the highest abstraction which is the behavior model is the algorithm description which is the source. Far from, I noticed that there was a large difference in abstraction between the two descriptions. It is desirable to find a description with an abstraction level that is hidden between the two descriptions and that is between the abstraction levels of the two descriptions, and by that description, a simulation model at a language level that has a lower abstraction level than the algorithm description and a higher abstraction level than the RT level. Is desired to be more precise than the operation level and faster than the RT level.

[0009]

An object of the present invention is to provide a simulation model based on a language having a higher abstraction level than the algorithm level and a lower abstraction level than the RT level, a description thereof, and a generation method thereof. To do.

Another object of the present invention is that, based on a description having a higher abstraction level than the algorithm level and a lower abstraction level than the RT level, the simulation is more precise than the simulation of the algorithm description and is more precise than the simulation of the RT level description. It is to provide a simulation model that can be simulated at a higher speed, a description thereof, and a method of generating the simulation model.

[0011]

According to the simulation model generation method of the present invention, in a simulation apparatus including a function synthesizing unit and a clock level verifying unit, the function synthesizing unit is controlled by a circuit module under the constraint of resources. A state transition control model and a correspondence table are generated from the algorithm description expressing the above, and the clock level verification unit generates a clock level algorithm model of the clock level description from the state transition control model and the correspondence table. The clock level description describes the operation of each of the resources at a unit clock, the clock level algorithm model is the clock level description of the circuit module, and the state transition control model is the state of each of the resources. The transition table is controlled, and the correspondence table represents the correspondence relation between the resource and the variable in the algorithm description for each unit clock and the resource.

The clock level algorithm model has a data path description unit for controlling the operation of the resource for each unit clock.

Further, according to the simulation model generating method of the present invention, in the simulation apparatus having the function synthesizing unit and the clock level verifying unit, the function synthesizing unit is an algorithm for expressing the circuit module under the constraint of resources. Even if the state transition control model and the correspondence table are generated from the description, and the clock level verification unit generates the clock level algorithm model of the clock level description from the state transition control model, the correspondence table, and interface information with the outside. Good. The clock level description describes the operation of each of the resources at a unit clock, the clock level algorithm model is the clock level description of the circuit module, and the state transition control model is the state of each of the resources. The transition table is controlled, and the correspondence table represents the correspondence relation between the resource and the variable in the algorithm description for each unit clock and the resource.

The clock level algorithm model may include an I / O unit for inputting / outputting data and a data path description unit for controlling the operation of the resource for each unit clock.

In any case, in the clock level description, one of the resources is preferably shared by the plurality of variables.

In the simulation method of the present invention, the clock level verification unit may simulate a simulation model including the clock level algorithm model according to any one of claims 1 to 5 based on the unit clock. Good. At this time, the simulation model may include a clock level CPU model corresponding to the operation of the CPU.

Further, the clock level verification unit associates the state of the resource with the algorithm description based on the result of the simulation, and displays the usage status of the resource for each description line of the algorithm description. It is preferable. Further, the clock level verification unit uses the clock level description included in the simulation model and a resource use correspondence table indicating a use state of the resource to associate the algorithm description with a variable value obtained by the simulation. Is preferably displayed.

In the display of the use status of the resource, the clock level verifying unit causes the description line of the algorithm description in which the state transition has occurred and the resource when the state transition of the unit clock of the clock level description occurs. Of the register value in which the state transition has occurred when the state transition of the unit clock of the clock level description occurs, in the corresponding display of the variable value. It is preferable to display the rows and the variable values. The variable value is a register or memory value of the resource.

In the simulation apparatus of the present invention, under the constraint of resources, a function synthesizing section for generating a state transition control model and a correspondence table from an algorithm description expressing a circuit module, the state transition control model, the correspondence table, And a clock level verification unit that generates a clock level algorithm model of a clock level description from interface information with the outside. The state transition control model controls the state transition of each of the resources, the correspondence table represents the correspondence relation between the resources and the variables in the algorithm description for each unit clock, and the clock level description. Describes the operation of each of the resources at the unit clock, and the clock level algorithm model is the clock level description of the circuit module.

The simulation device may further include a display unit, and the clock level verification unit associates the state of the resource with the algorithm description based on the result of the simulation, The use status of the resource for each description line is displayed on the display unit, and the description line of the algorithm description and the simulation are performed by using the clock level description and the resource use correspondence table included in the clock level simulation model. The correspondence of the variable value obtained by is displayed on the display unit. The clock level verification unit displays, on the display unit, the description line of the algorithm description in which the state transition has occurred and the usage status of the resource when the state transition of the clock level description in the clock unit occurs. When the state transition of the clock unit of the clock level description occurs, it is preferable to display the description line of the register description in which the state transition occurred and the variable value.

Further, in the simulation apparatus, an algorithm level verification unit for simulating an algorithm level simulation model of the circuit, which includes a hardware model representing a logical operation of the circuit, and the hardware model generated from the hardware model under resource constraints. A clock level verification unit for simulating a clock level simulation model including a clock level algorithm model, and the clock level algorithm model represents an operation of each of the resources at a unit clock, and the hardware is controlled under the constraint of the resources. R containing the RT level algorithmic model of the circuit generated from the model
And an RT level verification unit for simulating the T level simulation model.

The algorithm level simulation model includes a CPU model representing the operation of the CPU in the circuit, the clock level simulation model includes a clock level CPU model representing the operation of the CPU for each unit clock, and the RT The level simulation model may include an RT level CPU model that represents the operation of the CPU at the RT level. The simulation time of the clock level simulation model is shorter than the simulation time of the RT level simulation model. The simulation device further includes a display unit, and the clock level verification unit associates the state of the resource with the algorithm description based on a simulation result of the clock level algorithm model and the clock level CPU model. The use status of the resource for each description line of the algorithm description is displayed on the display unit, and the resource use correspondence table showing the use status of the resource is used to obtain the description line of the algorithm description and the simulation result. Correspondence of the variable values to be displayed is displayed on the display unit.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A simulation model description generation method according to the present invention includes lowering an algorithm description (3) to a clock level description (8) under the constraint of resources. Comprises breaking down a plurality of functions of the algorithm description (3) into partial functions capable of operating in a unit clock, and assembling the partial functions to recover the plurality of functions. Such a plurality of functions are expressed as a clock level simulator (8) that is a clock level description in a language whose variables are registers described later. The language that uses registers as variables is a low-level programming description language discovered by the present inventor.

The clock level description includes a description that causes one register of the plurality of registers of the resource to operate in different plurality of unit clocks. The registers are shared between such clocks, and the registers are verbalized as variables.

The simulation model according to the present invention is
Furthermore, the clock level description (8) described by the above-described simulation model description generation method.
And a correspondence table (22, 23) corresponding to the algorithm description (3) corresponding to the clock level description.

The simulation method according to the present invention includes simulating a plurality of functions by operating a partial function with a unit clock by using such a simulation model, and further, as a result of such simulation. On the basis of this, it includes debugging the algorithm description (3). Furthermore, by using the clock level description and the correspondence table included in the simulation model,
It includes displaying the correspondence between the number of lines in the algorithm description and the variable value obtained by simulation.

The simulation model generation method according to the present invention is such that the algorithm description (3) is performed under the constraint of resources.
To lower the clock level description (8),
The lowering comprises disassembling the plural functions of the algorithm description (3) into partial functions capable of operating in a unit clock, and assembling the partial functions to recover the plural functions. , Clock level description (8) is one of the multiple registers of the resource
A description is provided for operating two registers for different clocks respectively, and further, a clock level description (8) and a register (Reg1 of the clock level description (8)
Correspondence table (22,23) with register description about (5)
Of the clock level description (8), and if the state transition of the clock level description (8) in clock units occurs, the algorithm description part in which the state transition occurred is displayed. If it occurs, the register in the register description part (Reg
1 to 5) displaying the variable value (R). By creating such a correspondence table, it is possible to make a transition between both levels. It goes without saying that all the descriptions included in such a simulation model generation method can be read by a computer, which is used as a recording medium.

The simulation model according to the present invention is
Algorithm description (3), RT level description (17) having a lower abstraction level than algorithm description (3), and lower abstraction level than algorithm description (3) and more abstraction level than RT level description (17) Includes a high clock level description (8), and the clock level description (8) is a description automatically generated in clock units from the algorithm description (3). The algorithm description (3), the clock level description (8), The RT level description (17) is the register (Reg1) described in the clock level description (8).
Share the variable value (R) of ~ 5). Such sharing allows a transition between the three levels.

Further, the simulation model includes an algorithm description (3) and a clock level description (8) having a degree of abstraction lower than that of the algorithm description (3), and the clock level description (8) is a unit orthogonal to the time axis. It is a calculation description of a register described on a cross section for each clock. Here, the cross section is a chain of a series of descriptions in which operations simultaneously proceed within one unit clock. A language having a lower level of abstraction than the algorithm description and describing a register on a cross section for each unit clock orthogonal to the time axis can be expressed in a computer-readable form and can be made into a recording medium. By copying such a medium, various simulations can be performed simultaneously in parallel. The description language for the simulation model, which has a lower abstraction level than the algorithm description and is described for the register on the cross section for each unit clock orthogonal to the time axis, is Reg1.
A plurality of registers are multi-variable as a term like + Reg2. When the algorithm description (3) includes a numerical operation, the variable of the function that executes the operation in the unit of the clock that progresses on the time axis is expressed as a register.

As described above, in the intermediate level abstraction language, there are latent variables in which the operation of the register appears in clock units.

Corresponding to FIG. 1, the embodiment of the simulation model according to the present invention is characterized in that a clock level verification unit is newly provided between the algorithm verification unit and the RT level verification unit. There is. The algorithm verification unit 1 is formed of an algorithm system 2 as shown in FIG. The algorithm system 2 includes an algorithm description 3 which is an H / W model having the highest degree of abstraction and a C-program 4 which is an S / W model described in C language. The algorithm system 2 is converted into the algorithm simulator 5 by the C-compiler. The algorithm system 2 is simulated by the algorithm simulator 5.

The clock level verification unit 6 is formed of a clock level system 7. The clock level system 7 includes a clock level simulation model 8 that is a clock level description and a clock level CPU.
Model 9 and. Clock level system 7
Is automatically generated by the built-in C compiler 11 and its description is converted. For the description conversion, the conventional function synthesizing tool 1 is used.
A register, which is a tool of 2, is used as a term (word or primary variable). The algorithm description 3 is generated by the model conversion tool 13 having a tool described by the function synthesis tool 12 and the clock level simulation model 8
The description is converted to. The clock level CPU model 9
It is automatically generated from the C-program 4 by the built-in C compiler 11. The clock-based simulator 14 is composed of a clock level simulation model 8 and a clock level CPU model 9.

The RT level verification section 15 is formed of an RT level system 16. The RT level system 16 includes an RTL-HDL 17 and an RT level CPU model 18. The RTL-HDL 17 is automatically generated from the algorithm description 3 by the function synthesis tool 12. The HDL simulator 19 uses the RTL-HDL17.
And the RT level CPU model 18 are formed.

FIG. 2 shows a tool configuration for model generation for automatically generating the clock level simulation model 8 and its generation flow. The function synthesis tool 12 includes a constant and variable optimization function, a scheduling function, an allocation function, a register sharing function, and an H function.
It has a DL generation function. The register sharing function has the function of executing the following three generations: (1) FSM / controls the repetition of state transitions of multiple register resources used under resource constraints by data path control.
Creation of DataPath model 21 (2) Variable which is correspondence between variable, register and state position /
Creation of Register / State Position Correspondence Table 22 (3) Creation of Source Line / State Position Correspondence Table 23 which is a Correspondence between Source Line of Algorithm Description and Its State Position Model I / F information 24 is the function synthesis tool 12 and the model. It is input to the conversion tool 13. Model conversion tool 13
Is the model I / F information 24 and FSM / DataPath.
It operates based on the model 21 and the variable / register / state position correspondence table 22, and converts the algorithm description 3 into the clock level simulation model 8 to automatically generate the clock level simulation model 8. The model conversion tool 13 includes a debug function library 25 of the model function library and a model I for automatic generation.
The library information is input from the / F library 26.

FIG. 3 shows a description structure of the clock level simulation model 8. The clock level simulation model 8 includes a Bus simulation model 31. Bus simulation model 3
1 is composed of a module IO unit 32 and a data path description unit 33. An IO register structure in which a plurality of IO registers 34 and a plurality of IO memories 35 are described in the module IO unit 32, is created from the model I / F information 24, and is read and written by embedded software through the input / output terminals of the simulation model. And has an IO memory structure. The clock level simulation model 8 communicates with other modules via the module IO unit. As will be described later, the data path description unit 33 has a data path that describes the relationship between a plurality of IO registers and a plurality of operators, and a control structure that controls the operation of the operation in clock units.

A simulation controller 36 is connected to the data path description section 33. The simulation controller 36 receives the clock input 37 from the simulator body and performs the cyclic step control (FSM control) of the arithmetic operation transition 38 that advances the clock of the data path description unit 33 one by one. The FSM control signal 39 output from the simulation controller 36 is the data path description unit 33.
Entered in.

The data path description section 33 is connected to the GUI controller 41. The data path description unit 33 outputs the register value R and the state position value S which is the operation transition position. The register value R and the state position value S are input to the GUI controller 41. When the reset signal is input to the simulation controller 36, the register value R and the state position value S of the data path description unit 33 are initialized.

The GUI controller 41 can obtain the correspondence between the register of the current transition state position and the variable according to the algorithm level description from the variable / register / state position correspondence table 22 shown in FIG. GUI controller 4
In addition, 1 can obtain the source line according to the algorithm level description of the current transition state position from the source line / state position correspondence table 23.

The GUI controller 41 is connected to the algorithm level description variable value display window 42 and the algorithm level description source execution line display window 43. Algorithm level description variable value display window 4
In FIG. 2, the register value R of the register is displayed at the transition state position by giving the correspondence relationship based on the variable / register / state position correspondence table 22 as the algorithm level description variable value. The value of the algorithm-level description variable, which temporarily loses its correspondence with the register because a plurality of registers are partially shared between different transition states, is the GUI.
By being held by the controller 41, the latest variable value of the latest transition state is always displayed in the algorithm level description variable value display window 42.

On the other hand, the source line position value S of the algorithm level description corresponding to the current state transition position is displayed in the algorithm level description source execution line display window 43.
Source row / state position correspondence table 23 at the current transition state position
The corresponding relationship based on is given and highlighted. Furthermore, the GUI controller 41 uses the algorithm description variables, registers, and the number of changes in clock units,
The number of transitions to each state of the state transition, transition source, transition destination,
By being measured during the simulation, the coverage of variables, register changes, and state changes is measured. Such coverage rate is an index of how comprehensively the verification can be performed by the test pattern.

Algorithm verification: Both the hardware model and the software model included in the system are described in a programming language. The hardware model represents the algorithm of the hardware, and the software model represents the embedded software. An algorithm-level simulator is created by applying these programming language descriptions to a C compiler. Items that can be verified at the algorithm level without information about hardware are listed in (1) and (2) below.
As shown in, only purely logical behavior,
The simulation is very fast. (1) Verification of logical operation of each module (2) Verification of logical operation of system

Clock level verification: A clock level simulation model is created by processing the algorithm description of the hardware model with a function synthesis tool and a model conversion tool. Software model is C
It is read as embedded software on the PU simulation model and realizes the operation timing equivalent to that of the actual CPU. Since these hardware and software models have the same timing accuracy as the actual LSI system at the clock level, it is possible to estimate and verify the following items by performing simulation on a clock level simulator. . (1) Clock level operation timing verification of each module (2) Schematic verification of interface of each module (I
O register, IO memory, IO terminal configuration, name, bit width, etc.) (3) Frequency estimation of operating clock of each module and bus (4) Cache access estimation (cache hit rate, access rate, number of writebacks, etc.) (5) Estimate of access (bus occupancy rate, Adrs, Data, Master for each bus transaction)
r, Slave, Read / Write, Command
(6) Bus / Arbiter algorithm verification (7) Memory / IF traffic estimation (8) Throughput estimation of data processing (each module, each bus, entire system) (9) ) Estimate of buffer and stack size (10) Estimate of image quality and sound quality (11) Verification of consistency of inter-module connection I / F such as address map, terminal, bit width (12) When floating point is converted to fixed point Estimate (13) Development and debugging of embedded software (14) Rough estimate of power consumption

RT level verification: As the hardware model, the RTL-HDL model created by the function synthesis tool is used. This model has timing accuracy that includes asynchronous behavior in more detail than clock levels. The software model uses C as well as clock level simulation.
It is loaded as embedded software on the PU simulation model. By simulating these RTL-HDL model and CPU model on an HDL simulator, the following items can be verified and estimated. (1) Detailed verification of interface of each module (timing operation of control, address, data terminals) (2) Verification of detailed timing of each module (3) Detailed estimation of power consumption (4) Creation of pattern for tester

[0044]

EXAMPLE FIG. 10 shows an embodiment of a simulation model creating method according to the present invention. According to the flow chart shown in FIG. 10, the FSM / DataPath model description described later from the algorithm description shown in FIG. 4, the variable / register / state position correspondence table shown in FIG. 8, and the source line / state position shown in FIG. The method of creating the correspondence table and the clock level simulation model will be described below.

FIG. 4 shows algorithm description 3 (see FIG. 2).
Is illustrated. The function synthesizing tool 12 receives the algorithm description and the constraint conditions of the resources forming the circuit. The resource constraints in this case are as follows. Register: 5 adders: 1 variable In the algorithm description shown in FIG. 4, variables are a, b,
Five of c, d, and X are included, and three are included in addition. Since only one adder can be used at the same time due to the resource constraint condition, the arithmetic processing is time-divided, as shown in FIG. In Clock 1 of FIG. 5, a and b are added, and the result is substituted for X. In Clock2, in Clock1
Using the same adder as above, c and d are added, and a variable t2 is newly created and substituted in order to temporarily hold the addition result. Furthermore, in Clock3, Clock1,
The same adder as 2 is used to add X and t2, and the addition result is substituted for X. Such processing is referred to as arithmetic unit scheduling (step S2).

In order to implement the processing shown in the algorithm description of FIG. 4 under the constraint of one adder by the scheduling of the arithmetic unit, 3 clocks are required, and the variables a, b,
It can be seen that 6 pieces of c, d, X and t2 are required. According to the resource restriction on registers, the number of registers that can be used at the same time is limited to 5, so it is necessary to share the registers. In register sharing, first use Cl
variables a and b of ock1 and variables X and c of Clock2
Reg1 to Reg5 permitted by the register constraint are assigned to d. For the variable t2 of Clock3, R
It is necessary to reuse one of eg1 to Reg5. R assigned to variables a and b in Clock1
If the X of Clock2 is obtained for eg1 and Reg2,
Since it is not necessary to hold the contents, it is possible to reuse it after Clock2. Here, Clo
Reg2 is used to assign it to the variable t2 of ck3. Similarly for the last calculation result variable X, Cl
Reg5 that can be reused after ock3 is assigned. The registers are shared under the register constraint thus given (step S3). A model obtained as a result of performing the processing of step S1, step S2, and step S3 in the algorithm description of FIG. 4 is described below in a programming language.
It becomes the h model.

FIG. 8 shows a variable / register / state position correspondence table 22. Variable / register / state position correspondence table 2
2 is created from the correspondence between the variables shown in FIG. 5 and the Clock, and the correspondence between the registers and the clock shown in FIG. Clock1 or Clock3 in FIGS. 5 and 6
Corresponds to states 1 to 3 in FIG. In the state 1 of FIG. 8, that is, Clock 1 of FIGS. 5 and 6, the register Reg1 has the value of the variable a and the register Reg2 has the value of the variable b.
In the state 2, the register Reg3 has the variable X and the register Re
g4 has a value of c, and register Reg5 has a value of d. In the state 3, the register Reg2 is t2, the register Reg3 is X,
In state 4, register Reg5 has the value of X. Furthermore,
As the initial state, a state 0 in which variables are not assigned to all registers is created. Thus each state (ie Cloc
The correspondence between variables and registers in k) is shown as variables /
It is a register / state position correspondence table 22 (step S
5).

FIG. 9 shows the source row / state position correspondence table 23. The addition of the variables a and b in Clock1 corresponds to the third line in the algorithm description of FIG. Cl
The addition of the variables c and d in ock2 corresponds to the fourth line in the algorithm description of FIG. The addition of the variable X and t2 in Clock3 also corresponds to the fourth line. Final calculation result X
The state where is obtained corresponds to the fifth line of the algorithm description in FIG. As in FIG. 8, the states 1 to 3 in FIG.
Corresponding to Clocks 1 to 3. The source line / state position correspondence table 23 shows the correspondence between the line positions and the states in the algorithm description thus obtained. The model conversion tool 13 includes model I / F information 24 and FSM / Da.
The clock level simulation model 8 is created from the taPath model 21, the variable / register / state position correspondence table 22, and the source line / state position correspondence table 23 (step S7). Here, the model I / F information 24 has information that defines an interface between the circuit module represented by the algorithm description 3 and the outside. The contents include a command register and a status register accessible from the bus, a configuration of a data memory, a bit width of a data transfer path with another module, a synchronization method, and the like.

RT of known and conventional RT level system 16
The L-HDL 17 is automatically generated by the function synthesizing tool 12, as shown in FIG. 7. The hardware configuration thus automatically generated by the known tool is composed of five registers 1-5, seven multiplexers 1-7, and five switches SW1-5. Such a hardware model, which has a lower abstraction level than the clock level description model, requires a feedback function and a multiplexer for feeding back the output of the register to the data input in order to hold the value of the register. Requires a clock control for always supplying a clock signal to each of them, and a control signal 44 for controlling each multiplexer, and further selects one register from a plurality of registers to be inputs for sharing the arithmetic unit. For this reason, a multiplexer is needed. The hardware model is
As will be described later, various other various hardware components and control signal lines for controlling them are required.

Clock level simulation model 8
The following is a clock level description, which is a logic level description language as a language that operates in clock units. int DataPath (int a, b, c, d, rest) {static int FSM position; static int Reg1, Reg2, Reg3, Reg4, Reg5; if (rest = = 1) {FSM position = 0; return (0); } switch (FSM position) {case 0: Reg1 = a; Reg2 = b; Reg3 = Reg1 + Reg2; FSM position = 1; break; case 1: Reg4 = c; Reg5 = d; Reg2 = Reg4 + Reg5; FSM position = 2; break; case 2: Reg5 = a; Reg3 + Reg2; FSM position = 3; break; case3: X = Reg5; FSM position = 0; break; Case1 matches the step of clock 1 and Case
2 corresponds to the step of clock 2 and Case 3 corresponds to the step of clock 3. In this way, the clock level description to be used is generated by dividing the registers 1 to 5 for each clock. This clock level description has a more detailed expression than the expression by the algorithm description shown in FIG. 4, but is simplified in view of the RT level description described later. Depending on the content of the algorithm, the simulation time of the algorithm description is about 1/500 of the simulation time of the clock level description, and the operation time of the clock level description is about 500 compared to the operation time of the RT level description.
It has been confirmed by the present inventor that it is one-tenth.

The VHDL description corresponding to FIG. 7 is described below for reference. RT hardware description 1:

[0052]

[Equation 1] RT hardware description 2:

[0053]

[Equation 2] RT hardware description 3:

[0054]

[Equation 3] RT hardware description 4:

[0055]

[Equation 4] RT hardware description 5:

[0056]

[Equation 5] RT hardware description 6:

[0057]

[Equation 6] RT hardware description 7:

[0058]

[Equation 7] RT hardware description 8:

[0059]

[Equation 8] RT hardware description 9:

[0060]

[Equation 9] RT hardware description 10:

[0061]

[Equation 10] RT hardware description 11:

[0062]

[Equation 11] RT hardware description 12:

[0063]

[Equation 12] RT hardware description 13:

[0064]

[Equation 13] RT hardware description 14:

[0065]

[Equation 14] Such a description does not include a description regarding the controller. The first 6 lines of the RT hardware description 14 are the description part regarding the FF register, the next 6 lines are the description part regarding the multiplexer, and the next description is the description part regarding the addition by adder.
The bisections of both levels of description generally correspond to the length of time it takes for both levels of simulation.

FIG. 11 shows a method of displaying the algorithm description source in the algorithm level description source execution line display window 43. Each time a state transition occurs (step S11), the GUI control unit 41 inquires of the FSM / DataPath unit 33 about the current state position (step S12). For example, when the current state position is the state 2, from the source line / state position correspondence table 23, the corresponding source file is file1. It can be seen that the number of lines is the fourth line in c (step S13). Display the source file thus obtained on the GUI,
Further, the user can indicate the current execution position on the algorithm level description by highlighting the line corresponding to the current state position (step S1).
4).

FIG. 12 shows a method of displaying the variables in the algorithm description in the algorithm level description variable value display window 42. Each time a state transition occurs (step S21), the GUI control unit 41 inquires the FSM / DataPath unit 33 about the current state position (step S22). For example, the current state position is state 3
If it is, it can be seen from the variable / register / state position correspondence table 22 that the variables used in state 3 are t2 and X, and the corresponding registers are Reg2 and Reg3, respectively (step S23). GUI controller section 41
Sets the values of Reg2 and Reg3 to FSM / DataPat
Obtained from the h portion 33 and opened. The values of t2 and X are displayed in the algorithm description variable display window 42 (step S24). As a result, the user can observe the change in the register value in the clock level simulation model as the change in the variable value on the algorithm level description on the GUI even if the register is shared.

Compared with the RTL-HDL model having the structure shown in FIG. 7, the clock level simulation model is
The following simulation is omitted. (1) The RTL-HDL model requires a feedback and a multiplexer for holding a register value and outputting it, but in the clock level simulation model realized by a programming language, substitution does not occur for holding a variable value. To the extent no feedback and multiplexers are needed. (2) In the RTL-HDL model, since the clock signal is always supplied to all the registers, the register value is always updated to the new data input value or the value held by the register. Since only the variables that have new data input are updated in the model, the simulation can be sped up without unnecessary update processing. (3) In the RTL-HDL model, since the arithmetic unit is shared, a multiplexer for selecting one register from a plurality of input registers is required. However, the clock level simulation model has no limitation on the arithmetic unit. Such sharing is unnecessary, and a multiplexer for selecting the input of the arithmetic unit is unnecessary. (4) Since the clock level simulation model does not require a multiplexer for sharing a computing unit, a circuit for creating a control input, which is required for the multiplexer, is not required. (5) In the RTL-HDL model, all registers are provided with an asynchronous reset signal, but the clock level simulation model handles only the operation in units of clock cycles, so that it is not necessary to perform the asynchronous operation. (6) The RTL-HDL model has a structure that uses submodules such as registers, multiplexers, and arithmetic units, and the submodules have terminals, and also have signal lines, control mechanisms, etc. inside. In the clock level simulation model, the register is expressed as a variable in the programming language, the multiplexer is expressed as a conditional statement, and the arithmetic unit is expressed as an operator, so that the simulation process is greatly simplified. (7) The RTL-HDL model uses the ascending / descending order of the bit positions of the bundle line according to the actual hardware, the presence or absence of a sign, the distinction of signal types such as integer type / bit vector type, or conversion between these. It needs to be expressed exactly, but such a distinction is not made strictly in the clock level simulation model. (8) Although the parallelism of the operation between the sub-modules in the RTL-HDL model is rigorously expressed, the clock level simulation model does not perform the verification based on the strict operation timing difference of each sub-module. Therefore, it is not necessary to express parallelism exactly. (9) The RTL-HDL model strictly represents, for example, the operation at the time when the reset signal changes in addition to the clock change timing. However, since the clock level simulation model handles only the operation in clock units, the asynchronous operation is performed. Can be simplified.

[0069]

The simulation model according to the present invention,
The description and the generation method thereof enable intermediate level simulation by discovering a language having a level of abstraction lower than that of the algorithm level and higher than that of the RT level. Based on the description having a lower abstraction level than the algorithm level and a higher abstraction level than the RT level, it is possible to perform simulation more finely than the simulation of the algorithm description and faster than the simulation of the RT level description. In general, it is possible to create a programming language that uses hardware components as variables by logicalizing a simulation language for hard components that is more physical and is described in more detail. Can create languages.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of a logic simulation system according to the present invention.

FIG. 2 is a block flow diagram showing an embodiment of a simulation model generation method according to the present invention.

FIG. 3 is a logical block diagram showing the correspondence for a transition between two levels.

FIG. 4 is a logical expression showing an example of an algorithm description.

FIG. 5 is an operation time table showing clock level scheduling.

FIG. 6 is an operation time table showing an operation of a clock level register.

FIG. 7 is a circuit diagram showing a known hardware description.

FIG. 8 is a table showing the correspondence between the number of state transition positions and register variable values.

FIG. 9 is a table showing the correspondence between the number of state transition positions and source lines.

FIG. 10 is a flowchart showing an embodiment of the operation of the logic simulation method according to the present invention.

FIG. 11 is a flowchart showing another operation of the logic simulation method according to the present invention.

FIG. 12 is a flowchart showing still another operation of the logic simulation method according to the present invention.

FIG. 13 is a system flow diagram showing a known logic simulation method.

[Explanation of symbols]

3 ... Algorithm description 8 ... Clock level description (clock level simulation model) 22, 23 ... Correspondence table 22 ... Variable / register / state position correspondence table 23 ... Source line / state position correspondence table 17 ... RT level description R ... Variable value Reg1 ~ 5 ... Register

Claims (20)

[Claims] 1. In a simulation device comprising a function synthesizing section and a clock level verifying section, the function synthesizing section creates a state transition control model and a correspondence table from an algorithm description expressing a circuit module under resource constraints. And a step of generating a clock level algorithm model of a clock level description from the state transition control model and the correspondence table, the clock level verification unit comprising: The clock level algorithm model is the clock level description of the circuit module, the state transition control model controls the state transition of each of the resources, and the correspondence table is the resource ,
And a method of generating a simulation model representing a correspondence relationship between a variable in the algorithm description and the resource for each unit clock. 2. The simulation model generation method according to claim 1, wherein the clock level algorithm model includes a data path description unit that controls the operation of the resource for each unit clock. 3. A simulation apparatus comprising a function synthesizing section and a clock level verifying section, wherein the function synthesizing section creates a state transition control model and a correspondence table from an algorithm description representing a circuit module under resource constraints. And a step of causing the clock level verification unit to generate a clock level algorithm model of a clock level description from the state transition control model, the correspondence table, and interface information with the outside. Describing the operation of each of the resources at a unit clock, the clock level algorithm model being the clock level description of the circuit module, the state transition control model controlling state transitions of each of the resources, The correspondence table includes the resources,
And a method of generating a simulation model representing a correspondence relationship between a variable in the algorithm description and the resource for each unit clock. 4. The simulation model according to claim 3, wherein the clock level algorithm model has an I / O unit for inputting and outputting data and a data path description unit for controlling the operation of the resource for each unit clock. How to generate. 5. In the clock level description, one of the resources is shared by the plurality of variables.
5. The method for generating a simulation model according to any one of 4 to 4. 6. A recording medium in which a computer-executable program for realizing the simulation model generation method according to claim 1 is recorded. 7. A simulation method including a step in which the clock level verification unit simulates a simulation model including the clock level algorithm model according to any one of claims 1 to 5 based on the unit clock. 8. The simulation method according to claim 7, wherein the simulation model includes a clock level CPU model corresponding to the operation of the CPU. 9. The clock level verification unit associates the state of the resource with the algorithm description based on the result of the simulation, and displays the usage status of the resource for each description line of the algorithm description. The simulation method according to claim 7, further comprising a step. 10. The algorithm level description and variables obtained by the simulation, wherein the clock level verification unit uses the clock level description included in the simulation model and a resource usage correspondence table indicating a usage status of the resource. The simulation method according to claim 9, further comprising the step of displaying the correspondence of the values. 11. The step of displaying the usage status of the resource, the clock level verification unit, if the state transition of the unit clock of the clock level description occurs, the description of the algorithm description in which the state transition has occurred. A step of displaying a row and a usage status of the resource, wherein the step of displaying the correspondence between the variable values includes the state if the clock level verification unit causes a state transition of the unit clock of the clock level description. 11. The simulation method according to claim 9, further comprising the step of displaying the description line of the register description in which a transition has occurred and the variable value. 12. The simulation method according to claim 11, wherein the variable value is a value of a register or a memory of the resources. 13. A recording medium in which a computer-executable program for realizing the simulation method according to claim 7 is recorded. 14. A function synthesizing section for generating a state transition control model and a correspondence table from an algorithm description expressing a circuit module under the constraint of resources, and the state transition control model controls the state transition of each of the resources. However, the correspondence table represents a correspondence relationship between the resource and a variable in the algorithm description for each unit clock and the resource, and a clock level based on the state transition control model, the correspondence table, and interface information with the outside. A clock level verification unit for generating a clock level algorithm model of the description, the clock level description describes the operation of each of the resources at the unit clock, and the clock level algorithm model is for the circuit module. A simulation device that is the clock level description. 15. A display unit is further provided, wherein the clock level verification unit associates the state of the resource with the algorithm description based on the result of the simulation, and the clock level verification unit associates the state of the resource with the algorithm description. The resource usage status is displayed on the display unit, and the description line of the algorithm description and the variable value obtained by the simulation are calculated by using the clock level description and the resource use correspondence table included in the clock level simulation model. The simulation device according to claim 14, wherein the correspondence of is displayed on the display unit. 16. The clock level verification unit displays the description line of the algorithm description in which the state transition has occurred and the usage status of the resource when the state transition of the clock level description in the clock unit occurs. 16. The simulation apparatus according to claim 15, wherein the description line of the register description in which the state transition has occurred and the variable value are displayed when the state transition of the clock level description in the clock unit occurs. 17. An algorithm level verification unit for simulating an algorithm level simulation model of the circuit, including a hardware model representing a logical operation of the circuit, and a clock level algorithm generated from the hardware model under resource constraints. A clock level verification unit for simulating a clock level simulation model including a model and the clock level algorithm model represent each operation of the resource at a unit clock, and are generated from the hardware model under the constraint of the resource. And a RT level verification unit for simulating an RT level simulation model including an RT level algorithm model of the circuit. 18. The algorithm level simulation model includes a CPU model representing an operation of a CPU in the circuit, and the clock level simulation model represents a clock level CP representing an operation of the CPU for each unit clock.
The simulation apparatus according to claim 17, further comprising a U model, wherein the RT level simulation model includes an RT level CPU model that represents an operation of the CPU at an RT level. 19. The simulation apparatus according to claim 17, wherein a simulation time of the clock level simulation model is shorter than a simulation time of the RT level simulation model. 20. A display unit is further provided, wherein the clock level verification unit displays the state of the resource and the algorithm description based on a simulation result of the clock level algorithm model and the clock level CPU model. By associating the resource usage status for each description line of the algorithm description on the display unit and using the resource usage correspondence table indicating the resource usage status, the description line of the algorithm description and the simulation The simulation device according to claim 18 or 19, wherein correspondence of the obtained variable values is displayed on the display unit.