CN111313703A - Pulse sequence controlled PCCM Buck converter - Google Patents

Pulse sequence controlled PCCM Buck converter Download PDF

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Publication number
CN111313703A
CN111313703A CN202010193793.9A CN202010193793A CN111313703A CN 111313703 A CN111313703 A CN 111313703A CN 202010193793 A CN202010193793 A CN 202010193793A CN 111313703 A CN111313703 A CN 111313703A
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tube
pmos
nmos
circuit
transistor
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CN202010193793.9A
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CN111313703B (en
Inventor
曾衍瀚
陈涌楠
陈俊凯
林奕涵
杨敬慈
詹逸
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Guangzhou University
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Guangzhou University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H02M1/143—Arrangements for reducing ripples from dc input or output using compensating arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1566—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The application discloses PCCM Buck converter of pulse train control includes: the circuit comprises a main circuit, a current detection circuit, a first voltage comparator, a second voltage comparator, a charge control circuit and a pulse selection circuit; the output end of the main circuit is coupled to the reverse input end of the first voltage comparator, and the forward input end of the first voltage comparator is connected with reference voltage; the output end of the first voltage comparator is coupled to the input end of the pulse selection circuit, the output end of the pulse selection circuit is coupled to the main circuit, and the first input end of the logic control circuit; the input end of the current detection circuit is coupled to the main circuit, the output end of the current detection circuit is coupled to the reverse input end of the second voltage comparator, the positive input end of the second voltage comparator is coupled to the output end of the charge control circuit, and the output end of the second voltage comparator is coupled to the second input end of the logic control circuit; the output end of the logic control circuit is coupled to the current detection circuit; the charge control circuit is used for providing a freewheel value.

Description

Pulse sequence controlled PCCM Buck converter
Technical Field
The application relates to the technical field of integrated circuits, in particular to a pulse sequence controlled PCCM Buck converter.
Background
With the development of portable power electronic devices, switching power converters, such as DC-DC converters having high efficiency to supply large currents, have been widely used. Conventional linear control techniques, such as Pulse Width Modulation (PWM), including voltage mode and current mode, are difficult to predict in terms of both transient response and robustness. As a nonlinear technique, PT control has been proposed in recent years, which has advantages of simple implementation, no complex compensation, and fast transient response. PT control has been widely applied to switching converters operating in Discontinuous Conduction Mode (DCM) and Continuous Conduction Mode (CCM).
CCM is suitable for medium and high power applications, but has poor transient performance. Compared to CCM, DCM requires a simple control scheme and avoids the output diode reverse recovery problem, but results in larger current ripple and more severe electromagnetic interference (EMI). The Pseudo Continuous Conduction Mode (PCCM) has better transient response and better loading capacity by combining the advantages of CCM and DCM.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present application is to provide a PCCM Buck converter with fast transient, simple circuit structure and small current ripple pulse sequence control.
To solve the above problem, an embodiment of the present application provides a pulse train controlled PCCM Buck converter, including:
the circuit comprises a main circuit, a current detection circuit, a first voltage comparator, a second voltage comparator, a charge control circuit, a pulse selection circuit and a logic control circuit;
the main circuit comprises a first switching tube, a second switching tube, a third switching tube, an inductor and a first capacitor;
a source of the first switching tube is connected to a first voltage input end of the main circuit, a drain of the first switching tube is connected with a drain of the second switching tube and one end of the inductor, a source of the second switching tube is connected to a second voltage input end of the main circuit, a source of the third switching tube is connected with the drain of the first switching tube, the drain of the third switching tube is connected with one end of the first capacitor, and the other end of the first capacitor is connected with the source of the second switching tube;
the output end of the main circuit is coupled to the reverse input end of the first voltage comparator, and the forward input end of the first voltage comparator is connected with a reference voltage;
the output end of the first voltage comparator is coupled to the input end of the pulse selection circuit, the output end of the pulse selection circuit is coupled to the first switch tube, and the first input end of the logic control circuit;
an input end of the current detection circuit is coupled to a source electrode and a grid electrode of the second switch tube, a voltage output end of the current detection circuit is coupled to a reverse input end of the second voltage comparator, a positive input end of the second voltage comparator is coupled to an output end of the charge control circuit, and an output end of the second voltage comparator is coupled to a second input end of the logic control circuit;
the output end of the logic control circuit is coupled to the second switching tube and the third switching tube;
the charge control circuit is used for providing a freewheel value.
Further, the pulse selection circuit is used for outputting a high duty ratio pulse signal when the output voltage of the main circuit is lower than the reference voltage at the start time of any one switching period; otherwise, outputting a low duty ratio pulse signal.
Furthermore, the current detection circuit further comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;
the first PMOS tube, the second PMOS tube and the third PMOS tube are connected in a current mirror structure, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube and the drain electrode of the second NMOS tube, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the second NMOS tube and the drain electrode of the fourth NMOS tube;
the fifth PMOS tube is connected with the sixth PMOS tube in a current mirror structure, and the grid electrodes of the fifth PMOS tube and the sixth PMOS tube, and the drain electrode of the sixth PMOS tube are connected with the source electrode of the fourth PMOS tube;
the first NMOS tube is connected with the second NMOS tube in a current mirror structure, and the grid electrodes of the first NMOS tube and the second NMOS tube, and the drain electrode of the second NMOS tube are connected with the drain electrode of the second PMOS tube;
the drain of the third NMOS tube is connected with the source of the first NMOS tube, the grid of the third NMOS tube is connected with the grid of the second switch tube, and the source of the third NMOS tube is connected with the drain of the second switch tube;
and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the second switch tube, and the source stage of the fourth NMOS tube is grounded.
Further, the charge control circuit includes:
a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a second capacitor;
the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube are connected in a current mirror structure, the grid electrodes of the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube and the drain electrode of the fifth NMOS tube are connected with a current source, and the source electrodes of the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube are connected with a power supply;
the grid electrode of the seventh PMOS tube is connected with the drain electrode, the seventh PMOS tube is connected with the eighth PMOS tube in a current mirror structure, the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube are connected with the drain electrode of the sixth NMOS tube, and the source electrodes of the seventh PMOS tube and the eighth PMOS tube are connected with the power supply;
the grid electrode of the eighth NMOS tube is coupled to the second switch tube so as to access a driving signal of the second switch tube, and the source electrode of the eighth NMOS tube is connected with the drain electrode of the seventh NMOS tube;
the grid electrode of the ninth PMOS tube is coupled to the third switching tube so as to access a driving signal of the third switching tube, and the source electrode of the ninth PMOS tube is connected with the drain electrode of the eighth PMOS tube;
and the eighth NMOS tube is connected with a drain of the ninth PMOS switch, one end of a second capacitor is connected with the output end of the charge control circuit, and the other end of the second capacitor is grounded.
Further, the pulse selection circuit comprises a trigger, a first and gate circuit, a second and gate circuit and an or gate circuit;
the input end of the trigger is connected with the output end of the first voltage comparator, the high level output end of the trigger is connected with the input end of the first AND gate circuit, the low level output end of the trigger is connected with the input end of the second AND gate circuit, the output ends of the first AND gate circuit and the second AND gate circuit are connected with the OR gate circuit, and the output end of the OR gate circuit is coupled to the first switch tube and the first input end of the logic control circuit.
Further, the flip-flops comprise class D flip-flops.
Furthermore, the first switch tube is a PMOS tube, and the second switch tube and the third switch tube are NMOS tubes.
Compared with the prior art, the embodiment realizes the detection of the MOS tube current through the connection mode, so that the continuous current value changes along with the change of the load current, the circuit keeps a PCCM state when the load changes, and the rapid transient state is realized. And different follow current values can be output along with the change of the load in the transient state so as to reduce current ripples and avoid the circuit from exiting the PCCM state when the load changes.
Drawings
FIG. 1 is a schematic diagram of a pulse train controlled PCCM Buck converter according to an embodiment of the present application;
FIG. 2 is a simplified circuit diagram of a current sensing circuit;
FIG. 3 is a timing sequence when the circuit load changes;
FIG. 4 is a simplified circuit diagram of a charge control circuit;
fig. 5 shows the process of the output voltage of the charge control circuit under the load change of the circuit.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
With the development of portable power electronic devices, switching power converters, such as DC-DC converters having high efficiency to supply large currents, have been widely used. Conventional linear control techniques, such as Pulse Width Modulation (PWM), including voltage mode and current mode, are difficult to predict in terms of both transient response and robustness. As a nonlinear technique, PT control has been proposed in recent years, which has advantages of simple implementation, no complex compensation, and fast transient response. PT control has been widely applied to switching converters operating in Discontinuous Conduction Mode (DCM) and Continuous Conduction Mode (CCM).
CCM is suitable for medium and high power applications, but has poor transient performance. Compared to CCM, DCM requires a simple control scheme and avoids the output diode reverse recovery problem, but results in larger current ripple and more severe electromagnetic interference (EMI). The Pseudo Continuous Conduction Mode (PCCM) has better transient response and better loading capacity by combining the advantages of CCM and DCM. The present boost converter has not been implemented in an integrated circuit, and furthermore, implementing the circuit in an integrated circuit also faces the problem of how to design the NMOS current sensing. Therefore, referring to fig. 1, it is a schematic structural diagram of a pulse train controlled PCCM Buck converter provided in an embodiment of the present application, including: the circuit comprises a main circuit 1, a current detection circuit 2, a first voltage comparator COMP1, a second voltage comparator COMP2, a charge control circuit 3, a pulse selection circuit 4 and a logic control circuit 5.
The main circuit 1 comprises a first switch tube S1, a second switch tube S2, a third switch tube S3, an inductor L and a first capacitor C1.
The source of the first switch tube S1 is connected to the first voltage input end of the main circuit 1, i.e. to the positive end of the external power supply, the drain of the first switch tube S1 is connected to the drain of the second switch tube S2 and to one end of the inductor L, the source of the second switch tube S2 is connected to the second voltage input end of the main circuit 1, i.e. to the negative end of the external power supply, the source of the third switch tube S3 is connected to the drain of the first switch tube S1, the drain of the third switch tube S3 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the source of the second switch tube S2. The first switch tube S1 is a PMOS tube, and the second switch tube S2 and the third switch tube S3 are NMOS tubes.
An output end of the main circuit 1 is coupled to an inverting input end of a first voltage comparator COMP1 to output a voltage Vo to the inverting input end of the first voltage comparator COMP1, and a forward input end of a voltage comparator COMP1 is connected to a reference voltage Vref.
An output terminal of the first voltage comparator COMP1 is coupled to an input terminal of the pulse selection circuit 4, so that an output signal thereof is used as an input signal of the pulse selection circuit 4, an output terminal of the pulse selection circuit 4 is coupled to the first switch tube S1, and a first input terminal of the logic control circuit 5.
The input end of the current detection circuit 2 is coupled to the source and the gate of the second switch tube S2 for performing current detection of the main circuit. A voltage output terminal of the current detection circuit 2 is coupled to an inverting input terminal of the second voltage comparator COMP2 to output the current detection voltage Vsen to an inverting input terminal of the second voltage comparator COMP2, a positive input terminal of the first voltage comparator COMP1 is coupled to an output terminal of the charge control circuit 3 to receive the voltage Vdc supplied from the charge control circuit, and an output terminal of the second voltage comparator COMP2 is coupled to a second input terminal of the logic control circuit 5.
The output end of the logic control circuit is coupled to the second switch tube S2 and the third switch tube S3, so that two paths of output signals of the logic control circuit are used as control signals of the switch tubes S2 and S3, respectively.
The charge control circuit 3 is used to provide a freewheel value. When the charge control circuit 3 provides a follow current value, the converter enters a follow current stage, and when the switching tube S3 is conducted, the capacitor of the charge control circuit is charged, and the follow current value is increased; when the switch tube S2 is turned on, the charge control module capacitor discharges and the freewheel value decreases. The continuous current value changes along with the change of the load current, so that the circuit keeps a PCCM state when the load changes, and the rapid transient state is realized.
In this embodiment, the first voltage comparator COMP1 compares the voltage Vo obtained by dividing the output voltage of the main circuit 1 with the reference voltage Vref at the start time of any one switching cycle. When the output voltage of the main circuit 1 after voltage division is lower than the reference voltage, the pulse selection circuit 4 outputs a high duty ratio pulse signal PH, that is, a high level, as a driving signal of the first switching tube S1, otherwise, the pulse selection circuit 4 outputs a low duty ratio pulse signal PL, that is, a low level, as a driving signal of the first switching tube. At this time, the first switching tube S1 is turned on, the second switching tube S2 and the third switching tube S3 are turned off, and the inductor current increases. When the pulse PH or PL is over, the second switch tube S2 is turned on, the first switch tube S1 and the third switch tube S3 are turned off, and the inductor current drops at this stage, and at this time, the current detection voltage Vsen at the output end of the current detection circuit 2 is compared with the output voltage Vdc of the charge control circuit 3 through the second voltage comparator COMP 2. When Vsen reaches the freewheeling value, the third switch tube S3 is turned on, the first switch tube S1 and the second switch tube S2 are turned off, and the freewheeling stage is entered, in which the inductor current is unchanged.
In the present embodiment, the pulse selection circuit includes a class D flip-flop, a first AND circuit AND1, a second AND circuit AND2, AND an OR gate OR.
The input end of the flip-flop D is connected to the output end of the first voltage comparator COMP1, that is, the input end of the first voltage comparator COMP1 as a data selector is connected to the D flip-flop. The high-level output end Q of the flip-flop D is connected to the input end of the first AND-gate circuit AND1, the low-level output end Q' of the flip-flop D is connected to the input end of the second AND-gate circuit AND2, the output ends of the first AND-gate circuit AND1 AND the second AND-gate circuit AND2 are connected to an OR-gate OR, AND the output end of the OR-gate OR is coupled to the first switching tube S1 AND the first input end of the logic control circuit 5. When the output voltage Vo is lower than the reference voltage Vref, the Q end of the D trigger outputs a high level; otherwise, the Q' end outputs low level. Each pulse signal is connected with an AND gate, and when the condition is met, the corresponding pulse signal is output.
Further, as shown in fig. 2, the current detection circuit 2 further includes a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M9, and an NMOS transistor M10. The PMOS tube M1, the PMOS tube M2, the PMOS tube M3, the NMOS tube M4 and the NMOS tube M5 form an operational amplifier, the source electrode of the NMOS tube M5 is the non-inverting input end of the operational amplifier, and the source electrode of the NMOS tube M4 is the inverting input end of the operational amplifier.
The PMOS transistor M1, the PMOS transistor M2 and the PMOS transistor M3 are connected in a current mirror structure, namely the gates of the PMOS transistor M1, the PMOS transistor M2 and the PMOS transistor M3 and the drain of the PMOS transistor M1 are connected with a current source and lead out a current output end. The grid electrode of the PMOS tube M6 is connected with the drain electrode of the PMOS tube M3 and the drain electrode of the NMOS tube M5, the drain electrode of the PMOS tube M6 is connected with the source electrode of the NMOS tube M5 and the drain electrode of the NMOS tube M10, and therefore a negative feedback loop of the operational amplifier is formed.
The PMOS transistor M7 and the PMOS transistor M8 are connected in a current mirror structure, the grid electrodes of the PMOS transistor M7 and the PMOS transistor M8, and the drain electrode of the PMOS transistor M8 are connected with the source electrode of the PMOS transistor M6, and a current output end is led out. The output current will form a current sense voltage Vsen via a resistor R in fig. 2.
The NMOS transistor M4 is connected with the NMOS transistor M5 in a current mirror structure, the gates of the NMOS transistor M4 and the NMOS transistor M5, and the drain of the NMOS transistor M5 is connected with the drain of the PMOS transistor M2.
The drain of the NMOS transistor M9 is connected with the source of the NMOS transistor M4, i.e. connected to the inverting input terminal of the operational amplifier. The gate of the NMOS transistor M9 is connected to the gate of the second switch transistor to receive the control signal Vs 2. The source of the NMOS transistor M9 is connected to the drain of the second switch transistor, i.e., the source of the NMOS transistor M9 is connected to the voltage Vsw. The grid electrode of the NOMS tube M10 is connected to the grid electrode of the second switch tube S2 to receive the control signal N provided by the second switch tube, and the source electrode of the NOMS tube M10 is grounded. At this time, the op-amp acts as a follower, equalizing the voltage at point A, B.
During inductor current droop, i.e., during the period D2T shown in fig. 3, the currents at the first switch transistor S2 and the node Vsw are both negative, but since the amplifier composed of M1-M5 provides a dc bias, the negative voltage VB in the node a becomes positive. As the inductor current decreases, VSW increases, VB and VA increase. As shown in fig. 3, the fall of the induced current is detected and becomes a rise of Vsen. And once Vsen increases to Vdc, the converter enters the freewheel phase at this point. This current detection circuit, unlike the current mode of PWM control, is a current detection technique suitable for NMOS rather than PMOS.
In this case, however, the curve of Vsen moves down as the load current increases, thus requiring a longer time to reach Vdc. On the other hand, if Vdc is fixed, an increase in load current will cause D2T to shorten. If the increase is large, the converter may enter CCM, which may result in low frequency oscillations. Thus, Vdc should vary adaptively with load.
In view of this, the present embodiment provides a charge control circuit, as shown in fig. 4, including an NMOS transistor MA1, an NMOS transistor MA2, an NMOS transistor MA3, an NMOS transistor Mdch, a PMOS transistor MB1, a PMOS transistor MB2, a PMOS transistor Mch, and a second capacitor C2.
The NMOS tube MA1, the NMOS tube MA2 and the NMOS tube MA3 are connected in a current mirror structure, the grid electrodes of the NMOS tube MA1, the NMOS tube MA2 and the NMOS tube MA3 and the drain electrode of the NMOS tube MA1 are connected to a current source and led out to generate a current output end, and the source electrodes of the NMOS tube MA1, the NMOS tube MA2 and the NMOS tube MA3 are connected to a power supply.
The PMOS tube MB1 is connected into a diode form, namely a grid electrode is connected with a drain electrode, the PMOS tube MB1 is connected with the PMOS tube MB2 in a current mirror structure, the grid electrode of the PMOS tube MB1 and the grid electrode of the PMOS tube MB2 are connected with the drain electrode of the NMOS tube MA2 and led out to generate a current output end, and the source electrode of the PMOS tube MB1 and the source electrode of the PMOS tube MB2 are connected with a power supply.
The gate of the NMOS transistor Mdch is coupled to the second switch transistor S2 to receive the driving signal Vs2 of the second switch transistor S2, and the source of the NMOS transistor Mdch is connected to the drain of the NMOS transistor MA 3.
The grid electrode of the PMOS tube Mch is coupled to the third switch tube S3 to switch in a driving signal Vs3 of the third switch tube S3, and the source electrode of the PMOS tube Mch is connected with the drain electrode of the PMOS tube MB 2;
an NMOS transistor Mdch and a ninth PMOS off drain, and one end of a second capacitor C2 is connected to the output terminal of the charge control circuit to output the voltage Vdc, and the other end of the second capacitor C2 is grounded.
At this time, Mch is open during D3T and Mdch is open during D2T. Vdc is charged by a constant sink current Ich during D3T and discharged by a constant source current Idch-mIch during D2T. In steady state, Vdc remains constant as shown by the implementation in fig. 5, and due to feedback, a suitable D3T can be achieved.
It satisfies:
Ioh×D3T＝Idoh×D2T
assume that the charging and discharging power of the capacitor is Qin and Qout, respectively. Comprises the following steps:
Figure RE-GDA0002487618060000091
if the load current increases, the charge-discharge cycle of the respective inductor currents D '1T and D'2T needs to be extended to provide more power. D'3T is correspondingly reduced, resulting in Qin being less than Qout. Thus Vdc decreases to V' dc, as indicated by the dashed line identified by the lowermost Vdc on the right in fig. 5. Similarly, when the load is reduced, the Vdc value increases as indicated by the dashed line corresponding to the uppermost Vdc mark on the right in fig. 5. In this way, the PCCM control signal Vdc can be adaptively adjusted based on the load current, and then different follow-up current values can be output along with the change of the load in a transient state, so as to reduce the current ripple and avoid the circuit from exiting the PCCM state when the load changes.
The foregoing is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations are also regarded as the protection scope of the present application.

Claims (7)

1. A pulse train controlled PCCM Buck converter, comprising: the circuit comprises a main circuit, a current detection circuit, a first voltage comparator, a second voltage comparator, a charge control circuit, a pulse selection circuit and a logic control circuit;
the main circuit comprises a first switching tube, a second switching tube, a third switching tube, an inductor and a first capacitor;
a source of the first switching tube is connected to a first voltage input end of the main circuit, a drain of the first switching tube is connected with a drain of the second switching tube and one end of the inductor, a source of the second switching tube is connected to a second voltage input end of the main circuit, a source of the third switching tube is connected with the drain of the first switching tube, the drain of the third switching tube is connected with one end of the first capacitor, and the other end of the first capacitor is connected with the source of the second switching tube;
the output end of the main circuit is coupled to the reverse input end of the first voltage comparator, and the forward input end of the first voltage comparator is connected with a reference voltage;
the output end of the first voltage comparator is coupled to the input end of the pulse selection circuit, the output end of the pulse selection circuit is coupled to the first switch tube, and the first input end of the logic control circuit;
an input end of the current detection circuit is coupled to a source electrode and a grid electrode of the second switch tube, a voltage output end of the current detection circuit is coupled to a reverse input end of the second voltage comparator, a positive input end of the second voltage comparator is coupled to an output end of the charge control circuit, and an output end of the second voltage comparator is coupled to a second input end of the logic control circuit;
the output end of the logic control circuit is coupled to the second switching tube and the third switching tube;
the charge control circuit is used for providing a freewheel value.
2. The pulse train controlled PCCM Buck converter according to claim 1, wherein the pulse selection circuit is configured to output a high duty cycle pulse signal when the output voltage of the main circuit is lower than the reference voltage at the start of any one switching cycle; otherwise, outputting a low duty ratio pulse signal.
3. The pulse train controlled PCCM Buck converter according to claim 1, wherein the current sensing circuit further comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;
the first PMOS tube, the second PMOS tube and the third PMOS tube are connected in a current mirror structure, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube and the drain electrode of the second NMOS tube, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the second NMOS tube and the drain electrode of the fourth NMOS tube;
the fifth PMOS tube is connected with the sixth PMOS tube in a current mirror structure, and the grid electrodes of the fifth PMOS tube and the sixth PMOS tube, and the drain electrode of the sixth PMOS tube are connected with the source electrode of the fourth PMOS tube;
the first NMOS tube is connected with the second NMOS tube in a current mirror structure, and the grid electrodes of the first NMOS tube and the second NMOS tube, and the drain electrode of the second NMOS tube are connected with the drain electrode of the second PMOS tube;
the drain of the third NMOS tube is connected with the source of the first NMOS tube, the grid of the third NMOS tube is connected with the grid of the second switch tube, and the source of the third NMOS tube is connected with the drain of the second switch tube;
and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the second switch tube, and the source stage of the fourth NMOS tube is grounded.
4. The pulse train controlled PCCM Buck converter according to claim 1, wherein the charge control circuit comprises:
a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a second capacitor;
the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are connected in a current mirror structure, the grid electrodes of the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor and the drain electrode of the fifth NMOS transistor are connected with a current source, and the source electrodes of the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are grounded;
the grid electrode of the seventh PMOS tube is connected with the drain electrode, the seventh PMOS tube is connected with the eighth PMOS tube in a current mirror structure, the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube are connected with the drain electrode of the sixth NMOS tube, and the source electrodes of the seventh PMOS tube and the eighth PMOS tube are connected with the power supply;
the grid electrode of the eighth NMOS tube is coupled to the second switch tube so as to access a driving signal of the second switch tube, and the source electrode of the eighth NMOS tube is connected with the drain electrode of the seventh NMOS tube;
the grid electrode of the ninth PMOS tube is coupled to the third switching tube so as to access a driving signal of the third switching tube, and the source electrode of the ninth PMOS tube is connected with the drain electrode of the eighth PMOS tube;
and the eighth NMOS tube is connected with a drain of the ninth PMOS switch, one end of a second capacitor is connected with the output end of the charge control circuit, and the other end of the second capacitor is grounded.
5. The pulse train controlled PCCM Buck converter according to claim 1 or 2, wherein the pulse selection circuit comprises a flip-flop, a first and gate circuit, a second and gate circuit, and an or gate circuit;
the input end of the trigger is connected with the output end of the first voltage comparator, the high level output end of the trigger is connected with the input end of the first AND gate circuit, the low level output end of the trigger is connected with the input end of the second AND gate circuit, the output ends of the first AND gate circuit and the second AND gate circuit are connected with the OR gate circuit, and the output end of the OR gate circuit is coupled to the first switch tube and the first input end of the logic control circuit.
6. The pulse train controlled PCCM Buck converter according to claim 5, wherein the flip-flop comprises a class D flip-flop.
7. The pulse train controlled PCCM Buck converter according to claim 1, wherein the first switch is a PMOS transistor, and the second and third switch are NMOS transistors.
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