CN216904670U - Control circuit of DC/DC boosting system - Google Patents

Abstract

A control circuit of a DC/DC boosting system is used for boosting a voltage signal V1 into a voltage signal V2 and outputting the voltage signal V2; the circuit comprises a first transistor Q1, a second transistor Q2, an inductor L1, a constant conduction time module, a gating module T1, a PWM (pulse-width modulation) generation module, a boosting system driving control module and a current zero-crossing comparison module ZCCDCMP (zero cross point comparison); the gating module T1 outputs the PWM signal generated by the PWM generating module or the signal output by the constant on-time module according to the detection result of the received current zero-crossing comparison module ZCCDCMP on the working mode of the boosting same load; the boost system driving control module receives the output of the gating module T1 to generate a signal CLKP for controlling the on/off of the second transistor Q2 and a signal CLKN for controlling the on/off of the first transistor Q1, so as to ensure that the on/off time of the first transistor Q1 is the fixed on-time set by the constant on-time module under light load. Therefore, the utility model enables the boosting system in the heavy load mode to work in the constant frequency mode, and the boosting system in the light load mode to work in the constant conduction time mode.

Description

Control circuit of DC/DC boosting system

Technical Field

The utility model belongs to the technical field of circuit design, and relates to a control circuit of a DC/DC boosting system.

Background

The control circuit of the DC/DC boost system is applied more and more widely, for example, in the application scenes of power supply boost such as LED lighting, mobile phones, earphones, and wearable devices. In order to operate the DC/DC boost system in the power saving mode, a control circuit is usually used to detect and control the operation of the DC/DC boost system in the light load mode or the heavy load mode.

Referring to fig. 1, fig. 1 is a schematic diagram of a control circuit of a DC/DC boost system in the prior art. As shown, the control circuit includes a first voltage-dividing resistor RFB1, a second voltage-dividing resistor RFB2, a voltage-stabilizing capacitor C1 for V1, a voltage-stabilizing capacitor C2 for V2, an inductor L1, a first transistor Q1, a second transistor Q2, a Fixed minimum ON-Time module (Fixed MIN ON Time), an oscillator module OSC, an error amplifier module EAMP, a comparator module PWMCMP, a LOGIC control module LOGIC, a drive module dri, and a current zero-crossing comparison module zcdccmp.

The voltage V1 is an input voltage signal, and is generally provided by various battery or solar-generated voltages. The voltage V2 is an output voltage signal that provides voltage to various devices in the next level. In a boost system, voltage V1 is typically less than voltage V2. The Fixed minimum ON Time module (Fixed MIN ON Time) is used to set a minimum Time to control the first transistor Q1 to conduct. The oscillator module OSC is used for generating a harmonic signal RAMP and an OSC signal CLK; the error amplifier module EAMP is used for performing difference amplification on the reference voltage signal VREF and the feedback signal FB of the V2 to output a COMP signal; the comparator module PWMCMP compares the COMP signal with the RAMP signal and outputs a PWM signal; the LOGIC control module LOGIC is used for integrating the PWM signal and the CLK into an original driving signal DR1, and the driving module DRIVER generates CLKP and CLKN to control the on and off of the second transistor Q2 and the first transistor Q1, respectively; the current zero-crossing comparison module ZCCDCMP is used for monitoring whether the current of the inductor L is 0 or not; the fixed minimum on-time module is used to control the minimum on-time of the first transistor Q1, and may not be used in some conventional architectures.

The specific working principle of the circuit is as follows: when the signal CLKN and the signal CLKP are at a high level, the first transistor Q1 is turned on, the second transistor Q2 is turned off, the SW is connected to the ground GND (i.e., at a low level), and the current of the inductor L increases; when the signal CLKP and the signal CLKN are at a low level, the second transistor Q2 is turned on, the first transistor Q1 is turned off, at this time, SW is at a high level, VSW is V2+ Ron _ Q2 IQ2, and the current of the inductor L decreases.

When the current of the inductor L decreases to 0, VSW is equal to V2, and the output of the current zero-crossing comparison module zcdccmp (comparing the SW voltage and the V2 voltage) is at a high level, i.e., indicating that the boost system enters the light-load mode. If the current of the inductor L does not drop to 0 at all times, i.e., VSW is always greater than the voltage V2, it means that the boosting system is always operating in the heavy load mode. Of course, in some applications, the inductor current is close to 0, VSW ═ V2+ Vo, Vo is a small voltage value, and the output of the zero-crossing current comparison module zcdccmp is also high, i.e., it indicates that the boost system enters the light-load mode.

After the boost system enters the light load mode, in order to achieve the effect of saving energy under light load, the frequency of the oscillator OSC is decreased (or the ZCDCMP output signal turns off the oscillator OSC so that it does not work any more or operates at a decreased frequency), at this time, the overall operating frequency of the boost system is decreased, and the first transistor Q1 and the second transistor Q2 are turned off, so as to achieve the effect of saving energy under light load.

However, in the above control process, an unstable phenomenon that the on time of the first transistor Q1 is suddenly changed is caused; in addition, a Fixed minimum ON-Time module (Fixed MIN ON Time) is typically used to define the minimum Time that the first transistor Q1 is ON when operating in the light load mode.

Referring to fig. 2, fig. 2 is a schematic diagram showing a waveform of the CLKN signal TON of the DC/DC boost system of fig. 1. As shown, since the minimum ON-Time (Fixed MIN ON Time, MINTON) is Fixed, the Fixed minimum ON-Time is usually designed to be very small for different application scenarios of the voltage V1 and the voltage V2, which results in a high frequency of system operation under light load and failure to achieve better light load efficiency. Namely, the size of the TON signal CLKN in the prior art is changed, the system is unstable, and MINTON is not favorable for light load energy saving.

SUMMERY OF THE UTILITY MODEL

To solve the above technical problem, the present invention provides a control circuit of a DC/DC boost system, which ensures that the on/off time of the first transistor Q1 is the same at the time of light load and heavy load, so as to achieve the ideal energy saving effect after the boost system enters the light load mode.

In order to achieve the purpose, the technical scheme of the utility model is as follows:

a control circuit of a DC/DC boosting system is used for boosting an input direct-current power supply voltage signal V1 into a direct-current power supply voltage signal V2 and outputting the direct-current power supply voltage signal V2; it includes:

a first transistor Q1, a first transistor Q2, and an inductor L1; the inductor L1 is connected between the input terminal of the DC power supply voltage signal V1 and the drain connection point SW of the first transistor Q1 and the second transistor Q2; the source electrode of the first transistor Q1 is grounded, and the source electrode of the second transistor Q2 is connected with the output end of the direct current power supply voltage signal V2;

the current zero-crossing comparison module ZCCDCMP detects the load working mode of the boosting system and outputs a signal ZC according to the power supply voltage signal V1 and the power supply voltage signal V2; one input end of the direct current power supply is connected with a contact point SW, and the other input end of the direct current power supply is connected with the output end of the direct current power supply voltage signal V2;

the PWM generating module is used for generating a PWM signal and a fixed period frequency signal;

the constant on-time module is used for generating fixed on-time related to the power supply voltage signal V1 and the power supply voltage signal V2 in a proportional relation according to the detection result of the load working mode obtained by the current zero-crossing comparison module ZCCDCMP and outputting a corresponding control signal;

a gating module T1, receiving the detection result of the current zero crossing comparison module zcdccmp load operation mode, and outputting the PWM signal generated by the PWM generation module if the detection result is the heavy load operation mode; if the detection result is in a light load working mode, outputting a signal output by the constant conduction time module;

and the boost system driving control module is used for receiving the output of the gating module T1 and a fixed period frequency signal, and generating a signal CLKP for controlling the on-off of the second transistor Q2 and a signal CLKN for controlling the on-off of the first transistor Q1 so as to ensure that the on-off time of the first transistor Q1 is the fixed on-off time set by the constant on-time module. Preferably, the fixed on-time is directly proportional to the difference between V2 and V1, and inversely proportional to V2 itself.

Further, the control circuit of the DC/DC boost system further includes an on-off pre-control module, and when the current flowing through the first transistor Q1 is greater than a preset current threshold, the on-off pre-control module controls the gating module T1 to receive the output of the constant on-time module.

Furthermore, the on-off pre-control module comprises a logic gate and a current monitoring module; the current detection module comprises a zeroth transistor Q0, a comparator circuit CLCMP and a current source IOC; one input end of the logic and gate is connected with the output end of the constant on-time module, one input end of the logic gate is connected with the output end of the comparator circuit CLCMP, the zeroth transistor Q0 is a mirror tube of the first transistor Q1 and is used for mirroring the current of the first transistor Q1, and the current of the current source IOC is a current threshold; when the current of the zeroth transistor Q0 is greater than IOC, the comparator circuit CLCMP controls the logic gate to allow the output of the constant on-time module.

Further, the constant on-time TON of the first transistor Q1 is:

TON is greater than or equal to TOSC (V2-V1)/V2

Wherein, the TOSC is the period time of the fixed period frequency signal of the PWM generating module.

Further, the gating module T1 includes a logic inverter INV1, a transmission gate TG1, and a transmission gate TG 2; the input end of the logic inverter INV1, the lower gate of the transmission gate TG1 and the upper gate of the transmission gate TG2 receive the output signal ZC of the zero-crossing current comparison module zcdccmp, and the output end of the logic inverter INV1, the upper gate of the transmission gate TG1 and the lower gate of the transmission gate TG2 are connected together; the output ends of the transmission gate TG1 and the transmission gate TG2 are connected together, and the output result is input into the boosting system driving control module; the on-off of the transmission gate TG1 controls the on-off of the constant on-time module, and the on-off of the transmission gate TG2 controls the on-off of the signal PWM; when entering a light load mode, the transmission gate TG1 is conducted, and the transmission gate TG2 is closed; when entering the heavy load mode, the transmission gate TG2 is turned on, and the transmission gate TG1 is turned off.

Further, the constant on-time module includes a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a third PMOS transistor Q3, a fourth PMOS transistor Q4, a resistor RTON for generating a charging current for setting the TON time, a charging capacitor CTON for setting the TON time, an operational amplifier OP1, and a comparator TONCMP for generating the TON time; the positive end of the operational amplifier OP1 is connected with the output end of the control circuit, the negative end of the operational amplifier OP1 is connected with the source electrode of the fifth NMOS transistor Q5, and the output end of the operational amplifier OP1 is connected with the grid electrode of the fifth NMOS transistor Q5; the resistor RTON is connected between the source of the fifth NMOS transistor Q5 and the ground terminal; the drains of the fifth NMOS transistor Q5, the sixth NMOS transistor Q6, the third PMOS transistor Q3, and the fourth PMOS transistor Q4 are connected together with the positive electrode of the comparator TONCMP, the negative electrode of the comparator TONCMP is connected to the voltage VC, the sources and gates of the third PMOS transistor Q3 and the fourth PMOS transistor Q4 are connected together, the charging capacitor CTON is connected between the drain and the source of the sixth NMOS transistor Q6, and the gate of the sixth NMOS transistor Q6 is connected to the signal CLKN; wherein, the voltage VC is the voltage of the negative terminal of the comparator TONCMP, and the value is V2-V1; when the signal DR1 is at a high level, the sixth NMOS transistor Q6 is turned off, and the capacitor CTON is charged by the current of the fourth PMOS transistor Q4, and the voltage signal thereof is VRC; when the upper voltage VRC of the capacitor CTON is greater than the negative terminal signal VC of the comparator TONCMP; the comparator TONCMP generates a comparison signal TON1, the signal TON1 is the output signal of the constant on-time module.

Further, the PWM generating module includes an error amplifier module EAMP, a comparator module PWMCMP, and an oscillator OSC, a positive input of the error amplifier module EAMP is connected to the reference voltage, another input of the error amplifier module EAMP is connected to the divided voltage of the output voltage V2, and an output of the error amplifier module EAMP is connected to a negative input of the comparator module PWMCMP; the oscillator OSC provides a sawtooth wave signal to the positive input terminal of the comparator module PWMCMP and a fixed period frequency to the boost system drive control module according to the signal ZC, and the output terminal of the comparator module PWMCMP is connected to the gate module T1.

Further, the boost system driving control module includes a LOGIC control module LOGIC receiving the pulse clock signal CLK and the output of the gating module T1, and generating a driving signal DR1 to the driving module DRIVER, which outputs a signal CLKP and a signal CLKN.

Further, the LOGIC control module LOGIC is an RS latch.

Further, the fixed period frequency is a pulse clock signal CLK.

Further, the control circuit of the DC/DC boost system further includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is connected in parallel between the input terminal of the DC power voltage signal V1 and the ground terminal GND; the second capacitor C2 is connected in parallel between the output terminal of the dc power voltage signal V2 and the ground terminal GND.

It can be seen from the above technical solutions that, in the control circuit of the DC/DC boost system of the present invention, a Constant ON Time control module (Constant ON Time) is added in the light load mode, the boost system in the heavy load mode operates in a Fixed Frequency (Fixed Frequency) mode, and the boost system in the light load mode operates in a Constant ON Time mode. That is, since the conduction time of the first transistor Q1 is fixed in the present invention, not only the ideal energy saving effect after the boost system enters the light load mode is achieved, but also the stability of the boost system when operating in the light load mode is increased.

Drawings

FIG. 1 is a schematic diagram of a control circuit of a DC/DC boost system in the prior art

FIG. 2 is a waveform diagram of the CLKN signal TON of the DC/DC boost system of FIG. 1

FIG. 3 is a schematic diagram of a control circuit of the DC/DC boost system according to a preferred embodiment of the present invention

FIG. 4 is a schematic diagram of a constant on-time module in the control circuit of the DC/DC boost system of the present invention

FIG. 5 is a schematic diagram of another preferred embodiment of the control circuit of the DC/DC boost system of the present invention

FIG. 6 is a waveform diagram of the CLKN signal TON of the DC/DC boost system of FIG. 3 or FIG. 5

Detailed Description

The following describes in further detail embodiments of the present invention with reference to fig. 3-6.

It should be noted that the greatest difference between the present invention and the prior art is: in the control circuit of the DC/DC boosting system of the utility model, a constant conduction time module and a gating module T1 are added to replace a fixed minimum conduction time module in the prior art.

Specifically, in the following embodiments of the present invention, the control circuit of the DC/DC boost system is configured to boost the input DC power voltage signal V1 into the DC power voltage signal V2 for output; the boost circuit mainly comprises a first transistor Q1, a first transistor Q2, an inductor L1, a current zero-crossing comparison module ZCCDCMP, a PWM generation module, a gating module T1, a constant conduction time module and a boost system driving control module.

The inductor L1 is connected between the input end of the DC power supply voltage signal V1 and the drain connection point SW of the first transistor Q1 and the second transistor Q2; the source of the first transistor Q1 is grounded, and the source of the second transistor Q2 is connected to the output terminal of the dc power voltage signal V2; the current zero-crossing comparison module ZCCDCMP detects the load working mode of the boosting system and outputs a signal ZC according to the power supply voltage signal V1 and the power supply voltage signal V2; one input end of the direct current power supply is connected with the contact SW, and the other input end of the direct current power supply is connected with the output end of the direct current power supply voltage signal V2; the PWM generating module is used for generating a PWM signal and a fixed period frequency (such as a pulse clock signal CLK); the constant on-time module generates fixed on-time related to a proportional relation between a power supply voltage signal V1 and a power supply voltage signal V2 according to a detection result of a load working mode obtained by the current zero-crossing comparison module ZCDPM and outputs a corresponding control signal; the gating module T1 receives the detection result of the load working mode of the current zero-crossing comparison module ZCCDCMP, and outputs the PWM signal generated by the PWM generating module if the detection result is the heavy load working mode; if the detection result is in the light load working mode, outputting a signal output by the constant conduction time module; and the boost system driving control module is used for receiving the output of the gating module T1 and a fixed period frequency, and generating a signal CLKP for controlling the on-off of the second transistor Q2 and a signal CLKN for controlling the on-off of the first transistor Q1 so as to ensure that the on-off time of the first transistor Q1 is the same when the load is light and heavy.

That is, when the system operates in the light load power saving mode, the system operates at a Constant ON Time (Constant ON Time), and the Constant ON Time (the Constant ON Time of the first transistor Q1) is consistent with the ON Time when the system operates under a heavy load and is stable, so that the ON Time of the first transistor Q1 is consistent under either a light load or a heavy load, which is very beneficial to the stability of the system during the light load operation.

Example 1

Referring to fig. 3, fig. 3 is a schematic diagram of a control circuit of the DC/DC boost system according to a preferred embodiment of the present invention. As shown, the control circuit of the DC/DC boost system includes a first voltage dividing resistor RFB1, a second voltage dividing resistor RFB2, a voltage stabilizing capacitor C1 for V1, a voltage stabilizing capacitor C2 for V2, a voltage source DC, an inductor L1, a first transistor Q1, a second transistor Q2, a constant on-time module, a gating module T1, an oscillator module OSC, an error amplifier module EAMP, a comparator module PWMCMP, a LOGIC control module LOGIC, a drive module DRIVER, and a current zero-crossing comparison module zcdccmp; the voltage V1 is the voltage signal at the input of the control circuit, the voltage V2 is the voltage signal at the output of the control circuit, and the voltage V1 is usually smaller than the voltage V2.

Specifically, the inductor L1 is connected between a node SW and the input end of the control circuit, the node SW is a connection point of one input end of the current zero-crossing comparison module zcdccmp and the drain of the first transistor Q1 and the drain of the second transistor Q2, and the source of the first transistor Q1 is connected to the ground; the voltage source DC and the voltage-stabilizing capacitor C1 are connected in parallel between the input end of the control circuit and the grounding end; the output end of the control circuit is connected with the other input end of the current zero-crossing comparison module ZCCDCMP, one end of a voltage-stabilizing capacitor C2, one end of a first voltage-dividing resistor RFB1 and the source electrode of a second transistor Q2, and one end of a voltage-stabilizing capacitor C2 is connected with the ground end; the driving module DRIVER receives the output signal ZC of the current zero-cross comparison module zcdccmp and the output DR1 of the LOGIC control module LOGIC, and outputs a signal CLKP to the gate of the second transistor Q2 and a signal CLKN to the gate of the first transistor Q1; the oscillator module OSC receives an output ZC of the current zero-crossing comparison module ZCDPMC, outputs a pulse clock signal CLK to the constant on-time module and the LOGIC control module LOGIC, and outputs a sawtooth wave signal RAMP to a positive input end of the comparator module PWMCMP; the constant conduction time module is respectively connected with the input end of the control circuit, the output end of the control circuit and the first input end of the gating module T1; a second input terminal of the gating module T1 receives the PWM signal of the comparator module PWMCMP; the LOGIC control module LOGIC receives the pulse clock signal CLK and the output of the gating module T1, and generates a driving signal DR1 to the driving module DRIVER; the second divider resistor RFB2 is connected between the other end of the first divider resistor RFB1 and the ground; the positive input end of the error amplifier module EAMP is connected with the reference voltage, the error amplifier module EAMP is connected with the connection point of the first voltage-dividing resistor RFB1 and the second voltage-dividing resistor RFB2, and the output end of the error amplifier module EAMP is connected with the negative input end of the comparator module PWMCMP.

The constant on-time module is configured to set an on-time of the first transistor Q1 under a light load, and the gating module T1 is configured to switch the on-control signal of the first transistor Q1.

In the embodiment of the utility model, a current zero comparison module ZCCDCMP is used for judging whether the system enters a light load mode or not, and when the system enters the light load mode; the Constant On-Time module is used to generate a Constant On-Time (Constant On Time) value TON, which is proportional to the difference between V2 and V1 and inversely proportional to V2 itself.

And, the constant on-time value may be:

TON ═ TOSC (V2-V1)/V2; or

TON>TOSC*(V2-V1)/V2

Wherein, the TOSC is the period time of the fixed period frequency signal of the PWM generating module.

Specifically, the LOGIC control module LOGIC may be an RS latch, and when the LOGIC control module LOGIC operates in the light load mode, the gating module T1 performs RS latch on the TON signal of the constant on-time value instead of the PWM signal and the pulse clock signal CLK through the LOGIC control module LOGIC to generate a signal DR 1; when the driver operates in the heavy load mode, the strobe block T1 still uses the PWM signal and the clock signal CLK to perform RS latch through the LOGIC control block LOGIC to generate the signal DR 1. The signal DR1 generates the signal CLKP and the signal CLKN through the DRIVER module DRIVER.

In the embodiment of the present invention, when the system operates in both the light load mode and the heavy load mode, the on-time of the first transistor Q1 is the same, and when the system operates in the light load mode, the output signal zcdccmp of the current zero crossing comparison module ZCDCMP is at a high level, and the on-control signal of the first transistor Q1 is determined by the output of the constant on-time module; when the module is operated in the heavy load mode, the output signal zcdccmp of the zero-crossing current comparison module zcdccmp is at a low level, and the turn-on control signal of the first transistor Q1 is determined by the output of the comparator module PWMCMP.

In an embodiment of the present invention, the gating module T1 may also be implemented by a specific circuit in a dashed box of fig. 3, as shown in the figure, the gating module T1 may include a logic inverter INV1, a transmission gate TG1, and a transmission gate TG 2; an input end of the logic inverter INV1, a lower gate of the transmission gate TG1 and an upper gate of the transmission gate TG2 receive the signal ZC, and an output end of the logic inverter INV1, an upper gate of the transmission gate TG1 and a lower gate of the transmission gate TG2 are connected together; the output ends of the transmission gate TG1 and the transmission gate TG2 are connected together, and the output result is input into a LOGIC control module LOGIC; the constant on-time module controls the on-off of the transmission gate TG1, and the output signal PWM of the comparator module PWMCMP controls the on-off of the transmission gate TG 2; when the light load mode is entered, the signal ZC is high, the transmission gate TG1 is turned on, and the transmission gate TG2 is turned off; when entering the heavy load mode, ZC is low, transmission gate TG2 is turned on, and transmission gate TG1 is turned off.

Referring to fig. 4, fig. 4 is a schematic diagram of a constant on-time module in a control circuit of the DC/DC boost system according to the present invention. In an embodiment of the present invention, the constant on-time module includes a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a third PMOS transistor Q3, a fourth PMOS transistor Q4, a resistor RTON for generating a charging current for setting the TON time, a charging capacitor CTON for setting the TON time, an operational amplifier OP1, and a comparator TONCMP for generating the TON time.

The positive end of the operational amplifier OP1 is connected with the output end of the control circuit, the negative end of the operational amplifier OP1 is connected with the source electrode of the fifth NMOS transistor Q5, and the output end of the operational amplifier OP1 is connected with the grid electrode of the fifth NMOS transistor Q5; the resistor RTON is connected between the source electrode of the fifth NMOS transistor Q5 and the ground terminal; the drains of the fifth NMOS transistor Q5, the sixth NMOS transistor Q6, the third PMOS transistor Q3, and the fourth PMOS transistor Q4 are connected to the positive terminal of the comparator TONCMP, the negative terminal of the comparator TONCMP is connected to the voltage VC, the sources and gates of the third PMOS transistor Q3 and the fourth PMOS transistor Q4 are connected together, the charging capacitor CTON is connected between the drain and the source of the sixth NMOS transistor Q6, and the gate of the sixth NMOS transistor Q6 is connected to the signal CLKN.

Wherein, the voltage VC is the voltage of the negative terminal of the comparator TONCMP, and the value is V2-V1; the operational amplifier OP1 is for generating a current I1 flowing through the fifth NMOS transistor Q5 and the third PMOS transistor Q3; i1 ═ V2/RTON; the fourth PMOS transistor Q4 is a mirror image of the third PMOS transistor Q3, IQ4 is K IQ3, and K is a ratio of a current flowing through the fourth PMOS transistor Q4 to a current flowing through the third PMOS transistor Q3.

TON time is the constant on time of the first transistor Q1; the TOSC is the working frequency of the oscillator module OSC, and the values of the charging resistor RTON and the charging capacitor CTON need to meet the following requirements:

TON＝TOSC*(V2-V1)/V2

when the signal CLKN is at a high level, the sixth NMOS transistor Q6 is turned off, and the capacitor CTON is charged by the current of the fourth PMOS transistor Q4, whose voltage signal is VRC;

when the upper voltage VRC of the capacitor CTON is greater than the negative terminal signal VC of the comparator TONCMP; the comparator TONCMP generates a comparison signal TON1, signal TON1 is the output signal of the constant on-time module.

Therefore, it can be seen from the above technical solutions that, in the light load mode, by removing the Fixed minimum ON-Time module (Fixed MIN ON Time) and adding the Constant ON-Time module and the gating module T1, the system operates in the Fixed Frequency (Fixed Frequency) mode under the heavy load mode and operates in the Constant ON-Time (Constant ON Time) mode under the light load mode.

In some embodiments of the present invention, the Fixed minimum ON Time module (Fixed MIN ON Time) and the constant ON Time module may exist simultaneously, and when the constant ON Time module produces less Time than the Fixed minimum ON Time module (Fixed MIN ON Time), the constant ON Time of the first transistor Q1 is greater.

Example 2

In the embodiment of the present invention, by adding an on-off pre-control module, when the current flowing through the first transistor Q1 is greater than a preset current threshold, the on-off pre-control module controls the gating module T1 to receive the output of the constant on-time module. That is, the on-time of the first transistor Q1 is not only required to satisfy TON > -TOSC (V2-V1)/V2, but also required to satisfy the on-current of the on-Q1 reaching a set current value.

Specifically, the on-off pre-control module comprises a logic gate and a current monitoring module; the current detection module comprises a zeroth transistor Q0, a comparator circuit CLCMP and a current source IOC; an input of the logic gate is connected to the output of the constant on-time module, an input of the logic gate is connected to the output of the comparator circuit CLCMP, the zeroth transistor Q0 is a mirror transistor of the first transistor Q1 for mirroring the current of the first transistor Q1, and the current of the current source IOC is a current threshold; when the current of the zeroth transistor Q0 is greater than IOC, the comparator circuit CLCMP controls the logic and gate to allow the output of the constant on-time module.

Referring to fig. 5, fig. 5 is a schematic diagram of a control circuit of a DC/DC boost system according to another preferred embodiment of the present invention. As shown, the control circuit of the DC/DC boost system includes a first voltage dividing resistor RFB1, a second voltage dividing resistor RFB2, a voltage stabilizing capacitor C1 for V1, a voltage stabilizing capacitor C2 for V2, a voltage source DC, an inductor L1, a LOGIC and gate, a first transistor Q1, a second transistor Q2, a constant on-time module, a gating module T1, an oscillator module OSC, an error amplifier module EAMP, a comparator module PWMCMP, a comparator module CLCMP, a zeroth transistor Q0, a LOGIC control module LOGIC, a drive module DRIVER, a reference current source IOC, and a current zero-crossing comparison module zcdccmp; the voltage V1 is the voltage signal at the input of the control circuit, the voltage V2 is the voltage signal at the output of the control circuit, and the voltage V1 is usually smaller than the voltage V2.

Specifically, the inductor L1 is connected between a node SW and the input end of the control circuit, the node SW is a connection point between one input end of the current zero-crossing comparison module zcdccmp and the drain of the first transistor Q1, one input end of the comparator module CLCMP and the drain of the second transistor Q2, and the source of the first NMOS transistor Q1 is connected to the ground; the voltage source DC and the voltage stabilizing capacitor C1 are connected in parallel between the input end of the control circuit and the grounding end; the output end of the control circuit is connected with the other input end of the current zero-crossing comparison module ZCCDCMP, one end of a voltage-stabilizing capacitor C2, one end of a first voltage-dividing resistor RFB1 and the source electrode of a second transistor Q2, and one end of a voltage-stabilizing capacitor C2 is connected with the ground end; the driving module DRIVER receives the output signal ZC of the current zero-cross comparison module zcdccmp and the output DR1 of the LOGIC control module LOGIC, and outputs a signal CLKP to the gate of the second transistor Q2 and a signal CLKN to the gate of the first transistor Q1; the oscillator module OSC receives the output of the current zero-crossing comparison module ZCCDCMP, outputs a pulse clock signal CLK to the constant on-time module and the LOGIC control module LOGIC, and outputs a sawtooth wave signal RAMP to the positive input end of the comparator module PWMCMP; the constant conduction time module is respectively connected with the input end of the control circuit, the output end of the control circuit and one input end of the logic gate; the output end of the logic AND gate is connected with the first input end of the gating module T1; a second input terminal of the gating module T1 receives the PWM signal of the comparator module PWMCMP; the LOGIC control module LOGIC receives the pulse clock signal CLK and the output of the gating module T1, and generates a driving signal DR1 to the driving module DRIVER; the second divider resistor RFB2 is connected between the other end of the first divider resistor RFB1 and the ground; the positive input end of the error amplifier module EAMP is connected with the reference voltage, the error amplifier module EAMP is connected with the connection point of the first divider resistor RFB1 and the second divider resistor RFB2, and the output end of the error amplifier module EAMP is connected with the negative input end of the comparator module PWMCMP; the other input end of the comparator module CLCMP receives the current of the reference current source IOC and is connected with the drain of the zeroth transistor Q0, the source of the zeroth transistor Q0 is grounded, and the gate of the zeroth transistor Q0 is connected with the signal CLKN; the output terminal of the comparator module CLCMP is connected with the other input terminal of the logic gate.

The constant on-time module outputs a signal TON1 for setting the on-time of the first transistor Q1 under light load; the gating module T1 is used for switching the turn-on control signal of the first transistor Q1, so that the turn-on time of the first transistor Q1 is the same no matter whether the system operates in the light load mode or the heavy load mode; the comparator circuit CLCMP is used for detecting the current flowing through the first transistor Q1, and the zeroth transistor Q0 is a mirror tube of the first transistor Q1 and is used for mirroring the current of the first transistor Q1; when the current of the zeroth transistor Q0 is greater than IOC, the comparator circuit CLCMP inverts.

When the system works in a light load mode and a heavy load mode, the conduction time of the first transistor Q1 is the same, when the system works in the light load mode, the output signal ZC of the zero-crossing current comparison module ZCCDCMP is at a high level, and the conduction control signal of the first transistor Q1 is determined by the output of the constant conduction time module; when the module is operated in the heavy load mode, the output signal zcdccmp of the zero-crossing current comparison module zcdccmp is at a low level, and the turn-on control signal of the first transistor Q1 is determined by the output of the comparator module PWMCMP.

As with embodiment 1, in the embodiment of the present invention, a current zero comparison module zcdccmp is used to determine whether the system enters a light load mode, and when the system enters the light load mode; the Constant On-Time module is used to generate a Constant On-Time (Constant On Time) value TON, which is proportional to the difference between V2 and V1 and inversely proportional to V2 itself, and the Constant On-Time value can be:

TON ═ TOSC (V2-V1)/V2; or

TON>TOSC*(V2-V1)/V2

Wherein, the TOSC is the period time of the fixed period frequency signal of the PWM generating module.

Specifically, the LOGIC control module LOGIC may be an RS latch, and when the LOGIC control module LOGIC operates in the light load mode, the gating module T1 performs RS latch on the TON signal of the constant on-time value instead of the PWM signal and the pulse clock signal CLK through the LOGIC control module LOGIC to generate a signal DR 1; when the driver operates in the heavy load mode, the gating module T1 still uses the PWM signal and the CLK signal to perform RS latch through the LOGIC control module LOGIC to generate the DR 1; the signal DR1 generates the signal CLKP and the signal CLKN through the DRIVER module DRIVER.

Similarly, the specific circuits of the constant on-time module and the gating module T1 in embodiment 1 can also be introduced to embodiment 2, and are not described herein again.

It should be noted that the positive terminal of the comparator module CLCMP is connected to the VSW signal (the VSW signal is the voltage value of the SW node); the negative end of the voltage-controlled rectifier is connected with a voltage VQ0, VQ0 is IOC Ron _ Q0; ron _ Q0 is the on-resistance of the zeroth NMOS transistor Q0.

When the voltage VSW is greater than the voltage VQ0, the output signal VCL of the comparator CLCMP goes high, and the output signal TON1 of the constant on-time module can pass through the logic gate and the gating module T1 to control the turn-off of the Q1 terminal.

That is, the first transistor Q1 is turned on not only for TON > -TOSC (V2-V1)/V2, but also for the on current of the first NMOS transistor Q1 to reach a set current value ICL-IOC 1; m1 is a ratio of the first transistor Q1 and the zeroth transistor Q0.

Referring to fig. 6, fig. 6 is a schematic waveform diagram of the CLKN signal TON of the DC/DC boost system in fig. 3 or fig. 5. As shown in the figure, the CLKN signal TON of the DC/DC boost system of the present invention is fixed, which is very beneficial to the formation of light-load energy-saving waveform; and the TON value is related to the power input voltage V1 and the power output V2, so that the on-time of the first transistor Q1 is consistent with the on-time when the system is stable under heavy load. Namely, the CLKN signal TON of the circuit of the utility model is fixed, and the system is stable; the TON value is associated with V1 and V2, which is consistent with the ON Time value at reload.

The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims (10)

1. A control circuit of a DC/DC boosting system is used for boosting an input direct-current power supply voltage signal V1 into a direct-current power supply voltage signal V2 and outputting the direct-current power supply voltage signal V2; it is characterized by comprising:

a first transistor Q1, a second transistor Q2, and an inductor L1; the inductor L1 is connected between the input terminal of the DC power supply voltage signal V1 and the drain connection point SW of the first transistor Q1 and the second transistor Q2; the source electrode of the first transistor Q1 is grounded, and the source electrode of the second transistor Q2 is connected with the output end of the direct-current power supply voltage signal V2;

the current zero-crossing comparison module ZCCDCMP detects the load working mode of the boosting system and outputs a signal ZC according to the power supply voltage signal V1 and the power supply voltage signal V2; one input end of the direct current power supply is connected with a contact point SW, and the other input end of the direct current power supply is connected with the output end of the direct current power supply voltage signal V2;

the PWM generating module is used for generating a PWM signal and a fixed period frequency signal;

the constant on-time module is used for generating fixed on-time related to the power supply voltage signal V1 and the power supply voltage signal V2 in a proportional relation according to the detection result of the load working mode obtained by the current zero-crossing comparison module ZCCDCMP and outputting a corresponding control signal;

a gating module T1, receiving the detection result of the current zero crossing comparison module zcdccmp load operation mode, and outputting the PWM signal generated by the PWM generation module if the detection result is the heavy load operation mode; if the detection result is in a light load working mode, outputting a signal output by the constant conduction time module;

and the boost system driving control module is used for receiving the output of the gating module T1 and a fixed period frequency signal, and generating a signal CLKP for controlling the on-off of the second transistor Q2 and a signal CLKN for controlling the on-off of the first transistor Q1 so as to ensure that the on-off time of the first transistor Q1 is the fixed on-off time under light load.

2. A control circuit of a DC/DC boost system according to claim 1; the constant on-time control circuit is characterized by further comprising an on-off pre-control module, wherein when the current flowing through the first transistor Q1 is larger than a preset current threshold, the on-off pre-control module controls the gating module T1 to receive the output of the constant on-time module.

3. A control circuit of a DC/DC boost system according to claim 2; the on-off pre-control module is characterized by comprising a logic gate and a current monitoring module; the current detection module comprises a zeroth transistor Q0, a comparator circuit CLCMP and a current source IOC; an input of the logic gate is connected to the output of the constant on-time module, an input of the logic gate is connected to the output of the comparator circuit CLCMP, the zeroth transistor Q0 is a mirror transistor of the first transistor Q1 for mirroring the current of the first transistor Q1, and the current of the current source IOC is a current threshold; when the current of the zeroth transistor Q0 is greater than IOC, the comparator circuit CLCMP controls the logic gate to allow the output of the constant on-time module.

4. A control circuit of a DC/DC boost system according to claim 1; the constant on-time TON of the first transistor Q1 is:

TON is greater than or equal to TOSC (V2-V1)/V2

Wherein, the TOSC is the period time of the fixed period frequency signal of the PWM generating module.

5. A control circuit of the DC/DC boost system of claim 1; the constant on-time control circuit is characterized by further comprising a fixed minimum on-time module, and when the time generated by the constant on-time module is smaller than the fixed minimum on-time module, the constant on-time of the first transistor Q1 under light load is longer.

6. A control circuit of a DC/DC boost system according to any one of claims 1 to 5; the gating module T1 comprises a logic inverter INV1, a transmission gate TG1 and a transmission gate TG 2; the input end of the logic inverter INV1, the lower gate of the transmission gate TG1 and the upper gate of the transmission gate TG2 receive the output signal ZC of the zero-crossing current comparison module zcdccmp, and the output end of the logic inverter INV1, the upper gate of the transmission gate TG1 and the lower gate of the transmission gate TG2 are connected together; the output ends of the transmission gate TG1 and the transmission gate TG2 are connected together, and the output result is input into the boosting system driving control module; the on-off of the transmission gate TG1 controls the on-off of the constant on-time module, and the on-off of the transmission gate TG2 controls the on-off of a signal PWM; when entering the light load mode, the transmission gate TG1 is conducted, and the transmission gate TG2 is closed; when entering the heavy load mode, the transmission gate TG2 is turned on, and the transmission gate TG1 is turned off.

7. A control circuit of a DC/DC boost system according to any one of claims 1 to 5; the constant on-time module comprises a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a third PMOS transistor Q3, a fourth PMOS transistor Q4, a resistor RTON for generating a charging current for setting the TON time, a charging capacitor CTON for setting the TON time, an operational amplifier OP1 and a comparator TONCMP for generating the TON time;

the positive end of the operational amplifier OP1 is connected with the output end of the control circuit, the negative end of the operational amplifier OP1 is connected with the source electrode of the fifth NMOS transistor Q5, and the output end of the operational amplifier OP1 is connected with the grid electrode of the fifth NMOS transistor Q5; the resistor RTON is connected between the source of the fifth NMOS transistor Q5 and the ground terminal; the drains of the fifth NMOS transistor Q5, the sixth NMOS transistor Q6, the third PMOS transistor Q3, and the fourth PMOS transistor Q4 are connected to the positive terminal of the comparator TONCMP, the negative terminal of the comparator TONCMP is connected to the voltage VC, the sources and gates of the third PMOS transistor Q3 and the fourth PMOS transistor Q4 are connected to each other, the charging capacitor CTON is connected between the drain and the source of the sixth NMOS transistor Q6, and the gate of the sixth NMOS transistor Q6 is connected to the signal CLKN; wherein, the voltage VC is the negative terminal voltage of the comparator TONCMP, and the value is V2-V1;

when the signal DR1 is at a high level, the sixth NMOS transistor Q6 is turned off, and the capacitor CTON is charged by the current of the fourth PMOS transistor Q4, and the voltage signal thereof is VRC;

when the upper voltage VRC of the capacitor CTON is greater than the negative terminal signal VC of the comparator TONCMP; the comparator TONCMP generates a comparison signal TON1, the signal TON1 is the output signal of the constant on-time module.

8. The control circuit of the DC/DC boost system according to claim 1, wherein the PWM generating module comprises an error amplifier module EAMP, a comparator module PWMCMP and an oscillator OSC, a positive input of the error amplifier module EAMP is connected to a reference voltage, another input of the error amplifier module EAMP is connected to a divided voltage of the output voltage V2, an output of the error amplifier module EAMP is connected to an input of the comparator module PWMCMP; the oscillator OSC provides a sawtooth wave signal to another input terminal of the comparator module PWMCMP according to the signal ZC and provides a fixed period frequency to the boost system drive control module, and an output terminal of the comparator module PWMCMP is connected to the gate module T1.

9. The control circuit of the DC/DC boost system according to claim 1, wherein said boost system drive control module includes a LOGIC control module LOGIC receiving a pulse clock signal CLK and an output of said gating module T1, generating a drive signal DR1 to said drive module DRIVER, and a drive module DRIVER outputting a signal CLKP and a signal CLKN.

10. The control circuit of the DC/DC boosting system according to claim 1, further comprising a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 is connected in parallel between the input terminal of the DC power voltage signal V1 and a ground terminal GND; the second capacitor C2 is connected in parallel between the output terminal of the dc power voltage signal V2 and the ground terminal GND.

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