CN111312135A - Source driver and operating method thereof - Google Patents
Source driver and operating method thereof Download PDFInfo
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- CN111312135A CN111312135A CN201811516972.0A CN201811516972A CN111312135A CN 111312135 A CN111312135 A CN 111312135A CN 201811516972 A CN201811516972 A CN 201811516972A CN 111312135 A CN111312135 A CN 111312135A
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- 238000011017 operating method Methods 0.000 title description 3
- 238000011084 recovery Methods 0.000 claims abstract description 47
- 238000001514 detection method Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000012549 training Methods 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 101100028908 Lotus japonicus PCS3 gene Proteins 0.000 description 1
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- 101100493726 Phalaenopsis sp. BIBSY212 gene Proteins 0.000 description 1
- 101100030895 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RPT4 gene Proteins 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
A source driver and a method of operating the same. In the source driver, the clock data recovery circuit is used for receiving an original data signal from an external device and generating a clock signal and a first data signal according to the original data signal. The digital circuit receives a clock signal and a first data signal and generates a power-off signal according to the first data signal. The signal detection circuit is used for receiving a control signal from an external device and generating a starting power supply signal according to the control signal. The power control circuit powers off the clock data recovery circuit according to the power-off signal, and powers back the clock data recovery circuit according to the power-on signal.
Description
Technical Field
The present invention relates to a display device, and more particularly, to a source driver and a method of operating the same.
Background
With the progress of electronic technology, consumer electronics have become a necessary tool in people's life. There is also a trend to provide high quality display devices on consumer electronics products in order to provide good human-machine interfaces. Reducing the power consumption of the display device during the non-display time interval will be the subject of those skilled in the art.
Disclosure of Invention
The invention provides a source driver and an operation method thereof, which can effectively reduce the power consumption of the source driver in a non-display time interval.
The source driver of the invention comprises a Clock Data Recovery (CDR) circuit, a digital circuit, a signal detection circuit and a power supply control circuit. The clock data recovery circuit is used for receiving an original data signal from an external device and generating a clock signal and a first data signal according to the original data signal. The digital circuit is coupled to the clock data recovery circuit to receive the clock signal and the first data signal and generate a power-off signal according to the first data signal. The signal detection circuit is used for receiving a control signal from an external device and generating a starting power supply signal according to the control signal. The power control circuit is coupled to the digital circuit to receive the power-off signal and coupled to the signal detection circuit to receive the power-on signal, wherein the power control circuit powers off the clock data recovery circuit according to the power-off signal, and the power control circuit powers back the clock data recovery circuit according to the power-on signal.
The operation method of the invention comprises the following steps: generating a clock signal and a data signal by a clock data recovery circuit according to the original data signal; generating a power-off signal by the digital circuit according to the first data signal; generating a starting power supply signal by a signal detection circuit according to the control signal; the power supply control circuit powers off the clock data recovery circuit according to the power supply cutting signal; the clock data recovery circuit is powered back by the power control circuit according to the starting power signal.
In view of the above, the source driver according to the embodiments of the invention may be powered down by the power control circuit according to the power signal being turned off to enable at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit. And the power control circuit is used for enabling at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit to be powered back according to the starting power signal. Therefore, the source driver of the invention can further reduce the overall power consumption of the source driver when operating in the non-display time interval.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a block diagram of a source driver according to an embodiment of the invention.
Fig. 2 is a schematic diagram illustrating a signal timing diagram of the source driver shown in fig. 1 according to an embodiment of the invention.
Fig. 3 is a flowchart of an operating method of a source driver according to an embodiment of the invention.
Detailed Description
The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through some other device or some connection means. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. Components/parts/steps in different embodiments using the same reference numerals or using the same terms may be referred to one another in relation to the description.
Fig. 1 is a block diagram of a source driver 100 according to an embodiment of the invention. The source driver 100 receives the original data signal TX and the control signal CS from the external device 160, and drives the display panel 170 to display an image according to the received original data signal TX and the control signal CS. Specifically, the external device 160 of the present embodiment may include a Timing Controller (TCON). In this embodiment, the external device 160 may generate a raw data signal TX and a control signal CS to the source driver 100, wherein the raw data signal TX includes display data required to be displayed by the display panel 170, and the control signal CS indicates a valid data period and an invalid data (e.g., training pattern) period in the raw data signal TX. Generally, an invalid data period is arranged after a vertical blanking period (vertical blanking period) (before a transmission period of valid frame data). Therefore, the control signal CS carries phase (time point) information of "the vertical blanking period has ended".
Referring to fig. 1, the source driver 100 includes a clock data recovery circuit 110, a digital circuit 120, a signal detection circuit 130, a power control circuit 140, and a driving circuit 150. The power control circuit 140 is configured with a power on/off reset (POFR) circuit. The clock data recovery circuit 110 is configured to resolve the clock signal CLK and the data signal DS1 carried in the original data signal TX. The data signal DS1 may include pixel data, a vertical blanking start signal VBK, a line latch signal, and other control signals, but the embodiment is not limited thereto. In general, the vertical blanking start signal VBK may indicate/define a start phase (start time point) of one vertical blanking period.
The digital circuit 120 of the present embodiment may be, for example, a controller or a data processor, but the present invention is not limited thereto. The digital circuit 120 is coupled to the clock data recovery circuit 110 to receive the clock signal CLK and the data signal DS 1. Digital circuit 120 may process data signal DS1 to generate a processed data signal DS2, such as pixel data. The digital circuit 120 may also generate a power-off signal CPS in dependence on the data signal DS 1. For example, in the present embodiment, the digital circuit 120 may detect the vertical blanking start signal VBK in the data signal DS1, and generate the power shutoff signal CPS to the power control circuit 140 according to the vertical blanking start signal VBK. In other embodiments, the digital circuit 120 may detect other information in the data signal DS1 and generate the power-off signal CPS in dependence on the other information.
The driving circuit 150 is coupled to the clock data recovery circuit 110 for receiving the clock signal CLK. The driving circuit 150 is also coupled to the digital circuit 120 to receive the data signal DS 2. The driving circuit 150 can generate the source driving signals S1 Sn according to the clock signal CLK and the data signal DS2, and the driving circuit 150 can drive the display panel 170 by using the source driving signals S1 Sn. The present embodiment does not limit the implementation of the driving circuit 150. For example, in some embodiments, the driving circuit 150 may include a Shift Register (Shift Register), a Data Register (Data Register), a Level Shifter (Level Shifter), a Digital-to-analog converter (DAC), and an Output Buffer (Output Buffer), which are well known to those skilled in the art, and the operation of each component is not described herein.
On the other hand, the signal detection circuit 130 is coupled to the external device 160 to receive the control signal CS. The control signal CS carries the phase (time point) information of "the vertical blanking period has ended", so that the signal detection circuit 130 can generate the start power signal SPS according to the control signal CS. For example, in some application scenarios, the control signal CS having a first logic level (e.g., high level) may indicate a period of valid data in the original data signal TX, and the control signal CS having a second logic level (e.g., low level) may indicate a period of invalid data (e.g., training pattern) in the original data signal TX. Based on this, the signal detection circuit 130 may detect a falling edge of the control signal CS and generate the power-on/power-off reset circuit to start the power signal SPS to the power control circuit 140 according to the falling edge of the control signal CS. In other application scenarios, the control signal CS with a low level may indicate a period of valid data in the original data signal TX, and the control signal CS with a high level may indicate a period of invalid data (e.g. training pattern) in the original data signal TX. Based on this, the signal detection circuit 130 can detect the rising edge of the control signal CS and generate the power-on/power-off reset circuit for starting the power supply signal SPS to the power supply control circuit 140 according to the rising edge of the control signal CS.
The power-on/power-off reset circuit of the power control circuit 140 is coupled to the digital circuit 120 to receive the power-off signal CPS. The power-on/power-off reset circuit of the power control circuit 140 is coupled to the signal detection circuit 130 to receive the start power signal SPS. The power-up/power-down reset circuit of the power control circuit 140 may control the power supply of the clock data recovery circuit 110, the digital circuit 120 and/or the driving circuit 150. The power control circuit 140 can provide power control signals PCS1, PCS2 and PCS3 to the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 respectively according to the power-off signal CPS and the power-on signal SPS, so as to control the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 to operate in a power-off state or a power-restoration state. For example, the power control circuit 140 may power down the clock data recovery circuit 110 during the non-display time interval and power down the clock data recovery circuit 110 during the display time interval.
For details of the operation of the source driver 100, please refer to fig. 1 and fig. 2 simultaneously. Fig. 2 is a schematic diagram illustrating a signal timing diagram of the source driver 100 shown in fig. 1 according to an embodiment of the invention. The non-display time interval TND includes a vertical blanking interval and/or other times according to design requirements. The embodiment shown in fig. 2 will take the vertical blanking interval as an example of the non-display time interval TND. In detail, in the present embodiment, the digital circuit 120 may detect the vertical blanking start signal VBK of the data signal DS1 in the vertical blanking time interval TBK. The vertical blanking start signal VBK means the start of a vertical blanking period (non-display time interval TND). Therefore, the digital circuit 120 sets the power-off signal CPS to be in an enabled (e.g., high voltage level) state during the vertical blanking time interval TBK according to the vertical blanking start signal VBK. At the same time, the signal detection circuit 130 may receive the control signal CS. Since the control signal CS is still at the high level during the vertical blanking period, the signal detection circuit 130 can keep the power-on signal SPS in a disabled (e.g., low voltage level) state.
In the case where the power-off signal CPS is in the enabled state, the power-on/power-off reset circuit of the power control circuit 140 can know that the power-off reset event has occurred. Therefore, the power-up/power-down reset circuit of the power control circuit 140 can provide the power control signals PCS 1-PCS 3 with a disabled (e.g., low voltage level) state to the corresponding clock data recovery circuit 110, digital circuit 120 and driving circuit 150 according to the power-off signal CPS, so that the clock data recovery circuit 110, digital circuit 120 and driving circuit 150 are powered off.
On the other hand, in the embodiment shown in fig. 2, the control signal CS with a high level may indicate a period of valid data in the original data signal TX, and the control signal CS with a low level may indicate a period of invalid data (e.g., training pattern) in the original data signal TX. The falling edge of the control signal CS means the end of the vertical blanking period (non-display time interval TND). Therefore, the signal detecting circuit 130 can detect the falling edge of the control signal CS and generate the power-up/power-down reset signal SPS having an enabled (e.g., high voltage level) state to the power control circuit 140 at the end time TEND of the non-display time interval TND according to the falling edge of the control signal CS.
In the case where the power-on signal SPS is enabled, the power-on/power-off reset circuit of the power control circuit 140 may know that a power-on reset event occurs. Therefore, the power-up/power-down reset circuit of the power control circuit 140 can provide the power control signals PCS 1-PCS 3 with an enabled (e.g., high voltage level) state to the corresponding clock data recovery circuit 110, digital circuit 120 and driving circuit 150 according to the power-up signal SPS, so that the clock data recovery circuit 110, digital circuit 120 and driving circuit 150 are reset.
In other words, in the present embodiment, the source driver 100 can determine the start and the end of the vertical blanking period (the non-display time interval TND) through the digital circuit 120 and the signal detection circuit 130. When the digital circuit 120 detects the start of the vertical blanking period (non-display time interval TND) according to the vertical blanking time interval TBK, the digital circuit 120 may trigger a power-off reset event of the power-on/power-off reset circuit of the power control circuit 140 by cutting off the power signal CPS. Therefore, the power-up/power-down reset circuit of the power control circuit 140 can power down the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 to reduce the power consumption of the source driver 100. When the signal detection circuit 130 detects the end of the vertical blank period (the non-display time interval TND) according to the falling edge of the control signal CS, the signal detection circuit 130 may trigger the power-on reset event of the power-on/power-off reset circuit of the power control circuit 140 by activating the power signal SPS. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can perform a power recovery operation on the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150, so that the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 restart the related circuits at the end time TEND.
Then, when the source driver 100 operates in the display time interval TD, the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 operate under the normal operation state according to the corresponding power control signals PCS 1-PCS 3, so that the driving circuit 150 can normally generate the source driving signals S1-Sn according to the clock signal CLK and the data signal DS 2. The driving circuit 150 may drive the display panel 170 by the source driving signals S1 to Sn, so that the display panel 170 displays a picture in the display time interval TD.
It should be noted that, in the present embodiment, a person skilled in the art can determine which internal components of the source driver 100 are powered off or powered back on according to the design requirement of the source driver 100. For example, when the source driver 100 operates in the non-display time interval TND (e.g., the vertical blanking interval), the power control circuit 140 of the present embodiment may power down at least one or all of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the power-off signal CPS. In contrast, when the non-display time interval TND ends, the power control circuit 140 may reset at least one or all of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the power-on signal SPS.
As can be seen from the above description, the power control circuit 140 of the source driver 100 according to the present embodiment can cut off the power of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 in the non-display time interval TND according to the power cut-off signal CPS, so as to reduce the power consumption of the source driver 100. On the other hand, when the non-display time interval TND ends, the power control circuit 140 of the source driver 100 may recover the power of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the power-on signal SPS, so that the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 may start the related circuit operations again after the ending time point TEND of the non-display time interval TND.
Fig. 3 is a flowchart illustrating an operation method of the source driver 100 according to an embodiment of the invention. Referring to fig. 1 and fig. 3, in step S310, the source driver 100 may generate a clock signal CLK and a data signal DS1 according to the original data signal TX through the clock data recovery circuit 110. In step S320, the source driver 100 may generate the power-off signal CPS by the digital circuit 120 according to the data signal DS 1. In step S330, the source driver 100 may power down the clock data recovery circuit 110 by the power control circuit 140 according to the power-off signal CPS.
Next, in step S340, the source driver 100 may generate the start power signal SPS through the signal detection circuit 130 according to the control signal CS. In step S350, the source driver 100 can power back the clock data recovery circuit 110 via the power control circuit 140 according to the start power signal SPS.
Details of the steps are given in the foregoing examples and embodiments, and are not repeated herein.
In summary, the source driver according to the embodiments of the invention can be powered off by the power control circuit according to the power-off signal, so that at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit are powered off. And the power control circuit is used for enabling at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit to be powered back according to the starting power signal. Therefore, the source driver according to the embodiments of the invention can reduce the overall power consumption of the source driver during the non-display time interval, thereby achieving the power saving effect.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (8)
1. A source driver, comprising:
the clock data recovery circuit is used for receiving an original data signal from an external device and generating a clock signal and a first data signal according to the original data signal;
a digital circuit coupled to the clock data recovery circuit to receive the clock signal and the first data signal and generate a power-off signal according to the first data signal;
the signal detection circuit is used for receiving a control signal from the external device and generating a starting power supply signal according to the control signal; and
a power control circuit coupled to the digital circuit to receive the power-off signal and coupled to the signal detection circuit to receive the power-on signal, wherein the power control circuit powers off the clock data recovery circuit according to the power-off signal, and the power control circuit powers back the clock data recovery circuit according to the power-on signal.
2. The source driver as claimed in claim 1, wherein the power control circuit powers off the clock data recovery circuit during a non-display time interval.
3. The source driver of claim 2, wherein the non-display time interval comprises a vertical blanking period.
4. The source driver of claim 1, wherein the digital circuit detects a vertical blank start signal in the first data signal, and generates the power-off signal to the power control circuit according to the vertical blank start signal.
5. The source driver of claim 1, wherein the signal detection circuit detects a falling edge of the control signal, and generates the enable power signal to the power control circuit according to the falling edge of the control signal.
6. The source driver of claim 1, wherein the power control circuit further powers down the digital circuit in accordance with the power-off signal, and the power control circuit further powers back up the digital circuit in accordance with the power-on signal.
7. The source driver of claim 1, wherein the digital circuit outputs a second data signal in accordance with the first data signal, the source driver further comprising:
a driving circuit coupled to the clock data recovery circuit for receiving the clock signal and coupled to the digital circuit for receiving the second data signal, wherein the driving circuit is used for driving a display panel according to the second data signal;
the power supply control circuit also powers off the drive circuit according to the power supply cut-off signal, and the power supply control circuit also powers back the drive circuit according to the power supply start signal.
8. The source driver of claim 1, wherein the power control circuit comprises a power-on/power-off reset circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811516972.0A CN111312135B (en) | 2018-12-12 | 2018-12-12 | Source driver and operation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811516972.0A CN111312135B (en) | 2018-12-12 | 2018-12-12 | Source driver and operation method thereof |
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| CN111312135A true CN111312135A (en) | 2020-06-19 |
| CN111312135B CN111312135B (en) | 2024-01-19 |
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Cited By (2)
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| CN112951134A (en) * | 2021-04-20 | 2021-06-11 | 合肥京东方显示技术有限公司 | Clock recovery device, source electrode driving circuit, display panel and equipment |
| CN114220380A (en) * | 2022-02-22 | 2022-03-22 | 深圳通锐微电子技术有限公司 | Calibration digital circuit, source driver and display panel |
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| CN114220380A (en) * | 2022-02-22 | 2022-03-22 | 深圳通锐微电子技术有限公司 | Calibration digital circuit, source driver and display panel |
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| CN111312135B (en) | 2024-01-19 |
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