CN1617067A - Power saving control circuit for electronic device and its power saving method - Google Patents
Power saving control circuit for electronic device and its power saving method Download PDFInfo
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- CN1617067A CN1617067A CN 200310124733 CN200310124733A CN1617067A CN 1617067 A CN1617067 A CN 1617067A CN 200310124733 CN200310124733 CN 200310124733 CN 200310124733 A CN200310124733 A CN 200310124733A CN 1617067 A CN1617067 A CN 1617067A
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Abstract
The power saving control circuit for electronic device has power source controlling circuit, vibrator, clock generator, holding circuit and multitask actuating module. After the electronic device enters the power saving mode, the vibrator is stopped in generating vibrating clock signal and the clock generator is stopped in generating work clock signal. The digital clock signal generated with the vibrating clock signal or the work clock signal is then stopped correspondingly. In addition, the power source controlling circuit may be also used to control the vibrator, the clock generator or the multitask actuating module to shut down the flash memory in the electronic device.
Description
Technical field
The present invention relates to a kind of power-saving control circuit and method, relate in particular to a kind of power-saving control circuit and method of electronic installation.
Background technology
Fig. 1 is the figure that the power supply control structure of known electronic installation (for example integrated circuit or specific use integrated circuit) is shown.Please refer to Fig. 1, has power control circuit 101 in the known electronic installation, it receives a dagital clock signal DCLK with control clock generation circuit 103, comes clocking CLK1, CLK2, CLK3, CLK4 each assembly (for example digital circuit) 105,107,109,111 to the electronic installation.When entering power down modes such as standby (Stand-by) state or sleep (Sleep) state when known electronic installation, power control circuit 101 can stop clock signal CLK1, CLK2, CLK3, CLK4 by control clock generation circuit 103 one by one, temporarily to make assembly 105,107,109,111 power-offs (Power Down) reach purpose of power saving.
But, known power control circuit has individual shortcoming, exactly when electronic installation enters the battery saving mode of standby or sleep state etc., each can only be controlled the clock signal of each assembly closes, but but the power-off of power control circuit 101 can not be able to not be stopped to produce dagital clock signal DCLK because will receive external event.Therefore, the consumption of electric current can not further reduce.
Particularly, known electronic installation often also has internal memory, in order to assist the operation of each assembly outside circuit (numeral or simulation) waits.But, have only static RAM etc. itself to have the design of power-off, can be own own to being closed; And such as flash ROM etc., then do not have such design to close voluntarily, and necessarily need extraneous circuit to wait to control its operation or close.Therefore, the power supply of electronic installation control also must be special design circuit kits such as internal memory, and can not only increase cost but also flow process complexity with the circuit of the assembly of each receive clock signal of control shown in Figure 1.
Summary of the invention
Therefore, the invention provides a kind of electronic installation, when entering the state of battery saving mode, almost this electronic installation can be considered as the state of power-off.In addition, can close internal memory, not prepare circuit kit and do not need to be in particular internal memory with the circuit of closing each assembly.
The invention provides a kind of power-saving control circuit of electronic installation, have digital circuit in this electronic installation, and this power-saving control circuit comprises power control circuit, oscillator, clock generator and multitask activation module.At this, the obstructed oversampling clock signal of power control circuit moves, and can produce oscillation power signal, clock power signal and digital power signal respectively to oscillator, clock generator and multitask activation module, controls its operation or closes.Wherein, oscillator and clock generator determine whether wanting power-off according to oscillation power signal and clock power signal, in addition, oscillator can produce oscillating clock signal to clock generator, and clock generator produces the work clock signal according to oscillating clock signal more then.In addition, multitask activation module selects signal to select the work clock signal according to one or oscillating clock signal produces dagital clock signal, and determines whether exporting dagital clock signal to digital circuit according to the digital power signal; And power control circuit utilizes external signal to produce electric power starting (wake up).In addition, also can with can not be when closing clock in the digital circuit part out of service independently become and be connected to oscillator to receive the stick holding circuit of oscillating clock signal; And, power control circuit can also be sent to oscillation power signal, clock power signal and wherein at least one of digital power signal three the internal memory (as flash ROM) that digital circuit is therewith moved together, is will move or will close with control internal memory (as flash ROM).At this, multitask activation module can form by traffic pilot (Multiplexer) with door.
The invention provides the power-saving control circuit of another kind of electronic installation, have digital circuit in this electronic installation, power-saving control circuit of the present invention has then comprised oscillator, clock generator, frequency divider and traffic pilot.Wherein, oscillator produces oscillating clock signal to frequency divider and clock generator.Clock generator produces the work clock signal according to oscillating clock signal, frequency divider then with the frequency of the oscillating clock signal that receives divided by N (positive integer) to produce sub-frequency clock signal.In addition, traffic pilot can according to select signal select oscillating clock signal, work clock signal and sub-frequency clock signal three one of them, produce dagital clock signal to digital circuit.And, can also transmit the internal memory (as flash ROM) that signal moves together to digital circuit therewith from traffic pilot or Digital Circuit Signal, be will move or will close to control internal memory (as flash ROM).
The present invention also provides a kind of electricity saving method of electronic installation.This electronic installation has the digital circuit that the reception digital dock is normally moved, and under normal condition, can select the work clock signal produce dagital clock signal in the electronic installation.This electricity saving method comprises the following steps: to replace the work clock signal to produce dagital clock signal with oscillating clock signal at least, and the frequency of work clock signal is greater than the frequency of oscillating clock signal; Activation clock power signal stops to produce the work clock signal, and then activation digital power signal stops to produce dagital clock signal.And when external event took place, just activation recovered oscillating clock signal etc., made electronic installation recover normal condition.At this, activation can also be sent to the internal memory that moves with digital circuit with signal, with when stopping to produce dagital clock signal, in the lump with the power-off of internal memory.And, can also continue to receive the part that dagital clock signal comes operate as normal with needing in the digital circuit earlier, from the independent stick holding circuit that becomes of digital circuit; Only close dagital clock signal again and do not close oscillating clock signal, make digital circuit be closed but stick holding circuit operate as normal still.
The present invention also provides a kind of electricity saving method of electronic installation, and this electronic installation has the digital circuit that the reception digital dock is normally moved, and under normal condition, can select the work clock signal produce dagital clock signal in the electronic installation.This electricity saving method comprises the following steps: earlier the frequency of oscillating clock signal is used for producing sub-frequency clock signal divided by N (positive integer) at least, in the frequency of this oscillating clock signal frequency less than the work clock signal; Again according to the state of electronic installation, select the work clock signal or sub-frequency clock signal produces dagital clock signal, use for digital circuit.And take place as external event, just recover oscillating clock signal, make electronic installation recover normal condition.Certainly, when electronic installation has internal memory (as flash ROM), can also be according to the generation of sub-frequency clock signal, transmit signal to internal memory to close its power supply.
In brief, the present invention uses the power control circuit that does not move according to clock signal, therefore when electronic installation enters battery saving mode, can stop to produce dagital clock signal so that save more electric power.In addition on electronic installation can't cut out with the part that enters battery saving mode, for example dynamic RAM (DRAM) action that refreshes (Refresh), can with a stick holding circuit or directly receiving the lower clock signal of frequency with digital circuit move, can save electric power equally.And, when entering battery saving mode, can directly utilize the signal of closing digital circuit power-off at electronic installation with internal memory, and then can be with promote province's electrical efficiency than convenient mode.
Description of drawings
Fig. 1 is the figure that the power supply control structure of known CD-ROM drive is shown.
Fig. 2 is the calcspar that illustrates according to the power-saving control circuit of the electronic installation of a preferred embodiment of the present invention.
Fig. 3 A is the process flow diagram that illustrates according to the electricity saving method of the electronic installation of a preferred embodiment of the present invention.
Fig. 3 B is the process flow diagram that the electricity saving method of the electronic installation that replenishes a preferred embodiment of the present invention is shown.
Fig. 3 C is electronic installation that a preferred embodiment of the present invention is shown is reverted to the method for normal mode by battery saving mode a process flow diagram.
Fig. 3 D is another kind of electronic installation that a preferred embodiment of the present invention is shown is reverted to the method for normal mode by battery saving mode a process flow diagram.
Fig. 4 A is the calcspar that illustrates according to the power-saving control circuit of the electronic installation of another embodiment of the present invention.
Fig. 4 B is the calcspar that illustrates according to the micromodule of another embodiment of the present invention.
Fig. 5 A is the process flow diagram that illustrates according to the electricity saving method of the electronic installation of another embodiment of the present invention.
Fig. 5 B illustrates the process flow diagram that is reverted to the method for normal mode according to the electronic installation of another embodiment of the present invention by standby mode.
Fig. 6 A is the sequential chart that illustrates according to the optical drive power-saving control circuit of a preferred embodiment of the present invention.
Fig. 6 B is the sequential chart that illustrates according to the another kind of optical drive power-saving control circuit of a preferred embodiment of the present invention.
Fig. 6 C is the sequential chart that illustrates according to the electronic installation power-saving control circuit of another embodiment of the present invention.
The drawing reference numeral explanation
21,41: phase inverter
101,201: power control circuit
103: clock generation circuit
105,107,109,111: assembly
203,401: oscillator
205,403: clock generator
207: stick holding circuit
210: multitask activation module
212,407: traffic pilot
214,422: with door
221,409: digital circuit
223,411: flash ROM
405: frequency divider
420: micromodule
421: mini program controlling unit
S301, S303, S305, S307, S510, S520, S522, S524, S526, S528, S532, S530: the electricity saving method of electronic installation
S311, S313, S315, S317: the electricity saving method of electronic installation
S321, S323, S325, S327, S331, S333, S335, S337: electronic installation is reverted to the method for normal mode by battery saving mode
S541, S543, S545: electronic installation is reverted to the method for normal mode by standby mode
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiments more cited below particularly, and conjunction with figs. are described in detail below.
Fig. 2 is the calcspar that illustrates according to the power-saving control circuit of the electronic installation of one embodiment of the present invention.Please refer to Fig. 2, power control circuit 201 outputs signal to oscillator (OSC) 203 and clock generator 205.And, when electronic installation has flash ROM 223, can also output signal to flash ROM 223 (for example output to its chip and select (Chip Select) end CS); Power control circuit 201 all right output signals (for example by phase inverter 21) are to multitask activation module 210.In addition, oscillator 203 can also be coupled to stick holding circuit 207.At this, stick holding circuit 207 is coupled to digital circuit 221, in order to will can not part out of service being separated to stick holding circuit 207 in the digital circuit 221.And power control circuit 201 also can receive the external event of electronic installation, and then wakes the electronic installation that enters power down mode up.
Please continue with reference to Fig. 2, electronic installation provided by the present invention is under normal condition, and oscillator 203 produces oscillating clock signal CLK1 and gives clock generator 205 and multitask activation module 210.Clock generator 205 can produce work clock signal CLK2 according to oscillating clock signal CLK1 and give multitask activation module 210.At this moment, the digital power signal V1 that 210 meetings of multitask activation module are exported according to power control circuit 201 exports dagital clock signal DCLK and give digital circuit 221, and digital clock circuit 221 is exactly to receive dagital clock signal DCLK to move.In the present embodiment, multitask activation module 210 can be formed by traffic pilot 212 with 214 at door.Traffic pilot 212 selects to use oscillating clock signal CLK1 or work clock signal CLK2 to give and door 214 to produce clock signal CLK3 according to selecting signal SEL.Whether with 214 at door is to be enabled according to the digital power signal V1 that power control circuit 201 is exported, and determines whether exporting dagital clock signal DCLK and gives digital circuit 221.
In the present embodiment, when electronic installation for example entered battery saving mode such as standby mode or sleep pattern, the oscillating clock signal CLK1 that traffic pilot 212 can select oscillators 203 to be produced produced outputting oscillation signal CLK3.At this moment, power control circuit 201 activation clock power signal V2 make clock generator 205 power-offs, thereby stop to produce work clock signal CLK2.Then, power control circuit 201 can activation digital power signal V1, make can't be exported dagital clock signal DCLK with door 214 by forbidden energy, and digital circuit 221 are not because have supply thereby the power-off of dagital clock signal DCLK.At this moment, if have in the digital circuit 221 some functions for example refreshing of Dram be when need continuing clock signal to come operate as normal, then the circuit of these functions can be separated (can certainly be to duplicate out for stick holding circuit 207, just this part circuit can repeat), and the oscillating clock signal CLK1 that reception oscillator 203 is produced normally moves (just can not also turn off oscillator 203 this moment).In addition, in the present embodiment, in the time of power control circuit 201 activation digital power signal V1, chip selecting side CS that simultaneously can forbidden energy flash ROM 223 makes the power-off of flash ROM 223.
In addition, if functions all in the digital circuit 221 can enter battery saving mode, and make when digital circuit 221 can be fully with power-off power control circuit 201 activation oscillation power signal V3, with power-off, so that stop to produce oscillating clock signal CLK1 with oscillator 203.
In the present embodiment, when external event takes place, receive wake events by the power control circuit 201 that does not take clock, for example user's certain button or external device (ED) of pressing electronic installation needs exchanges data or the like, and then control generator (OSC) 203 and clock generator 205 etc., so that electronic installation recovers normal operation.
In the present embodiment, power control circuit 201 does not need to move by any clock signal.Therefore in the present embodiment, when electronic installation enters battery saving mode, when using stick holding circuit 207 operations if necessary, also have only running clock CLK1 to be produced.And the frequency of oscillating clock signal CLK1 is also low more than the frequency of work clock signal CLK2 and dagital clock signal DCLK, does not therefore more consume electric power.And if digital circuit 221 connects oscillating clock signal CLK1 and can stop to produce can be fully with power-off the time.At this moment, have only stick holding circuit 207, make that the electric power that consumes can be lower in operation.In addition, the electric power that flash ROM 223 in the electronic installation consumes is considerable, in the present embodiment, when electronic installation enters battery saving mode, oscillation power signal, clock power signal and wherein at least one of digital power signal three can be transferred to flash ROM 223 to close flash ROM 223, therefore can save more electric power.Particularly, present embodiment uses the signal of power control circuit 201 control generators (OSC) 203 or clock generator 205 etc. to close flash ROM 223, does not need to prepare in addition circuit kit fully, not only saves cost but also efficient.Certainly, this notion of this example can expand to any internal memory, is flash ROM and need not limit, or restriction is that input signal is to the chip selecting side.
In the present embodiment, flash ROM 223 comes its chip selecting side of forbidden energy CS by activation digital power signal V1, and makes its power-off.But present embodiment might not so design.Present embodiment can also utilize activation clock power signal V2 or oscillation power signal V3, or other control signal of activation makes the power-off of flash ROM 223, and those skilled in the art can be changed according to actual conditions.
Fig. 3 A is the process flow diagram that illustrates according to the electricity saving method of the electronic installation of another preferred embodiment of the present invention, and Fig. 6 A is the sequential chart that illustrates according to the optical drive power-saving control circuit of this preferred embodiment.Above embodiment is done an arrangement, the invention provides a kind of electricity saving method of CD-ROM drive, as Fig. 3 A and Fig. 6 A, at first in T1, shown in step S301, activation selects signal SEL to produce dagital clock signal DCLK to select oscillating clock signal CLK1; Shown in the step S303, activation clock power signal V1 stops to produce work clock signal CLK2 when T2 for another example; Carry out step S305 again, in T3, activation digital power signal V1 is to stop to produce dagital clock signal DCLK, and this moment, electronic installation entered battery saving mode.If shown in step S307, when T4, have in the external event generation, progressively turn off V1, V2 and SEL, so that electronic installation recovers normal condition.Must be emphatically, for avoiding the influence of unstable signal, opening or during shutdown signal when start signal (particularly), must wait until that usually this signal stablizes (be stabilized in fixed value or be stabilized in zero), could remove to open in regular turn or close next signal again.In addition, in the time of activation clock power signal V2, also can activation clock resetting signal RSTCLG, make work clock CLK2 to be reset.
Fig. 3 B illustrates the process flow diagram of electricity saving method that supplementary copy is invented the electronic installation of another preferred embodiment.Please refer to Fig. 2, Fig. 3 B and Fig. 6 A, when activation digital power signal, shown in step S311, judge whether that needing to receive dagital clock signal DCLK comes the circuit of operate as normal, for example the circuit of the refresh activity of Dram.If, then carry out step S313, receive oscillating clock signal CLK1 with stick holding circuit 207, and then need clock signal to come the function of work in the execute script digital circuit 221.And if not, then carrying out step S315, activation oscillation power signal V3 stops to produce oscillating clock signal CLK1.In addition, in the time of activation digital power signal V1, can shown in step S317, V1, V2 or V3 be transferred to flash ROM 223 to close its power supply along band.
To be electronic installation that a preferred embodiment of the present invention is shown revert to the process flow diagram of the method for normal mode by battery saving mode to Fig. 3 C, and Fig. 6 B system illustrates the sequential chart according to the another kind of optical drive power-saving control circuit of another preferred embodiment of the present invention.Please refer to Fig. 2, Fig. 3 C and Fig. 6 B, when electronic installation reverts to normal mode by battery saving mode, if when T6, there is external event to take place, then power control circuit 201 can receive the external event that comes from the outside, carry out step S321 again, forbidden energy oscillation power signal V3 produces oscillating clock signal CLK1 again.After oscillating clock signal CLK1 is stable, just shown in step S323, forbidden energy clock power signal V2 when T7, make according to oscillating clock signal CLK1 and produce work clock signal CLK2 again, this moment in the present embodiment, also forbidden energy clock resetting signal RSTCKG simultaneously makes work clock signal CLK2 to be produced again.After waiting until that again work clock CLK2 is stable, shown in step S325, forbidden energy digital power signal V1 makes according to work clock signal CLK2 and produces dagital clock signal DCLK when T8.Then carry out step S327, make the power supply of flash ROM 223 open again.
Fig. 3 D is another kind of electronic installation that another preferred embodiment of the present invention is shown is reverted to the method for normal mode by battery saving mode a process flow diagram.Please refer to Fig. 2, Fig. 3 D and Fig. 6 A, if when T4 has external event to take place, digital control circuit 201 can be accepted incoming event equally and send wake-up signal Wake.If this moment, the oscillation power signal of electronic installation was not enabled, then shown in step S331, forbidden energy digital power signal V2 makes according to oscillating clock signal CLK1 and produces dagital clock signal CLK3 again when T4.Then shown in step S333, after dagital clock signal CLK3 stablized by the time, forbidden energy clock power signal V2 produced work clock signal CLK2 again when T5, similarly, and also can while forbidden energy clock resetting signal RSTCKG at this.By the time after work clock signal CLK2 stablizes, then carry out step S335, forbidden energy selects signal SEL to select work clock signal CLK2 to produce dagital clock signal CLK3 when T6, makes digital circuit normal 221 move.
Fig. 4 A is the calcspar that illustrates according to the power-saving control circuit of the electronic installation of another embodiment of the present invention.Please refer to Fig. 4 A, oscillator (OSC) 401 produces oscillating clock signal CLK1 to frequency divider 405, traffic pilot 407 and clock generator 403.Frequency divider 405 receives oscillating clock signal CLK1 and produces sub-frequency clock signal CLK3 to multichannel converter 407, and clock generator 403 then is to receive oscillating clock signal CLK1 to produce work clock signal CLK2 to multichannel converter 407.Work clock signal CLK2 selected by traffic pilot 407 or sub-frequency clock signal CLK3 produces dagital clock signal DCLK to digital circuit 409, and digital circuit 409 is coupled to flash ROM 411.
Please continue the A with reference to Fig. 4, in the present embodiment, the battery saving mode of electronic installation is divided into standby mode and sleep pattern.When electronic installation entered standby mode, at first traffic pilot 407 produced dagital clock signal DCLK according to the oscillating clock signal CLK1 that selects signal SEL to select running clock generator 401 to be exported.And, when electronic installation enters standby mode, traffic pilot 407 (or digital circuit 409) can be sent signal with the power-off with clock generator 403, traffic pilot 407 (or digital circuit 409) also can send signal so that with the power-off of digital circuit 409 interactional flash ROMs 411 (can certainly be any internal memory that can whether close by external signal controlling).
Fig. 4 B is the calcspar that illustrates according to the micromodule of another embodiment of the present invention.Please refer to Fig. 4 B, in the present embodiment, provide a micromodule 420 to make the power-off of flash ROM 411, and micromodule 420 can design (not shown) in (shown in Fig. 4 A) or traffic pilot 407 in the digital circuit 409.In micromodule 420, can comprise for example mini program controlling unit 421 of 8051 single-chips.When electronic installation enters standby mode, mini program controlling unit 421 can be according to the microprogram unit clock signal of for example dagital clock signal DCLK, produce memory idle signal IDLE to flash ROM 411, make the power-off of flash ROM 411.Simultaneously memory idle signal IDLE enters one of them input end with door 422 by phase inverter 41, with the other end of door 422 then be to receive dagital clock signal DCLK.Can determine whether activation control signal V4 according to memory idle signal IDLE with door 422, make the power-off of mini program controlling unit 421.The feature of mini program controlling unit 421 is exactly when its power-off, if there is look-at-me INT to produce, will forbidden energy memory idle signal IDLE, and make the power supply of itself and flash ROM 411 to open again.Therefore when external incident takes place, will produce look-at-me INT, make that the power supply of flash ROM 411 can be opened again.
Referring again to Fig. 4 A, when electronic installation entered sleep pattern, traffic pilot 407 can be according to selecting signal SEL, and the sub-frequency clock signal CLK3 that selects frequency divider 403 to be produced produces dagital clock signal DCLK, then clock generator 403 is closed again.Sub-frequency clock signal CLK3 is the frequency with oscillating clock signal CLK1, is produced later divided by some positive integer N through frequency divider.In addition, digital circuit 409 (or traffic pilot 307) also can be as described in Fig. 4 B, makes the power-off of flash ROM 411.
In the present embodiment, no matter electronic installation is in standby mode or sleep pattern, the frequency of the dagital clock signal DCLK that its digital circuit 409 is received all can be very low, simultaneously also as a same embodiment, when electronic installation enters battery saving mode, can be so that the power-off of flash ROM 411.Therefore in the present embodiment, when electronic installation under battery saving mode, the loss of its electric power also can be very low.
Fig. 5 A is the process flow diagram that illustrates according to the electricity saving method of the electronic installation of another embodiment of the present invention.Embodiment among the synthesizing map 4A the invention provides the electricity saving method of another kind of electronic installation, please refer to Fig. 4 A, Fig. 5 A and Fig. 6 C, at first carries out step S510, oscillating clock signal CLK1 is produced divided oscillator signal CLK3 divided by N, and N is a positive integer.For another example shown in the step S520,, select oscillating clock signal CLK1 or sub-frequency clock signal CLK3 produces dagital clock signal DCLK according to the state of electronic installation.And when the battery saving mode of electronic installation of the present invention, shown in step S530,, can make electronic installation recover normal condition if when having external event to take place in standby mode or sleep pattern etc.In addition, in the electricity saving method of the present invention, when also being included among Fig. 6 C T3, can produce memory idle signal IDLE, can be with the power-off of flash ROM 411.
Please merge with reference to Fig. 4 A and Fig. 5 A, in step S520, when electronic installation enters standby mode, at first shown in step S522, select oscillating clock signal CLK1 to produce dagital clock signal DCLK.Then carry out step S524, stop to produce work clock signal CLK2.
Fig. 6 C is the sequential chart that illustrates according to the electronic installation power-saving control circuit of another embodiment of the present invention.Please refer to Fig. 5 A and Fig. 6 C, when electronic installation enters sleep pattern, then carry out step S526 earlier, activation selects signal SEL to produce dagital clock signal DCLK to select sub-frequency clock signal CLK3 when T1.For another example shown in the step S528, when T2, can activation for example clock power signal PDCKG and clock resetting signal RSTCKG, stop to produce work clock signal CLK2.
Fig. 5 B illustrates the process flow diagram that is reverted to the method for normal mode according to the electronic installation of yet another embodiment of the invention by sleep pattern.Please merge with reference to Fig. 5 B and Fig. 6 C, when electronic installation in standby mode or sleep pattern, if when having external event to take place, at first carry out step S541, can be in T4 produce look-at-me INT and come forbidden energy memory idle signal IDLE, make the electric power starting of flash ROM.Next shown in step S543, can forbidden energy when T5 for example clock power signal PDCKG and clock resetting signal RSTCKG, make according to oscillating clock signal CLK1 and produce work clock signal CLK2 again.By the time after work clock CLK2 stablizes, shown in step S545, when T6, can select signal SEL produce dagital clock signal DCLK by forbidden energy, make digital circuit 409 normally to move to select work clock signal CLK2.
Though the present invention with preferred embodiment openly as above; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; change and modification when doing some, so protection scope of the present invention is when being as the criterion with claims.
Claims (20)
1. the power-saving control circuit of an electronic installation, this electronic installation has a digital circuit, and this power-saving control circuit comprises:
One power control circuit produces an oscillation power signal, a clock power supply signal and a digital power signal;
One oscillator produces an oscillating clock signal, and this oscillator moves or cuts out according to described oscillation power signal;
One clock generator produces a work clock signal according to described oscillating clock signal, and moves or close according to described clock power signal; And
One multitask activation module, determine whether producing a dagital clock signal to described digital circuit according to described digital power signal, to be this multitask activation module select signal to select described work clock signal and described oscillating clock signal the two one of them and produce according to one to described dagital clock signal;
Wherein, the operation of described power control circuit is independent of described clock signal.
2. power-saving control circuit as claimed in claim 1, described electronic installation also comprises an internal memory, wherein this internal memory according to described oscillation power signal, described clock power signal and described digital power signal three wherein at least one and move or close, and described internal memory can be a flash ROM at least.
3. power-saving control circuit as claimed in claim 1, described multitask activation module comprises:
One traffic pilot receives described oscillating clock signal and described work clock signal, and according to described selection signal select described oscillating clock signal and work clock signal the two one of, produce a clock signal; And
One with door, wherein an input end receives described clock signal, another input end then receives the described digital power signal after anti-phase, and should export described dagital clock signal with the output terminal of door.
4. power-saving control circuit as claimed in claim 1, also comprise a stick holding circuit, with former belong to described digital circuit but must be when other of described digital circuit partly quits work the part of continuous firing still, separating from described digital circuit becomes this stick holding circuit, and this stick holding circuit receives described oscillating clock signal and normally moves.
5. power-saving control circuit as claimed in claim 4, when this electronic installation enters battery saving mode, and all functions in described digital circuit and the described stick holding circuit are neither needs clock signal and when out of service, the power supply of this oscillator will be closed.
6. the power-saving control circuit of an electronic installation, this electronic installation has a digital circuit, and this power-saving control circuit comprises:
One oscillator produces an oscillating clock signal;
One clock generator produces a work clock signal according to described oscillating clock signal;
One frequency divider receives described oscillating clock signal, and with the frequency of described oscillating clock signal divided by N producing a sub-frequency clock signal, and N is a positive integer; And
One traffic pilot, according to one select signal select described oscillating clock signal, described work clock signal and described sub-frequency clock signal three one of them, export a dagital clock signal to described digital circuit.
7. power-saving control circuit as claimed in claim 6, wherein, described electronic installation also has an internal memory.
8. power-saving control circuit as claimed in claim 7, also has a micromodule, when described electronic installation enters a battery saving mode, this micromodule produces a memory idle signal, and according to the operation of described dagital clock signal and the described internal memory of described memory idle signal deciding or close, described micromodule can comprise a mini program controlling unit, and described microprogram control module can merge mutually with one of following: described traffic pilot, described digital circuit.
9. it is one of following that power-saving control circuit as claimed in claim 8, described battery saving mode are selected from: a standby mode, a sleep pattern.
10. power-saving control circuit as claimed in claim 9, described traffic pilot is carried out following function at least:
When described electronic installation enters when operating under the normal condition, select described work clock signal to produce described dagital clock signal;
When this electronic installation enters described standby mode, select described work clock signal to produce described dagital clock signal; And
When described electronic installation enters described sleep pattern, select described sub-frequency clock signal to produce described dagital clock signal.
Receive the digital circuit that a dagital clock signal moves 11. the electricity saving method of an electronic installation, this electronic installation have, select a work clock signal to produce this dagital clock signal under normal condition, this electricity saving method comprises:
Activation one clock power supply signal stops to produce described work clock signal;
Activation one digital power signal stops to produce described dagital clock signal; With
When an external event takes place, recover to produce described dagital clock signal, so that described digital circuit is resumed operation with described work clock signal.
12. electricity saving method as claimed in claim 11, when described electronic installation also has an internal memory, one signal is transferred to this internal memory so that this internal memory is closed, it is one of following that this signal is selected from: described clock power signal, described digital power signal, and this internal memory can be a flash ROM.
13. electricity saving method as claimed in claim 11, can also replace described work clock signal to produce described dagital clock signal with an oscillating clock signal earlier, stop to produce described work clock signal again, the frequency of said work clock signal is greater than the frequency of described oscillating clock signal, and can activation one oscillation power signal to stop to produce described oscillating clock signal.
14. electricity saving method as claimed in claim 11 also comprises:
The part that still needs normal operation when described digital circuit inherence is not had described dagital clock signal is from the independent stick holding circuit that becomes of described digital circuit; And
Described dagital clock signal is passed to this stick holding circuit, so that this stick holding circuit normally moves, and stops described dagital clock signal is passed to described digital circuit, to close described digital circuit.
15. electricity saving method as claimed in claim 14, the process that described electronic installation is reverted to normal condition comprises the following steps:
The described digital power signal of forbidden energy is to produce described dagital clock signal;
The described clock power signal of forbidden energy is to produce described work clock signal; With
Select described work clock signal to produce described dagital clock signal, make described digital circuit normally move;
Wherein,, produce this described dagital clock signal and the process that produces described work clock signal if described electronic installation also has an internal memory, also can transmit a signal to this internal memory to open this internal memory.
16. electricity saving method as claimed in claim 13, when described oscillating clock signal stopped to produce, the process of wherein recovering described electronic installation normal condition comprised the following steps:
The described oscillation power signal of forbidden energy, the described oscillating clock signal of activation;
The described clock power signal of forbidden energy makes according to described oscillating clock signal and produces described work clock signal; And
The described digital power signal of forbidden energy, and select described work clock signal to produce described dagital clock signal;
Wherein, if described electronic installation also has an internal memory, the process of the described oscillation power signal of forbidden energy, the described clock power signal of forbidden energy and forbidden energy digital power signal, also can transmit a signal to this internal memory to open this internal memory.
Receive the digital circuit that a dagital clock signal moves 17. the electricity saving method of an electronic installation, this this electronic installation have, select a work clock signal to produce this dagital clock signal in normal condition, this electricity saving method comprises:
Divided by a positive integer N, in order to produce a sub-frequency clock signal, the frequency of this oscillating clock signal is less than the frequency of described work clock signal with the frequency of an oscillating clock signal; And
According to the state of described electronic installation select described oscillating clock signal and described sub-frequency clock signal the two one of produce described dagital clock signal, when described electronic installation enters a holding state, select to use described oscillating clock signal, when described electronic installation enters a sleep state, select to use described sub-frequency clock signal.
18. electricity saving method as claimed in claim 17, when described electronic installation also has an internal memory, this electricity saving method comprises that also the described dagital clock signal of foundation produces a memory idle signal, makes this memory power supply close, and can be a flash ROM at this this internal memory.
19. electricity saving method as claimed in claim 17 can also stop to produce described work clock signal when described electronic installation enters described standby mode or described sleep state.
20. electricity saving method as claimed in claim 17, when external event took place, the process that makes described electronic installation recover normal condition comprised the following steps:
When described electronic installation is in the state of described standby mode, comprise:
Again produce described work clock signal according to described oscillating clock signal; With
Select described work clock signal to produce described dagital clock signal again, make described digital circuit normally move;
Wherein,, produce described work clock signal and the process that produces described dagital clock signal if this electronic installation also has an internal memory, also can transmit a signal to this internal memory to open this internal memory; And
State when the described sleep pattern of described electronics process comprises:
Again produce described oscillating clock signal;
Again produce described work clock signal according to described oscillating clock signal; With
Select described work clock signal to produce described dagital clock signal again, make described digital circuit normally move;
Wherein,, produce described oscillating clock signal, described work clock signal and the process that produces described dagital clock signal if described electronic installation also has an internal memory, also can transmit a signal to this internal memory to open this internal memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310124733 CN1617067A (en) | 2003-12-26 | 2003-12-26 | Power saving control circuit for electronic device and its power saving method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310124733 CN1617067A (en) | 2003-12-26 | 2003-12-26 | Power saving control circuit for electronic device and its power saving method |
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| CN1617067A true CN1617067A (en) | 2005-05-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200310124733 Pending CN1617067A (en) | 2003-12-26 | 2003-12-26 | Power saving control circuit for electronic device and its power saving method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100511048C (en) * | 2007-10-17 | 2009-07-08 | 威盛电子股份有限公司 | Power supply management method and management system thereof |
| CN101246388B (en) * | 2007-02-14 | 2010-08-25 | 盛群半导体股份有限公司 | Microcontroller and its power-saving method |
| CN101729489B (en) * | 2008-10-14 | 2013-04-17 | 爱特梅尔汽车股份有限公司 | Circuit for a radio system, use and method for operation |
| CN103677210A (en) * | 2012-09-10 | 2014-03-26 | 三星电子株式会社 | Method of performing dynamic voltage and frequency, application processor and mobile device |
| CN111312135A (en) * | 2018-12-12 | 2020-06-19 | 奇景光电股份有限公司 | Source driver and operating method thereof |
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2003
- 2003-12-26 CN CN 200310124733 patent/CN1617067A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246388B (en) * | 2007-02-14 | 2010-08-25 | 盛群半导体股份有限公司 | Microcontroller and its power-saving method |
| CN100511048C (en) * | 2007-10-17 | 2009-07-08 | 威盛电子股份有限公司 | Power supply management method and management system thereof |
| CN101729489B (en) * | 2008-10-14 | 2013-04-17 | 爱特梅尔汽车股份有限公司 | Circuit for a radio system, use and method for operation |
| CN103677210A (en) * | 2012-09-10 | 2014-03-26 | 三星电子株式会社 | Method of performing dynamic voltage and frequency, application processor and mobile device |
| CN103677210B (en) * | 2012-09-10 | 2018-03-23 | 三星电子株式会社 | Method, application processor and mobile device for dynamic voltage frequency adjustment |
| CN111312135A (en) * | 2018-12-12 | 2020-06-19 | 奇景光电股份有限公司 | Source driver and operating method thereof |
| CN111312135B (en) * | 2018-12-12 | 2024-01-19 | 奇景光电股份有限公司 | Source driver and operation method thereof |
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