CN111263979B - 作为扩散屏障层的多层镍合金 - Google Patents

作为扩散屏障层的多层镍合金 Download PDF

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CN111263979B
CN111263979B CN201880068534.4A CN201880068534A CN111263979B CN 111263979 B CN111263979 B CN 111263979B CN 201880068534 A CN201880068534 A CN 201880068534A CN 111263979 B CN111263979 B CN 111263979B
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layer
alloy layer
alloy
niw
forming
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CN111263979A (zh
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N·戴德万德
C·D·马纳克
S·F·帕沃内
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

一种用于半导体装置的结构(200)包含铜Cu层(210)和具有Ni晶粒大小a1的第一镍Ni合金层(201)。所述结构(200)还包含具有Ni晶粒大小a2的第二Ni合金层(202)，其中a1<a2。所述第一Ni合金层(201)处于所述Cu层(210)和所述第二Ni合金层(202)之间。所述结构(200)另外包含锡Sn层(220)。所述第二Ni合金层(202)处于所述第一Ni合金层(201)和所述Sn层(220)之间。

Description

作为扩散屏障层的多层镍合金
技术领域
这涉及扩散屏障层。
背景技术
晶片凸起是板级半导体封装的要求，借此由焊料制成的凸块或球在晶片切成个别芯片之前形成于晶片上整个晶片中。由铜(Cu)和锡(Sn)的相互扩散引起的凸块电迁移失效模式是半导体装置中的突出问题。
发明内容
通过在Cu上电沉积多层镍(Ni)合金形成半导体装置。
在一个方面中，一种用于半导体装置的结构包含Cu层和具有Ni晶粒大小a1的第一Ni合金层。所述结构还包含具有Ni晶粒大小a2的第二Ni合金层，其中a1<a2。所述第一Ni合金层处于所述Cu层和所述第二Ni合金层之间。所述结构另外包含Sn层或Sn合金，例如Sn-Ag、Sn-Cu-Ag、Sn-Bi等。所述第二Ni合金层处于所述第一Ni合金层和所述Sn层之间。
在另一方面中，一种集成电路(IC)封装包含裸片和电连接到所述裸片的凸块。所述凸块包含Cu层和形成于所述Cu层上方的具有Ni晶粒大小a1的第一镍钨(NiW)层。所述凸块还包含形成于第一NiW层上方的具有Ni晶粒大小a2的第二NiW层。所述凸块另外包含形成于所述第二NiW层上方的具有Ni晶粒大小a3的第三NiW层，其中a1<a2<a3。Sn层形成于所述第三NiW层上方。
在又一方面中，一种形成集成电路封装的方法包含形成裸片；和在所述裸片上形成凸块以使得所述凸块电连接到所述裸片。形成所述凸块包含在铜Cu层上方形成具有Ni晶粒大小a1的第一镍Ni合金层。形成所述凸块还包含在所述第一Ni合金层上方形成具有Ni晶粒大小a2的第二Ni合金层，其中a1<a2。形成所述凸块另外包含在所述第二Ni合金层上方形成锡Sn层。
附图说明
图1是IC封装的侧视图。
图2是凸块的多层结构的侧视图。
图3是凸块的另一多层结构的侧视图。
图4是凸块的又一多层结构的侧视图。
图5是包含多层凸块结构的IC封装的侧视图。
图6是描绘可应用于形成半导体装置的结构的Ni合金层的反向脉冲波形的实例的绘图。
图7是说明用于形成集成电路封装的示范性方法的流程图。
图8是凸块的又一多层结构的侧视图。
图9是说明用于形成另一集成电路封装的示范性方法的流程图。
具体实施方式
在此描述中，术语“耦合”意指间接或直接的有线或无线连接。因此，如果第一装置耦合到第二装置，那么所述连接可能是通过直接连接，或通过经由其它装置和连接的间接连接。此外，在此描述中，“基于”的叙述意指“至少部分地基于”。因此，如果X基于Y，那么X可以取决于Y和任何数目的其它因素。
对半导体封装(或IC封装)的小型化的日益迫切的需求使增加每凸块的电流密度(每表面区域的电流量)成为必要。图1是具有凸块的IC封装的示意图。因此，凸块的电迁移失效模式对于确定凸块载流能力来说至关重要。电迁移是归因于导电电子和扩散金属原子之间的动量传送引起导体中的离子逐渐移动以此带来的材料传输。电迁移降低芯片的可靠性，造成连接最终丢失或电路失效。随着例如IC的电子装置中的结构大小减小，电迁移效应变得更为重要。Cu柱凸块中以及焊料凸块中的电迁移失效是归因于Cu和Sn的界面处的金属间化合物的耗尽。
Cu和Sn之间的金属间化合物(IMC)生长和空隙形成两者均会影响焊料接头可靠性，这可使接头的机械性质和电性质降级。Cu/Sn系统中的空隙形成的机制从根本上是由Cu和Sn的不平衡扩散速率所导致，其中铜的扩散速率高于Cu3Sn相中的锡的扩散速率(柯肯特尔效应)。柯肯特尔效应是由于金属原子的扩散速率的差异而发生的两种金属之间的界面运动。柯肯特尔效应具有重要的实践结果。这些实践结果中的一个是阻止或抑制在各种合金-金属接合的边界界面处形成空隙。这些空隙被称为柯肯特尔空隙。
可通过插入具有受控晶粒大小的多层的(或多层)NiW达成Cu-Sn界面处的空隙化和微裂纹消除和/或减小。通过形成Cu6Sn5(η)相来支配Cu-Sn金属间层，且使有限量的Cu3Sn(ε)形成为Cu表面处的非连续层。一般来说，η相展示具有类似于ε岛的图案的大面积扇形边。柯肯特尔空隙通常以Cu3Sn相主要存在于Cu-Cu3Sn界面的邻近处和界面自身上，且只要是存在足够的Cu源，Cu3Sn层就以Cu6Sn5为代价生长。因此，在Cu-Sn界面处插入中间扩散屏障层可减小和/或消除Cu和Sn的相互扩散。当Ni独自用作扩散屏障层时，在Sn和Ni界面处形成Ni3Sn4的脆性金属间化合物，这加剧可靠性问题。使经溶解Cu存在于Ni3Sn4中会减缓金属间生长。然而，Cu的量需要小到足以形成(Cu,Ni)3Sn4。存在过多Cu会引起形成具有Cu6Sn5化学计量的Cu/Ni金属间化合物，产生大面积的扇形边。
具有受控晶粒结构的多个NiW层作为扩散屏障层的脉冲式电沉积是这些问题的解决方案。公开通过反向脉冲电沉积在Cu和Sn界面处的NiW界面连接，其中可使用特定镀覆化学方法以及反向脉冲波形精确地控制经电沉积NiW的Ni晶粒大小。使用此反向脉冲镀覆，混合阳极和阴极脉冲或波形，其中阴极脉冲后跟阳极脉冲。
通过电沉积应用多个NiW层，其中第一层301(图4)具有晶粒大小a1，第二层402具有晶粒大小a2，且第三层403(如果采用)具有晶粒大小a3，其中a1<a2<a3。某一量的共沉积W溶解于Ni晶粒的晶体结构中，且剩余量的共沉积W在Ni的晶粒边界处隔离。共沉积W的含量(重量％)(即，相对于整个NiW层)与颗粒的大小呈负相关。因此，通过精确控制共沉积W，有可能精确地控制Ni的晶粒大小。共沉积钨(W)的量取决于所应用的反向脉冲波形的类型；这意味着阴极和阳极电流密度以及其脉冲持续时间影响共沉积钨的量。共沉积钨的含量影响镍(Ni)晶粒的大小。因此，通过精确控制阳极和阴极电流密度和其脉冲持续时间，有可能精确地控制镍(Ni)的晶粒大小。Ni的晶粒边界处的W的隔离阻挡Cu通过晶粒边界路径的扩散。而且，具有较大晶粒大小的较高层(如图4中定向)内的Ni具有朝向具有较小晶粒大小的层扩散的趋势。因此，层403中的Ni具有朝向层402扩散的趋势且层402中的Ni具有朝向层401扩散的趋势。这预期会减缓或消除归因于朝向下方层扩散的趋势引起的从层403到Sn层的Ni扩散。另一方面，预期Ni晶粒边界处的经隔离W将减缓或消除脆性Ni3Sn4金属间化合物的形成。
在Cu-Sn界面处插入多层NiW解决上述问题。执行多层沉积过程，其中以从Cu层开始逐渐增加Ni晶粒大小的方式沉积NiW层。这尤其引起Ni的晶粒边界处的W隔离，进而改进电迁移性能。
反向脉冲电沉积会减缓或消除原本会在Sn和Ni的界面处形成的脆性Ni3Sn4金属间层的形成。
Ni晶粒边界中的W隔离会减缓或消除通过晶粒边界路径的Cu扩散，从而形成与单独的Ni相比更高效的扩散屏障。
精确控制晶粒大小的多层NiW沉积允许强制使Ni扩散方向朝向具有较小晶粒大小的下层NiW层(即，在朝向Cu层的方向上)。这使得朝向Sn层的Ni扩散减缓或消除，因此减小任何可能形成的在性质上为脆性的Ni3Sn4金属间化合物的厚度。另一方面，Ni在Cu中的固体溶解度将在第一NiW层401和Cu层410界面(图4)处提供良好粘附性。
反向脉冲电沉积允许调整Ni晶粒大小，因此强制Ni扩散与朝向Sn层相比更多地朝向下层NiW层。
反向脉冲电沉积允许精确控制Ni的晶粒生长和被隔离W的精确量。反向脉冲电沉积还允许在镀覆期间以逐渐增加镍的晶粒大小的方式电沉积多个NiW层，因而强制Ni扩散朝向其具有较小Ni晶粒大小的下层NiW(例如，朝向图2和3中的下部Ni合金层，或图4中的下部NiW层)。
图2-4尤其示出凸块的多层结构内的特定晶粒大小布置。
参考图2，在一个方面中，半导体装置的结构200包含Cu层210和具有Ni晶粒大小a1的第一Ni合金层201。结构200还包含具有Ni晶粒大小a2的第二Ni合金层202，其中a1<a2。第一Ni合金层201处于Cu层210和第二Ni合金层202之间。结构200另外包含Sn层220。Sn层220可任选地包含Sn合金，例如Sn-Ag、Sn-Cu-Ag、Sn-Bi等。第二Ni合金层202处于第一Ni合金层201和Sn层220之间。
在实例中，第一Ni合金层201和第二Ni合金层202各自包括选自由以下组成的群组的至少一个元素：钨(W)、钼(Mo)、来自镧系元素族的元素，以及其组合。
在实例中，存在第一Ni合金层201内的至少一个元素的重量％(x1)，存在第二Ni合金层202内的至少一个元素的重量％(x2)，且其中x1>x2。
在实例中，第一Ni合金层201可形成于Cu层210上方，且Sn层220可形成于第二Ni合金层202上方。
在实例中，第一Ni合金层201中的至少一个元素中的一些和第二Ni合金层202中的至少一个元素中的一些溶解于Ni晶粒中，而第一Ni合金层201中的至少一个元素的剩余部分和第二Ni合金层202中的至少一个元素的剩余部分在Ni晶粒的边界处隔离。
在实例中，第一Ni合金层201包括NiW。
在实例中，第二Ni合金层202包括NiW。
在实例中，第一Ni合金层201包括NiCe、NiLa、NiMo、NiMoW或NiWCe。
在实例中，第二Ni合金层202包括NiCe、NiLa、NiMo、NiMoW或NiWCe。
参考图3，在另一方面中，半导体装置的结构300包含Cu层310和具有Ni晶粒大小a1的第一Ni合金层301。结构300还包含具有Ni晶粒大小a2的第二Ni合金层302，其中a1<a2。第一Ni合金层301处于Cu层310和第二Ni合金层302之间。结构300另外包含具有Ni晶粒大小a3的第三Ni合金层303，其形成于第二Ni合金层302上方，且Sn层320形成于第三Ni合金层303上方，其中a1<a2<a3。
在实例中，第一Ni合金层301、第二Ni合金层302和第三Ni合金层303各自包括选自由以下组成的群组的至少一个元素：钨(W)、钼(Mo)、来自镧系元素族的元素，以及其组合。存在第一Ni合金层301内的至少一个元素的重量％(x1)，存在第二Ni合金层302内的至少一个元素的重量％(x2)，存在第三Ni合金层303内的至少一个元素的重量％(x3)，且其中x1>x2>x3。
参考图4，在另一方面中，半导体装置的结构400包含Cu层410和形成于Cu层410上方的具有Ni晶粒大小a1的第一镍钨(NiW)层401，结构400还包含形成于第一NiW层401上方的具有Ni晶粒大小a2的第二NiW层402。结构400另外包含形成于第二NiW层402上方的具有Ni晶粒大小a3的第三NiW层403，其中a1<a2<a3。Sn层420形成于第三NiW层403上方。
参考图5，在另一方面中，IC封装/裸片包含多层凸块(还在图4中示出)。特定返回参考图4，多层凸块400包含Cu层410和形成于Cu层410上方的具有Ni晶粒大小a1的第一镍钨(NiW)层401。凸块400还包含形成于第一NiW层401上方的具有Ni晶粒大小a2的第二NiW层402。凸块400另外包含形成于第二NiW层402上方的具有Ni晶粒大小a3的第三NiW层403，其中a1<a2<a3。Sn层420形成于第三NiW层403上方。
在实例中，存在第一NiW层401内的W的重量％(x1)，存在第二NiW层402内的W的重量％(x2)，且存在第三NiW层403内的W的重量％(x3)，且其中x1>x2>x3。
在实例中，第一NiW层401和/或第二NiW层402包括来自镧系元素族的元素。
在实例中，第一NiW层401、第二NiW层402和第三NiW层403中的一些W溶解于Ni晶粒中，而第一NiW层401、第二NiW层402和第三NiW层403中的W的剩余部分在Ni晶粒的边界处被隔离。
参考图7，在又一方面中，形成集成电路封装的方法700包含形成裸片(框702)和在裸片上形成凸块以使得凸块电连接到裸片(框704)。形成凸块包含在Cu层上方形成具有Ni晶粒大小a1的第一Ni合金层。形成凸块还包含在第一Ni合金层上方形成具有Ni晶粒大小a2的第二Ni合金层，其中a1<a2。形成凸块另外包含在第二Ni合金层上方形成Sn层。
在方法的实例中，第一Ni合金层和第二Ni合金层各自包括选自由以下组成的群组的至少一个元素：钨(W)、钼(Mo)、来自镧系元素族的元素，以及其组合。
在方法的实例中，存在第一Ni合金层内的至少一个元素的重量％(x1)，存在第二Ni合金层内的至少一个元素的重量％(x2)，且其中x1>x2。
在方法的实例中，经由反向脉冲电沉积过程执行第一Ni合金层和第二Ni合金层的形成。
在任选过程步骤中(并且参考图8和9)，一旦形成多个Ni合金层，并且在其上形成Sn层之前，可将结构在约4-5小时的时段内加热到介于约100-200℃之间的温度。此任选过程步骤将多个Ni合金层熔融或融合在一起，进而形成单个Ni合金层。此单个Ni合金层作为整体实际上具有与多个Ni合金层的性质大体上类似的性质(例如，Ni晶粒大小的方位和分布和W含量重量％)。在图8中示出所得结构。
参考图8，在另一方面中，半导体装置的结构800包含Cu层810和具有Ni晶粒大小a1和a2的Ni合金层801，其中a1<a2。结构800另外包含Sn层820。Sn层820可任选地包含Sn合金，例如Sn-Ag、Sn-Cu-Ag、Sn-Bi等。Ni合金层801处于Cu层810和Sn层820之间。
在实例中，Ni合金层内的大小a1的Ni晶粒与Sn层相比显著更接近Cu层，且Ni合金层内的大小a2的Ni晶粒与Cu层相比显著更接近Sn层。
在实例中，Ni晶粒大小a1的直径介于1nm和100nm之间，且Ni晶粒大小a2的直径介于2nm和100nm之间。
在实例中，Ni合金层包括选自由以下组成的群组的至少一个元素：钨(W)、钼(Mo)、来自镧系元素族的元素，以及其组合。
在实例中，存在Ni合金层内的至少一个元素的重量％(x1)，存在Ni合金层内的至少一个元素的重量％(x2)，且其中x1>x2。
在实例中，Ni合金层内的x1下的至少一个元素与Cu层相比显著更接近Sn层，且Ni合金层内的x2下的至少一个元素与Sn层相比显著更接近Cu层。
在实例中，Ni合金层内的x1下的至少一个元素中的一些和Ni合金层内的x2下的至少一个元素中的一些溶解于Ni晶粒中，而Ni合金层内的x1下的至少一个元素的剩余部分和Ni合金层内的x2下的至少一个元素的剩余部分在Ni晶粒的边界处被隔离。
在实例中，Ni合金层包括NiW。
在实例中，Ni合金层包括NiCe、NiLa、NiMo、NiMoW或NiWCe。
参考图9，在又一方面中，形成集成电路封装的方法900包含形成裸片(框902)和在裸片上形成凸块以使得凸块电连接到裸片(框904)。形成凸块包含形成铜(Cu)层。形成凸块还包含形成具有Ni晶粒大小a1和a2的镍(Ni)合金层，其中a1<a2。形成凸块另外包含形成锡(Sn)层，其中Ni合金层处于Cu层和Sn层之间。
在方法的实例中，Ni合金层内的大小a1的Ni晶粒与Sn层相比显著更接近Cu层，且Ni合金层内的大小a2的Ni晶粒与Cu层相比显著更接近Sn层。
在方法的实例中，Ni合金层包括选自由以下组成的群组的至少一个元素：钨(W)、钼(Mo)、来自镧系元素族的元素，以及其组合。
在方法的实例中，存在Ni合金层内的至少一个元素的重量％(x1)，存在Ni合金层内的至少一个元素的重量％(x2)，且其中x1>x2。
在方法的实例中，Ni合金层内的x1下的至少一个元素与Cu层相比显著更接近Sn层，且Ni合金层内的x2下的至少一个元素与Sn层相比显著更接近Cu层。
在方法的实例中，形成Ni合金层包括在形成Sn层之前，将多个经预热Ni合金层加热和熔融在一起。
反向脉冲镀覆
以下实例描述反向脉冲电沉积过程，尤其包含电流密度和脉冲持续时间特性。在脉冲反向镀覆(PRP)中，电势电压和/或电流在阴极脉冲和阳极脉冲之间交替。阴极脉冲和阳极脉冲表征为其幅度(峰值电压和/或峰值电流密度)和脉冲持续时间。每一脉冲可由期间所应用电流为零的关断时间(TOFF)组成。图6是描绘在方面中的任一个中可应用于在Cu层和Sn层之间形成Ni合金层的反向脉冲波形的实例的标绘图600。Cu层和Sn层以及中间Ni合金层的组合形成半导体装置的结构。如图6中可见，每一阴极脉冲由以下组成：期间应用负电势和/或负电流的接通时间脉冲持续时间(TON,cathodic)，以及期间应用零电流的关断时间(TOFF,cathodic)。每一阳极脉冲由以下组成：期间应用正电势和/或正电流的接通时间脉冲持续时间(TON,anodic)，以及期间应用零电流的关断时间(TOFF,anodic)。
可通过调节脉冲幅度和宽度按原子次序控制沉积的膜成分(例如，NiW合金的电沉积中的共沉积W的含量(重量％))，促进晶粒晶核的起始并且极大地增加每单位面积的晶粒的数目，因而引起与直流电(DC)镀覆的涂层相比具有更好性质的更细微粒度沉积。
浴液(即，镀覆液)中的高电流密度区域与低电流密度区域相比更多地耗尽离子。在TOFF期间，离子迁移到浴液中的被耗尽区域。因此，在TON期间，更均匀分布的离子可用于电沉积。
下表1和表2展示可用于分别沉积第一NiW层和第二NiW层的波形的实例。使用方程式1计算平均电流密度(IAverage)。
IAverage＝(ICathodic,ON x TCathodic,ON-Ianodic,ON x TAnodic,ON)/(TCathodic,ON+TCathodic,OFF+TAnodic,ON+TAnodic,OFF) (方程式1)
表1.用于沉积第一NiW层的脉冲波形特性。
脉冲表征 符号 值
阴极脉冲幅度(电流密度) ICathodic,ON 0.5A/cm2
在接通时间期间的阴极脉冲持续时间 TCathodic,ON 20ms
阴极关断时间 tCathodic,OFF 0
阳极脉冲幅度(电流密度) IAnodic,ON 0.3A/cm2
在接通时间期间的阳极脉冲持续时间 TAnodic,ON 13ms
阳极关断时间 TAnodic,OFF 0
平均电流密度 IAverage 0.185A/cm2
表2.用于沉积第二NiW层的脉冲波形特性。
脉冲表征 符号 值
阴极脉冲幅度(电流密度) ICathodic,ON 0.5A/cm2
在接通时间期间的阴极脉冲持续时间 TCathodic,ON 20ms
阴极关断时间 tCathodic,OFF 0
阳极脉冲幅度(电流密度) IAnodic,ON 0.4A/cm2
在接通时间期间的阳极脉冲持续时间 TAnodic,ON 15ms
阳极关断时间 TAnodic,OFF 0
平均电流密度 IAverage 0.114A/cm2
下表3和表4展示可用于分别沉积第一NiW层和第二NiW层的波形的另一实例。使用方程式1计算平均电流密度(IAverage)。
表3.用于沉积第一NiW层的脉冲波形特性。
脉冲表征 符号 值
阴极脉冲幅度(电流密度) ICathodic,ON 0.6A/cm2
在接通时间期间的阴极脉冲持续时间 TCathodic,ON 20ms
阴极关断时间 tCathodic,OFF 1
阳极脉冲幅度(电流密度) IAnodic,ON 0.4A/cm2
在接通时间期间的阳极脉冲持续时间 TAnodic,ON 13ms
阳极关断时间 TAnodic,OFF 0.2
平均电流密度 IAverage 0.199A/cm2
表4.用于沉积第二NiW层的脉冲波形特性。
这些各个方面的实例优点包含更好的防腐蚀性、更好的扩散屏障、沉积的晶粒大小的精确控制、对合金化元素(例如，W)的隔离的量的更好控制、合理的成本，和/或从实验室规模容易地扩展生产规模。
虽然实例在上文参考W描述为NiW层内的合金化元素，但可在上述实例中的任一个中替代地采用例如Ce、La、Mo、MoW或WCe等其它合金化元素/成分。这类替代方案被视为在本说明书的精神和范围内，且因而可使用上文所描述的配置和实例的优点。
而且，虽然实例在上文参考具有两个或三个Ni合金层的结构进行描述，但可在上述实例中的任一个中替代地采用在Cu层和Sn层之间具有多于三个Ni合金层的结构。这类替代方案被视为在本说明书的精神和范围内，且因而可使用上文所描述的配置和实例的优点。
本文中所描述的任何实施例中的方法步骤不局限于按任何特定次序执行。而且，方法实施例中的任一个中提及的结构可使用在装置实施例中的任一个中提及的结构。这类结构可仅相对于装置实施例进行详细地描述但适用于方法实施例中的任一个。
本文中所描述的任何实施例中的特征可结合本文中所描述的其它实施例中的特征采用，且这类组合在本说明书的精神和范围内。
在所描述的实施例中可能进行修改，且其它实施例在权利要求书的范围内是可能的。

Claims (29)

1.一种用于半导体装置的结构，所述结构包括：
铜Cu层；
具有镍Ni晶粒大小a1的第一Ni合金层；
具有Ni晶粒大小a2的第二Ni合金层，其中a1<a2，且其中所述第一Ni合金层处于所述Cu层和所述第二Ni合金层之间；和
锡Sn层，其中所述第二Ni合金层处于所述第一Ni合金层和所述Sn层之间，
其中所述第一Ni合金层和所述第二Ni合金层各自包括选自由以下组成的群组的至少一个元素：钨W、钼Mo、来自镧系元素族的元素，以及其组合。
2.根据权利要求1所述的结构，其中所述第一Ni合金层内的所述至少一个元素的重量％为x1，所述第二Ni合金层内的所述至少一个元素的重量％为x2，且其中x1>x2。
3.根据权利要求1所述的结构，其中所述第一Ni合金层形成于所述Cu层上方。
4.根据权利要求1所述的结构，其中所述Sn层形成于所述第二Ni合金层上方。
5.根据权利要求1所述的结构，其中所述第一Ni合金层中的所述至少一个元素中的一些和所述第二Ni合金层中的所述至少一个元素中的一些溶解于所述Ni晶粒中，而所述第一Ni合金层中的所述至少一个元素的剩余部分和所述第二Ni合金层中的所述至少一个元素的剩余部分在所述Ni晶粒的边界处被隔离。
6.根据权利要求1所述的结构，其中所述第一Ni合金层包括NiW。
7.根据权利要求1所述的结构，其中所述第二Ni合金层包括NiW。
8.根据权利要求1所述的结构，其中所述第一Ni合金层包括NiCe、NiLa、NiMo、NiMoW或NiWCe。
9.根据权利要求1所述的结构，其中所述第二Ni合金层包括NiCe、NiLa、NiMo、NiMoW或NiWCe。
10.根据权利要求1所述的结构，其另外包括形成于所述第二Ni合金层上方的具有Ni晶粒大小a3的第三Ni合金层，且所述Sn层形成于所述第三Ni合金层上方，其中
a1<a2<a3。
11.根据权利要求10所述的结构，其中所述第一Ni合金层、所述第二Ni合金层和所述第三Ni合金层各自包括选自由以下组成的群组的至少一个元素：钨W、钼Mo、来自镧系元素族的元素，以及其组合；且
其中所述第一Ni合金层内的所述至少一个元素的重量％为x1，所述第二Ni合金层内的所述至少一个元素的重量％为x2，所述第三Ni合金层内的所述至少一个元素的重量％为x3，且其中x1>x2>x3。
12.一种集成电路封装，其包括：
裸片；和
凸块，其电连接到所述裸片，所述凸块包括：
铜Cu层；
第一镍钨NiW层，其具有Ni晶粒大小a1，形成于所述Cu层上方；
第二NiW层，其具有Ni晶粒大小a2，形成于所述第一NiW层上方；
第三NiW层，其具有Ni晶粒大小a3，形成于所述第二NiW层上方，其中
a1<a2<a3；和
锡Sn层，其形成于所述第三NiW层上方。
13.根据权利要求12所述的集成电路封装，其中所述第一NiW层内的所述W的重量％为x1，所述第二NiW层内的所述W的重量％为x2，且所述第三NiW层内的所述W的重量％为x3，且其中x1>x2>x3。
14.根据权利要求12所述的集成电路封装，其中所述第一NiW层和所述第二NiW层包括来自镧系元素族的元素。
15.根据权利要求12所述的集成电路封装，其中所述第一NiW层、第二NiW层和第三NiW层中的一些W溶解于所述Ni晶粒中，而所述第一NiW层、第二NiW层和第三NiW层中的所述W的剩余部分在所述Ni晶粒的边界处被隔离。
16.一种形成集成电路封装的方法，所述方法包括：
形成裸片；和
在所述裸片上形成凸块以使得所述凸块电连接到所述裸片，所述形成所述凸块包括：
在铜Cu层上方形成具有Ni晶粒大小a1的第一Ni合金层；
在所述第一Ni合金层上方形成具有Ni晶粒大小a2的第二Ni合金层，其中a1<a2；和
在所述第二Ni合金层上方形成锡Sn层,
其中所述第一Ni合金层和所述第二Ni合金层各自包括选自由以下组成的群组的至少一个元素：钨W、钼Mo、来自镧系元素族的元素，以及其组合。
17.根据权利要求16所述的方法，其中所述第一Ni合金层内的所述至少一个元素的重量％为x1，所述第二Ni合金层内的所述至少一个元素的重量％为x2，且其中x1>x2。
18.根据权利要求16所述的方法，其中经由反向脉冲电沉积过程执行所述第一Ni合金层和所述第二Ni合金层的所述形成。
19.一种用于半导体装置的结构，所述结构包括：
铜Cu层；
镍Ni合金层，其具有Ni晶粒大小a1和a2，其中a1<a2；和
锡Sn层，其中所述Ni合金层处于所述Cu层和所述Sn层之间，
其中所述Ni合金层内的大小a1的所述Ni晶粒与所述Sn层相比更接近所述Cu层，且所述Ni合金层内的大小a2的所述Ni晶粒与所述Cu层相比更接近所述Sn层，以及
其中所述Ni合金层包括选自由以下组成的群组的至少一个元素：钨W、钼Mo、来自镧系元素族的元素，以及其组合。
20.根据权利要求19所述的结构，其中所述Ni晶粒大小a1的直径介于1nm和100nm之间，且所述Ni晶粒大小a2的直径介于2nm和100nm之间。
21.根据权利要求19所述的结构，其中所述Ni合金层内的所述至少一个元素的重量％为x1，所述Ni合金层内的所述至少一个元素的重量％为x2，且其中x1>x2。
22.根据权利要求21所述的结构，其中所述Ni合金层内的x1下的所述至少一个元素与所述Cu层相比更接近所述Sn层，且所述Ni合金层内的x2下的所述至少一个元素与所述Sn层相比更接近所述Cu层。
23.根据权利要求21所述的结构，其中所述Ni合金层内的x1下的所述至少一个元素中的一些和所述Ni合金层内的x2下的所述至少一个元素中的一些溶解于所述Ni晶粒中，而所述Ni合金层内的x1下的所述至少一个元素的剩余部分和所述Ni合金层内的x2下的所述至少一个元素的剩余部分在所述Ni晶粒的边界处被隔离。
24.根据权利要求19所述的结构，其中所述Ni合金层包括NiW。
25.根据权利要求19所述的结构，其中所述Ni合金层包括NiCe、NiLa、NiMo、NiMoW或NiWCe。
26.一种形成集成电路封装的方法，所述方法包括：
形成裸片；和
在所述裸片上形成凸块以使得所述凸块电连接到所述裸片，所述形成所述凸块包括：
形成铜Cu层；
形成具有Ni晶粒大小a1和a2的镍Ni合金层，其中a1<a2；和
形成锡Sn层，其中所述Ni合金层处于所述Cu层和所述Sn层之间，
其中所述Ni合金层内的大小a1的所述Ni晶粒与所述Sn层相比更接近所述Cu层，且所述Ni合金层内的大小a2的所述Ni晶粒与所述Cu层相比更接近所述Sn层，以及
其中所述Ni合金层包括选自由以下组成的群组的至少一个元素：钨W、钼Mo、来自镧系元素族的元素，以及其组合。
27.根据权利要求26所述的方法，其中所述Ni合金层内的所述至少一个元素的重量％为x1，所述Ni合金层内的所述至少一个元素的重量％为x2，且其中x1>x2。
28.根据权利要求27所述的方法，其中所述Ni合金层内的x1下的所述至少一个元素与所述Cu层相比更接近所述Sn层，且所述Ni合金层内的x2下的所述至少一个元素与所述Sn层相比更接近所述Cu层。
29.根据权利要求26所述的方法，其中所述形成所述Ni合金层包括在所述形成所述Sn层之前，将多个经预热Ni合金层加热和熔融在一起。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
US11011483B2 (en) * 2018-02-21 2021-05-18 Texas Instruments Incorporated Nickel alloy for semiconductor packaging
US10903151B2 (en) * 2018-05-23 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086183A (ja) * 2004-09-14 2006-03-30 Shindengen Electric Mfg Co Ltd ＳｉＣ半導体装置およびＳｉＣ半導体装置の製造方法
CN101379618A (zh) * 2006-02-03 2009-03-04 德州仪器公司 具有改进的焊料接合的半导体装置
CN101903566A (zh) * 2007-12-20 2010-12-01 英特格兰科技公司 具有可变性质的金属性结构
CN104051381A (zh) * 2013-03-14 2014-09-17 国际商业机器公司 用于改善电迁移的球下金属结构及其形成方法
CN204067341U (zh) * 2014-07-25 2014-12-31 颀邦科技股份有限公司 具有凸块结构的基板

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG107600A1 (en) 2002-06-27 2004-12-29 Agency Science Tech & Res Multilayer substrate metallization for ic interconnection
CN100428414C (zh) 2005-04-15 2008-10-22 中芯国际集成电路制造(上海)有限公司 形成低应力多层金属化结构和无铅焊料端电极的方法
WO2008013516A2 (en) * 2005-05-13 2008-01-31 Cambrios Technologies Corp. Seed layers, cap layers, and thin films and methods of making thereof
US7425255B2 (en) * 2005-06-07 2008-09-16 Massachusetts Institute Of Technology Method for producing alloy deposits and controlling the nanostructure thereof using negative current pulsing electro-deposition
US8269345B2 (en) * 2007-10-11 2012-09-18 Maxim Integrated Products, Inc. Bump I/O contact for semiconductor device
EP2287899B1 (de) * 2009-08-18 2014-05-07 SEMIKRON Elektronik GmbH & Co. KG Lötverbindung mit einer mehrlagigen lötbaren Schicht und entsprechendes Herstellungsverfahren
US8293643B2 (en) 2010-06-21 2012-10-23 International Business Machines Corporation Method and structure of forming silicide and diffusion barrier layer with direct deposited film on silicon
US8268716B2 (en) * 2010-09-30 2012-09-18 International Business Machines Corporation Creation of lead-free solder joint with intermetallics
JP2012191123A (ja) * 2011-03-14 2012-10-04 Renesas Electronics Corp 半導体集積回路装置およびその製造方法ならびにそれを用いた電子システム
US8610285B2 (en) * 2011-05-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC packaging structures and methods with a metal pillar
KR101359733B1 (ko) 2011-12-16 2014-02-11 성균관대학교산학협력단 반도체 3차원 적층공정에서의 이중 확산방지층을 포함하는 범프 및 그 제조방법
US9673132B2 (en) 2012-04-27 2017-06-06 Taiwan Semiconductor Manufacting Company, Ltd. Interconnection structure with confinement layer
US9147663B2 (en) 2013-05-28 2015-09-29 Intel Corporation Bridge interconnection with layered interconnect structures
US9741682B2 (en) * 2015-12-18 2017-08-22 International Business Machines Corporation Structures to enable a full intermetallic interconnect
US20170253008A1 (en) 2016-02-16 2017-09-07 Xtalic Corporation Articles including a multi-layer coating and methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086183A (ja) * 2004-09-14 2006-03-30 Shindengen Electric Mfg Co Ltd ＳｉＣ半導体装置およびＳｉＣ半導体装置の製造方法
CN101379618A (zh) * 2006-02-03 2009-03-04 德州仪器公司 具有改进的焊料接合的半导体装置
CN101903566A (zh) * 2007-12-20 2010-12-01 英特格兰科技公司 具有可变性质的金属性结构
CN104051381A (zh) * 2013-03-14 2014-09-17 国际商业机器公司 用于改善电迁移的球下金属结构及其形成方法
CN204067341U (zh) * 2014-07-25 2014-12-31 颀邦科技股份有限公司 具有凸块结构的基板

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Sliding wear of nanocrystalline Ni-W: Structural evolution and the apparent breakdown of Archard scaling;Timothy J. Rupert;《Acta Materialia》;20100405;第4137-4148页 *
组分调制Cu/Ni多层膜的合金化及其合金化镀层的耐蚀特性;骆立立;费敬银;王磊;林西华;王少兰;;中国腐蚀与防护学报(第06期) *
骆立立 ; 费敬银 ; 王磊 ; 林西华 ; 王少兰 ; .组分调制Cu/Ni多层膜的合金化及其合金化镀层的耐蚀特性.中国腐蚀与防护学报.2014,(第06期), *

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